DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-15 in the reply filed on 10/24/25 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eid(USPGPUB DOCUMENT: 2020/0194335, hereinafter Eid) in view of Kim (USPGPUB DOCUMENT: 2017/0207205, hereinafter Kim).
Re claim 1 Eid discloses an electronic assembly, comprising: a substrate(901); a first die(905/906) with first and second opposing surfaces, wherein the first die(905/906) is coupled to the substrate(901) at the first surface(bottom); a stiffener(902/902c/902d/925)[0041] attached to the substrate(901), the stiffener(902/902c/902d/925)[0041] having a cavity that accommodates the first die(905/906), wherein the second surface(top) of the first die(905/906) faces the stiffener(902/902c/902d/925)[0041]; and a thermally conductive layer(930/910) positioned in the cavity between the stiffener(902/902c/902d/925)[0041] and the first die(905/906).
Eid does not disclose at least one first trench extending partially through the first die(905/906) from the second surface(top); and a thermally conductive layer(930/910) positioned in the cavity between the stiffener(902/902c/902d/925)[0041] and the first die(905/906) and at least partially filling the at least one first trench.
Kim disclose in Fig 5B at least one first trench(380) extending partially through the first die(300) from the second surface(top); and a thermally conductive layer(ML/MLP) at least partially filling the at least one first trench(380).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Kim to the teachings of Eid in order to enhance the operational reliability of the first semiconductor chip [0071, Kim]. In doing so, a thermally conductive layer(ML/MLP of Kim) positioned in the cavity between the stiffener(902/902c/902d/925 of Eid) and the first die(300 of Kim) and at least partially filling the at least one first trench(380 of Kim).
Re claim 2 Eid and Kim disclose the electronic assembly of claim 1, wherein the first die(905/906) has a first footprint and the cavity of the stiffener(902/902c/902d/925)[0041] has a second footprint, and wherein the conductive layer extends across the second footprint between the stiffener(902/902c/902d/925)[0041] and the second surface(top) of the first die(905/906).
Re claim 3 Eid and Kim disclose the electronic assembly of claim 1, wherein the conductive layer is a liquid metal[0042].
Re claim 4 Eid and Kim disclose the electronic assembly of claim 3, wherein the liquid metal[0042] comprises metal alloy composites of at least one of tin, indium, gallium, francium, cesium, and rubidium[0042].
Re claim 5 Eid and Kim disclose the electronic assembly of claim 1, further comprising a dielectric layer(610)[0092 of Kim] positioned in the cavity over the conductive layer and around the first die(905/906), wherein the dielectric layer(610)[0092 of Kim] holds the conductive layer intact to the stiffener(902/902c/902d/925)[0041].
Re claim 6 Eid and Kim disclose the electronic assembly of claim 5, wherein the dielectric layer(610)[0092 of Kim] comprises an epoxy polymer layer, a polyimide layer, a mold compound layer, or a silicone layer.
Re claim 7 Eid and Kim disclose the electronic assembly of claim 1, wherein the stiffener(902/902c/902d/925)[0041] is formed of a conductive material.
Re claim 8 Eid and Kim disclose the electronic assembly of claim 1, wherein the stiffener(902/902c/902d/925)[0041] and the conductive layer is coupled to a reference voltage.
Re claim 9 Eid and Kim disclose the electronic assembly of claim 1, wherein the at least one first trench(380 of Kim) comprises a plurality of columns(see Fig 5B of Kim).
Re claim 10 Eid and Kim disclose the electronic assembly of claim 1, wherein the at least one first trench(380 of Kim) comprises a first inner ring trench with a first inner trench footprint and a first outer ring trench with a first outer trench footprint, the first outer trench footprint being greater than the first inner trench footprint.
Re claim 11 Eid and Kim disclose the electronic assembly of claim 1, further comprising:a second die(905/906) adjacent to the first die(905/906), the second die(905/906) includes first and second opposing surfaces; and at least one second trench(380 of Kim) extending partially through the second die(905/906) from the second surface(top) of the second die(905/906).
Re claim 12 Eid and Kim disclose the electronic assembly of claim 11, wherein the first and second die(905/906)s are encapsulated within a mold layer(400)[0052 of Kim] with a first footprint, the cavity of the stiffener(902/902c/902d/925)[0041] has a second footprint, and wherein the conductive layer extends across the second footprint between the stiffener(902/902c/902d/925)[0041] and the second surface(top) of the first die(905/906) and the second surface(top) of the second die(905/906), and wherein the conductive layer further at least partially fills the at least one second trench(380 of Kim).
Re claim 13 Eid and Kim disclose the electronic assembly of claim 12, further comprising a dielectric layer(610)[0092 of Kim] positioned in the cavity over the conductive layer and around the mold layer(400)[0052 of Kim], wherein the dielectric layer(610)[0092 of Kim] holds the conductive layer intact to the stiffener(902/902c/902d/925)[0041].
Re claim 14 Eid and Kim disclose the electronic assembly of claim 11, wherein the first die(905/906) comprises a central processing unit (CPU)[0070 of Kim].
Re claim 15 Eid and Kim disclose the electronic assembly of claim 14, wherein the second die(905/906) comprises a graphic processing unit (GPU), a neural processing unit (NPU), a deep learning processor (DLP), a system-on-chip (SOC), a memory device, a field programmable gate array (FGPA) or an 1/0 tile[0159].
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812