DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 02/06/2026 has been entered. Applicant's amendments have overcome the objections to the Claims and 112 (b) rejections previously set forth in the Non-Final Office Action dated on 11/28/2025.
Response to Arguments
Applicant's arguments "Applicant Arguments/Remarks Made in an Amendment" with the
"Amendment/Req. Reconsideration-After Non-Final Reject" filed on 02/06/2026, have been fully considered, the arguments are not persuasive and some of them are moot because do not apply to new ground of rejections with a new reference, US 20200006246 A1 to Kong, being used in the current rejection, see detail below.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1,5-6,8-9,11 and 12 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kong et al. (US 20200006246 A1, hereinafter Kong) in view of Kang et al. (US 20060012019 A1, hereinafter Kang, of the record).
Re: Independent Claim 1, Kong discloses a semiconductor package comprising: a package
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Kong’s Figure 1-Annotated.
substrate (118 a package substrate in [0019], Fig. 1) with a top surface
(top surface-118, Fig. 1-Annotated), wherein the top surface (top surface-118) extends to a peripheral side surface (side surface-118, Fig. 1-Annotated) of the package substrate (118);
a stiffener (110 a frame stiffener in [0019], Fig. 1) with a lateral portion (110-lateral, Fig. 1-Annotated) and a basket portion (110-basket, Fig. 1-Annotated), wherein the lateral portion (110-lateral) is positioned over the top surface (top surface-118) of the package substrate (118) and the basket portion (110-basket) overhangs (110-basket is adjacent to a peripheral side of the portion of the package substrate 118 disposed on the right side, Fig. 1-Annotated) from the top surface (top surface-118) of the package substrate (118) adjacent to the peripheral side surface (side surface-118) of the package substrate (118), and
wherein the peripheral side surface (side surface-118) of the package substrate (118) is an outermost edge surface (Fig. 1-Annotated) of the package substrate (118);
Kong does not expressly disclose at least one semiconductor die positioned in the basket portion of the stiffener; and at least one wire attached to the at least one semiconductor die and extending out of the basket portion of the stiffener.
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Kang’s Figure 4-Annotated.
However, in the same semiconductor device field of endeavor, Kang discloses at least one semiconductor die (15 a semiconductor chip in [0038], Figs. 2-5) positioned (Fig. 4-Annotated) in the basket portion (13-basket Fig. 4-Annotated) of the stiffener (13 a metal structure providing mechanical stability to 11 in [0041], Figs. 2-5); and at least one wire (19 bonding wires connected to the top surface-11 of the package substrate 11 in [0045], Figs. 2 and 5) attached to the at least one semiconductor die (15) and extending out of the basket portion (13-basket) of the stiffener (13).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Kang’s feature of at least one semiconductor die positioned in the basket portion of the stiffener; and at least one wire attached to the at least one semiconductor die and extending out of the basket portion of the stiffener to Kong’s device to provide a semiconductor chip appropriately manufactured depending upon its field of application ([0044], Kang).
Re: Claim 5, Kong modified by Kang discloses the semiconductor package of claim 1, wherein the at least one semiconductor die (15, Kang) is connected (Fig. 5, Kang) via the at least one wire (19, Kang) to the top surface (top surface-11, Fig. 4, Kang) of the package substrate (11, Kang).
Re: Claim 6, Kong modified by Kang discloses semiconductor package of claim 1, further comprising a base die (114 a component in [0019], Fig. 1, Kong) disposed on the top surface (top surface-118, Kong) of the package substrate (118, Kong, Fig. 1), wherein the at least one semiconductor die (Kang-15 applied to Kong) is connected (all electronic components are electrically connected, Kang) via the at least one wire (Kang-19 applied to Kong) to the base die (114, Fig. 1, Kong).
Re: Claim 8, Kong modified by Kang discloses the semiconductor package of claim 1, wherein the at least one wire (Kang-19 applied to Kong) is connected by reversed wire bonding (Fig. 5, Kang) to the package substrate (11, Kang).
Re: Claim 9, Kong modified by Kang discloses the semiconductor package of claim 1,
Kong modified by Kang does not expressly disclose wherein the at least one semiconductor die and the at least one wire are embedded by an underfill or a sealant.
However, in the same semiconductor device field of endeavor, Kang discloses wherein the at least one semiconductor die (15) and the at least one wire (19) are embedded (Fig. 5) by an underfill or a sealant (23 hermetic insulating member in [0045], Figs. 4 and 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Kang’s feature of wherein the at least one semiconductor die and the at least one wire are embedded by an underfill or a sealant to Kong’s device for protecting the circuit board and the semiconductor chip ([0045], Kang).
Re: Claim 11, Kong modified by Kang discloses the semiconductor package of claim 1, wherein the basket portion (110-basket, Kong) of the stiffener (110, Kong) is configured to be a heat spreader (electronics-grade heat-sink copper in [0032], Kong) for the at least one semiconductor die (Kang’s 15 applied to Kong).
Re: Claim 12, Kong modified by Kang discloses the semiconductor package of claim 1, wherein the stiffener (110, Kong) comprises a metal (made of copper in [0032], Kong) or an organic material that is coated with a metal.
Claim(s) 2 and 7 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kong in view of Kang and further in view of Vogelsang (US 20140063887 A1, hereinafter Vogelsang, of the record).
Re: Claim 2, Kong modified by Kang discloses the semiconductor package of claim 1,
Kong modified by Kang does not expressly disclose wherein the at least one semiconductor die further comprises at least one stack of a master die positioned on top of a plurality of slave dies.
However, in the same semiconductor device field of endeavor, Vogelsang discloses wherein the at least one semiconductor die (stacked memory device in [0023], Fig. 3) further comprises at least one stack of a master die (122 a master memory die in [0023], Fig. 3) positioned on top of a plurality of slave dies (124 slave memory dies in [0023], Fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the die of the combination of Kong and Kang comprising at least one stack of a master die positioned on top of a plurality of slave dies according to Vogelsang’s device to enhance characteristics of DRAM chips in terms of capacity and bandwidth ([0003], Vogelsang).
Re: Claim 7, Kong modified by Kang discloses the semiconductor package of claim 6, wherein a die (Kang-15 applied to Kong) is connected via the at least one wire (Kang-19 applied to Kong) to the base die (114, Fig. 1, Kong) or the package substrate.
Kong modified by Kang does not expressly disclose wherein a die is a master die.
However, in the same semiconductor device field of endeavor, Vogelsang discloses a master die (122 a master memory die in [0023], Fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the die of the combination of Kong and Kang, a master die according to Vogelsang’s device to enhance characteristics of DRAM chips in terms of capacity and bandwidth ([0003], Vogelsang).
Claim(s) 3-4 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kong in view of Kang, in view of Vogelsang and further in view of Liu et al. (US 20230395446 A1, hereinafter Liu, of the record).
Re: Claim 3, Kong modified by Kang and Vogelsang discloses the semiconductor package of claim 2,
Kong modified by Kang and Vogelsang does not expressly disclose wherein the master and slave dies are laterally offset from each other.
However, in the same semiconductor device field of endeavor, Liu discloses wherein a top die (122 a top die connected through wiring to lower stacked dies in [0020], Fig. 1) and lower dies (122-lower dies in [0020], Fig. 1) are laterally offset from each other (Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the combination of the Kong, Kang and Vogelsang having a top die and lower dies that are laterally offset from each other according to Liu to obtain the master and slave dies are laterally offset from each other to enable high-yield fabrication of nonvolatile-memory devices having sixteen or more stacked memory dies ([0004], Liu).
Re: Claim 4, Kong modified by Kang and Vogelsang discloses the semiconductor package of claim 2, wherein the master die (122- Vogelsang) is connected to a beneath slave die (124-Vogelsang) via at least one inter-die wire (Liu applied to 122-Vogelsang), and each of the plurality of slave dies (Liu applied to 124-Vogelsang) is connected to a further beneath adjacent slave die via at least one further inter-die wire (Fig. 1, Liu).
Claim(s) 10 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kong in view of Kang and further in view of Chen et al. (US 20180261528 A1, hereinafter Chen, of the record).
Re: Claim 10, Kong modified by Kang discloses the semiconductor package of claim 6,
Kong modified by Kang does not expressly disclose wherein the at least one semiconductor die and the at least one wire are embedded by an underfill or a sealant and further comprising an electrical component positioned on a top surface of the base die; and wherein a top surface of the underfill or the sealant is substantially at the same height with or at a lower height than a top surface of the electrical component.
However, in the same semiconductor device field of endeavor, Kang discloses wherein the at least one semiconductor die (15, Kang) and the at least one wire (19, Kang) are embedded (Fig. 5, Kang) by an underfill or a sealant (23 hermetic insulating member in [0045], Figs. 4 and 5, Kang)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Kang’s feature of wherein the at least one semiconductor die and the at least one wire are embedded by an underfill or a sealant and further comprising an electrical component positioned on a top surface of the base die to Kong’s device to provide a semiconductor chip appropriately manufactured depending upon its field of application ([0044], Kang).
Still, Kong modified by Kang does not expressly disclose further comprising an electrical component positioned on a top surface of the base die; and wherein a top surface of the underfill or the sealant is substantially at the same height with or at a lower height than a top surface of the electrical component.
However, in the same semiconductor device field of endeavor, Chen discloses an electrical component (31 a micro-processor in [0041], Fig. 17) positioned on a top surface of the base die (20 an interposer in [0040], Fig. 17); and wherein a top surface of the underfill or the sealant (60 a molding compound in [0080], Fig. 17) is substantially at the same height (Fig. 17) with or at a lower height than a top surface of the electrical component (31).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Chen’s feature of comprising an electrical component positioned on a top surface of the base die; and wherein a top surface of the underfill or the sealant is substantially at the same height with or at a lower height than a top surface of the electrical component to the combination of Kong and Kang and to include a heat sink mounted on the top surface of the device ([0004], Chen).
Claim(s) 13 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kong in view of Kang and further in view of Higgins (US 5583377 A, hereinafter Higgins, of the record).
Re: Claim 13, Kong modified by Kang discloses the semiconductor package of claim 1, further comprising solder balls (144 land-side ball in [0024], Fig. 1, Kong) attached (Fig. 1, Kong) to a bottom surface of the package substrate (118, Kong) and
Kong modified by Kang does not expressly disclose a section of the basket portion extending below the bottom surface of the package substrate and wherein the solder balls attached to the bottom surface of the package substrate have a diameter that is greater than a height of the section of the basket portion below the bottom surface of the package substrate.
However, in the same semiconductor device field of endeavor, Kang discloses a section of the basket portion (13-basket) extending below (Fig. 4- Annotated) the bottom surface of the package substrate (11).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Kang’s feature of a section of the basket portion extending below the bottom surface of the package substrate to Kong’s device to provide a semiconductor chip appropriately manufactured depending upon its field of application ([0044], Kang).
Still, Kong modified by Kang does not expressly disclose wherein the solder balls attached to the bottom surface of the package substrate have a diameter that is greater than a height of the section of the basket portion below the bottom surface of the package substrate.
However, in the same semiconductor device field of endeavor, Higgins discloses wherein the solder balls (21 solder balls in Col.3 lines 32-33, Fig. 1) attached to the bottom surface of the package substrate (12 substrate in Col. 4 line 1, Fig. 1) have a diameter that is greater (Fig. 1-Annotated) than a height (height -22 Fig. 1-Annotated) of the section of the basket portion below (Fig. 1-Annotated) the bottom surface of the package substrate (12).
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Higgins’s Figure 1-Annotated.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Higgins’s feature of wherein the solder balls attached to the bottom surface of the package substrate have a diameter that is greater than a height of the section of the basket portion below the bottom surface of the package substrate to the combination of Kong and Kang for improving in heat dissipation without substantial increase a device mass (Col. 2 lines 53-55, Higgins).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Talledo et al. (US 9947612 B2) teaches “SEMICONDUCTOR DEVICE WITH FRAME HAVING ARMS AND RELATED METHODS”. This document is related to a semiconductor device including a circuit board having an opening, and a frame. The frame may have an IC die pad in the opening, and arms extending outwardly from the IC die pad and coupled to the circuit board. The semiconductor device may include an IC mounted on the IC die pad, bond wires coupling the circuit board with the IC, and encapsulation material surrounding the IC, the bond wires, and the arms.
Lin et al. (US 8283211 B2) teaches “METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A BUMP/BASE HEAT SPREADER AND A DUAL-ANGLE CAVITY IN THE BUMP”. This document is related to a semiconductor chip assembly providing a bump and a ledge, wherein the bump includes first, second and third bent corners that shape a cavity, mounting an adhesive on the ledge including inserting the bump into an opening in the adhesive, mounting a conductive layer on the adhesive including aligning the bump with an aperture in the conductive layer.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898