DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims presented have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3,5,11-15,18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over FUJIMAKI et al. (US20200091129A1) in view of Iwasaki et al. (US6462425B1).
Regarding claim 1, Fig.4 of FUJIMAKI teaches a semiconductor device, comprising:
a printed wiring substrate 21 (para.0035);
a semiconductor chip 23 (para.0035) mounted along a first surface 21a (para.0035) of the printed wiring substrate 21;
a sealing resin 25 (para.0040) sealing the semiconductor chip 23 and disposed over the first surface 21a;
an electrode pad 35 (para.0029) disposed along a second surface 21b (para.0028) of the printed wiring substrate 21 opposite to the first surface 21a;
an electrode terminal 31 (para.0029) connected to the electrode pad 35 and protruding from the second surface 21b; and
FUJIMAKI does not teach a metal layer in contact with the electrode pad, and disposed on a surface of the electrode pad facing the electrode terminal, such that the metal layer straddles a boundary line of the bonding surface between the electrode terminal and the electrode pad which is at least a boundary line on a side facing an outside of a mounting region of the semiconductor chip.
Iwasaki teaches, in Fig.1, wherein a metal layer 5 (col.8, line 45) in contact with the electrode pad 2 (col.8, line 44), and disposed on a surface of the electrode pad 2 facing the electrode terminal 13 (col.8, line 48), such that the metal layer 5 straddles a boundary line of the bonding surface between the electrode terminal 13 and the electrode pad 2 which is at least a boundary line on a side facing an outside of a mounting region of the semiconductor chip.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the underlying metal film of Iwasaki in the teachings of FUJIMAKI because the underlying metal film provides a larger area that can contain the diameter of the end portion of the connecting conductor with a sufficient margin to accommodate the shift in alignment of the connecting conductor and the connecting underlying metal film (col.2, lines 42-47).
Regarding claim 2, Iwasaki further teaches the semiconductor device according to claim 1, wherein the metal layer 5 (col.8, line 45) is a thickened portion of the electrode pad 2 (col.8, line 44) and the metal layer 5 is disposed over the entire boundary line.
Regarding claim 3, Iwasaki further teaches the semiconductor device according to claim 2, wherein the metal layer 5 (col.8, line 45) is also disposed in the boundary line, and the metal layer 5 covers the entire surface overlapping the bonding surface.
Regarding claim 5, FUJIMAKI further teaches the semiconductor device according to claim 4, further comprising a grid array, the grid array having a plurality of electrode terminals 31 (para.0029) located in a grid shape, the plurality of electrode terminals 31 including the electrode terminal 31 at a position overlapping the mounting region on the printed wiring substrate 21 (para.0027),
wherein the electrode terminal 31 is located at a position overlapping an outer edge portion of the mounting region on the printed wiring substrate 21, or located at an outermost peripheral portion in the mounting region among the plurality of electrode terminals 31.
Regarding claim 11, FUJIMAKI further teaches the semiconductor device according to claim 1, wherein the semiconductor device includes a NAND memory (para.0034, wherein memory chip 23 is a NAND-type flash memory).
Regarding claim 12, FUJIMAKI further teaches the semiconductor device according to claim 1, wherein the semiconductor device includes at one of a memory or a memory controller 22 (para.0040).
Regarding claim 13, Fig.4 of FUJIMAKI further teaches the semiconductor device according to claim 1, further including a plurality of stacked semiconductor chips 23 (para.0035) including the semiconductor chip 23.
Regarding claim 14, FUJIMAKI further teaches the semiconductor device according to claim 13, further including bonding wires 24 (para.0035) electrically connecting at least some of the plurality of stacked semiconductor chips 23 (para.0035) to the first surface 21a (para.0035).
Regarding claim 15, Iwasaki further teaches the semiconductor device according to claim 1, wherein the metal layer 5 (col.9, lines 59-60, wherein the metal film is plated to facilitate the bonding of the terminal electrode to the connecting conductor) includes a plating layer.
Regarding claim 18, FUJIMAKI further teaches the semiconductor device according to claim 1, wherein the electrode terminal 31 (para.0029) includes a solder bump or a solder ball 36 (para.0029).
Regarding claim 20, Iwasaki further teaches the semiconductor device according to claim 1, wherein the metal layer 5 (col.8, line 45) having a diameter larger than a diameter of the bonding surface.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over FUJIMAKI et al. (US20200091129A1) in view of Hashimoto et al. (US20090181521A1).
Regarding claim 17, FUJIMAKI does not teach wherein the mounting region has a substantially rectangular shape.
Hashimoto teaches, in Fig.5, wherein the mounting area has a rectangular shape and wherein stress relieving layer 7 is provided in the active region and leads 3 are positioned within the active region. External electrodes 5 are also provided within the active region. (para.0131).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the rectangular active region of Hashimoto in the teachings of FUJIMAKI because when laying out the external electrodes 5, the interior of the active region, a region of a particular area can be provided, and thus the degree of freedom for positioning the external electrodes is greatly increased. (Hashimoto, [para.0131]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT KIPKEMOI RONO whose telephone number is (571)270-5977. The examiner can normally be reached Mon-Fri, 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891