DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of species 1 in the reply filed on 06/30/2025 is acknowledged.
Claims 4, 6-10,16 and 19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Claim 5 is also withdrawn as it depends on withdrawn claim 4. Election was made without traverse in the reply filed on 06/30/2026.
Response to Arguments
Applicant’s arguments with respect to claims presented have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3,11-15, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over FUJIMAKI et al. (US20200091129A1) in view of Hsiao et al. (US10522491B2).
Regarding claim 1, Fig.4 of FUJIMAKI teaches a semiconductor device, comprising:
a printed wiring substrate 21 (para.0035);
a semiconductor chip 23 (para.0035) mounted along a first surface 21a (para.0035) of the printed wiring substrate 21;
a sealing resin sealing 25 (para.0040) the semiconductor chip 23 and disposed over the first surface 21a;
an electrode pad 35 (para.0029) disposed along a second surface 21b (para.0028) of the printed wiring substrate 21 opposite to the first surface 21a;
an electrode terminal 31 (para.0029) connected to the electrode pad 35 and protruding from the second surface 21b.
FUJIMAKI does not teach a metal layer in contact with the electrode pad, and disposed on a surface of the electrode pad facing the electrode terminal, such that the metal layer straddles a boundary line of the bonding surface between the electrode terminal and the electrode pad which is at least a boundary line on a side facing an outside of a mounting region of the semiconductor chip, and a diameter of the metal layer is smaller than a diameter of the electrode pad.
Fig.1G of Hsiao teaches a semiconductor device includes a solder bump overlying and electrically connected to a pad region, and a metal cap layer formed on at least a portion of the solder bump; wherein a metal layer 16 (col.3, lines 57-58) in contact with the electrode pad 12 (col.3, line 57), and disposed on a surface of the electrode pad 12 facing the electrode terminal 22b (col.5, line 59), such that the metal layer 16 straddles a boundary line of the bonding surface between the electrode terminal 26 and the electrode pad 12 which is at least a boundary line on a side facing an outside of a mounting region of the semiconductor chip 10 (col.5, lines 38-39), and a diameter of the metal layer 16 is smaller than a diameter of the electrode pad 12.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Hsiao’s pad region 12, which has a greater diameter than UBM layer 16, in the teachings of FUJIMAKI in order to provide more surface area that can be used in the bonding process to connect the integrated circuits in the respective chip to external features (Hsiao, [col.3, lines 41-42]).
Regarding claim 2, Hsiao further teaches the semiconductor device according to claim 1, wherein the metal layer 16 (col.3, lines 57-58) is a thickened portion of the electrode pad 12 (col.3, lines 34-36 and col.4, line 5; wherein conductive region 12 may include copper and copper alloy and layer 16 is a Cu/Ti layer and thus, conductive region 12 and layer 16 can be formed of the same material that is combined and thus thickened in the middle) and the metal layer 16 is disposed over the entire boundary line.
Regarding claim 3, Hsiao further teaches the semiconductor device according to claim 2, wherein the metal layer 16 (col.3, lines 57-58) is also disposed in the boundary line, and the metal layer 16 covers the entire surface overlapping the bonding surface.
Regarding claim 11, FUJIMAKI further teaches the semiconductor device according to claim 1, wherein the semiconductor device includes a NAND memory (para.0034, wherein the memory chip 23 is a NAND-type flash memory).
Regarding claim 12, FUJIMAKI further teaches the semiconductor device according to claim 1, wherein the semiconductor device includes at one of a memory or a memory controller 22 (para.0040).
. Regarding claim 13, FUJIMAKI further teaches the semiconductor device according to claim 1, further including a plurality of stacked semiconductor chips 23 (para.0035) including the semiconductor chip 23.
Regarding claim 14, FUJIMAKI further teaches the semiconductor device according to claim 13, further including bonding wires 24 (para.0035) electrically connecting at least some of the plurality of stacked semiconductor chips 23 (para.0035) to the first surface 21a (para.0035).
Regarding claim 15, Hsiao further teaches the semiconductor device according to claim 1, wherein the metal layer 16 (col.3, lines 60-61) includes a plating layer (col.3, lines 60-61, wherein UBM layer 16 includes a seed layer that may be a copper seed layer formed on the diffusion barrier layer).
Regarding claim 18, FUJIMAKI further teaches the semiconductor device according to claim 1, wherein the electrode terminal 31 (para.0029) includes a solder bump or a solder ball 36 (para.0029).
Regarding claim 20, Hsiao further teaches the semiconductor device according to claim 1, wherein the metal layer 16 (col.3, lines 57-58) having a diameter larger than a diameter of the bonding surface.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over FUJIMAKI et al. (US20200091129A1) in view of Hsiao et al. (US10522491B2) and in further view of Hashimoto et al. (US20090181521A1).
Regarding claim 17, the combination of FUJIMAKI and Hsiao does not teach wherein the mounting region has a substantially rectangular shape.
Fig.5 of Hashimoto teaches wherein a mounting area has a rectangular shape and wherein stress relieving layer 7 is provided in the active region and leads 3 are positioned within the active region. External electrodes 5 are also provided within the active region (para.0131).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the rectangular active region of Hashimoto in the teachings of FUJIMAKI, as modified by Hsiao, because when laying out the external electrodes 5, the interior of the active region, a region of a particular area can be provided, and thus the degree of freedom for positioning the external electrodes is greatly increased (Hashimoto, [para.0131]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT KIPKEMOI RONO whose telephone number is (571)270-5977. The examiner can normally be reached Mon-Fri, 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
Prosecution Insights