DETAILED ACTION
Claim Objections
Claim 6 is objected to because of the following informalities: the amended subject matter of “a subsequent semiconductor” should be rewritten as --a subsequent semiconductor device--. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4-6, 8-12, 15-17, and 26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Leshinsky-Altshuller et al. [US 2020/0201193].
For claims 1 and 8, Leshinsky-Altshuller teaches an apparatus (see Figs. 1A and 1B) for manufacturing a semiconductor device (see [0003]), the apparatus comprising:
a light source (112, see [0048]) configured to provide a light;
a mask (120) in the light path of the light, wherein the mask comprises a pattern configured to form a light pattern from the provided light (see [0052]);
a movable carrier stage (126) configured to carry a carrier (124); and
a non-transitory computer readable medium (see [0046]-[0047]) having instructions stored thereon that, when executed by a controller (106), cause the apparatus to
expose a portion (pattern exposure using negative or positive resist, see [0053], patterns 304, and device 404 in a first exposure field 202a, see Figs. 4A-9B) of a first region (202a) of a photoresist layer (128) with the light pattern, leaving a first unexposed portion in the first region (boundary portions of 202a where no pattern is provided is unexposed),
expose (patterns 302, and device 404 in a second exposure field 202b, see Figs. 4A-9B) a portion of a second region (202b) of the photoresist layer with at least in part the same light pattern, leaving a second unexposed portion in the second region (boundary portions of 202b where no pattern is provided is unexposed),
wherein the second region and the first region overlap in an overlap region (204) of the photoresist layer,
wherein the first unexposed portion in the first region is at a first end of the overlap region and the second unexposed portion in the second region is at a second end of the overlap region (vertically extending top or bottom regions that extend from the marks 302 in field 202b and the other side of vertically extending top or bottom regions that extend from marks 304 in field 202a),
wherein the first unexposed portion in the first region overlaps with an exposed portion of the second region (mark 302 provided in an unexposed top or bottom portion of the field 202a in overlap region 204) and the second unexposed portion in the second region overlaps with an exposed portion of the first region (mark 304 provided in an unexposed top or bottom portion of the field 202b in overlap region 204),
wherein the mask is configured to form the light pattern that forms, in exposing the first region, a first portion of individual markings in the overlap region of the photoresist layer, and to form, in exposing the second region, a second portion of individual markings in the overlap region of the photoresist layer (pattern elements 408 associated with the first-layer target features 302 are located on the left and top sides of the device area 404 and pattern elements 410 associated with the second-layer target features 304 are located on the right and bottom sides of the device area 404 in the overlap region 204, see Figs 4A-9B).
For claim 2, Leshinsky-Altshuller teaches the mask is configured to generate the light pattern in the photoresist layer by reflection, absorption (negative or positive pattern mask blocking light that is not transmitted, see [0053]), and/or phase shifting.
For claim 4, Leshinsky-Altshuller teaches the individual markings are configured to comprise at least one spatial symmetry when the first region and the second region are arranged in a predetermined manner to each other on the photoresist layer (see the spatial symmetry in marks 302 and 304 in Figs. 4A-9B and [0072]).
For claim 5, Leshinsky-Altshuller teaches the controller is further configured to: determine the spatial symmetry of at least one of the markings (1408, see [0072] and [0099] and Fig. 14); and adjust at least one process based on the determined spatial symmetry (step 1410, generating one or more correctable to adjust one or more fabrication parameters, see [0100]).
For claim 6, Leshinsky-Altshuller teaches the process is a process performed for the same semiconductor device (the same sample, see [0101]) or a subsequent semiconductor device (to different samples within the same lot, see [0101]).
For claim 9, Leshinsky-Altshuller teaches the first region corresponds to a first integrated circuit estate and the second region corresponds to a second integrated circuit estate (device area in region 206 array, see Figs. 4-9B).
For claim 10, Leshinsky-Altshuller teaches the instructions are further configured to cause the apparatus to form one or more components of the semiconductor device in the first integrated circuit estate, and separate the first integrated circuit estate from the second integrated circuit estate (device area in regions 206 separated by the overlap region 204, see Figs. 4A-9B).
For claim 11, Leshinsky-Altshuller teaches the light pattern comprises an active region (device die, see [0067] and [0074]) and a frame region (region surrounding field 206), and wherein the frame region in exposing the first region and the frame region in exposing the second region forms the overlap region, wherein the active region corresponds to a first integrated circuit estate in the first region and the active region corresponds to a second integrated circuit estate in the second region, and wherein the overlap region is arranged between the first integrated circuit estate and the second integrated circuit estate (device area in regions 206 separated by the overlap region 204, see Figs. 4A-9B).
For claim 12, Leshinsky-Altshuller teaches the instructions are further configured to cause the apparatus to form one or more components of the semiconductor device in the active regions of at least one of the first integrated circuit estate and the second integrated circuit estate (device die in regions 206/404, see [0067] and [0074]), and separate the first integrated circuit estate from the second integrated circuit estate (device area in regions 206 separated by the overlap region 204, see Figs. 4A-9B).
For claim 15, Leshinsky-Altshuller teaches the overlap region comprises a scribe area of the semiconductor device (area framing the device area with markings 302, 304, see Figs. 4A-9B).
For claim 16, Leshinsky-Altshuller teaches wherein the individual markings are configured to comprise at least one spatial symmetry when the first region and the second region are arranged in a predetermined manner to each other on the photoresist layer (see the spatial symmetry in marks 302 and 304 in Figs. 4A-9B and [0072]).
For claim 17, Leshinsky-Altshuller teaches the instructions are further configured to cause the apparatus to: determine the spatial symmetry of at least one of the markings (1408, see [0072] and [0099] and Fig. 14); and adjust at least one process based on the determined spatial symmetry (step 1410, generating one or more correctable to adjust one or more fabrication parameters, see [0100]), wherein the process is at least one of a process performed for the same semiconductor device (the same sample, see [0101]) and a process performed for a subsequent semiconductor device (to different samples within the same lot, see [0101]).
For claim 26, Leshinsky-Altshuller teaches the first portion of individual markings and the second portion of individual markings together comprise the individual markings (300, see Figs. 4A-9B), and wherein the individual markings are disposed densely to enable higher order modeling of the field grid shapes (field to field variations and errors are detected, see [0069]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Leshinsky-Altshuller in view of Yu et al. [US 2019/0033706].
For claim 14, Leshinsky-Altshuller fails to teach the first region corresponds to a first portion of an integrated circuit estate and the second region corresponds to a second portion of the same integrated circuit estate, wherein the light pattern comprises an active region and a frame region, and wherein the frame region in exposing the first region and the frame region in exposing the second region forms the overlap region, wherein the active region corresponds to a first portion of an integrated circuit estate in the first region and the active region corresponds to a second portion of the same integrated circuit estate in the second region, and wherein the overlap region is arranged between the first portion of the integrated circuit estate and the second portion of the integrated circuit estate.
Yu teaches the first region corresponds to a first portion of an integrated circuit estate and the second region corresponds to a second portion of the same integrated circuit estate (stitching region in overlapping region 208A-B, 602 to form large functional area of circuit device, see Figs. 2-8), wherein the light pattern comprises an active region (206) and a frame region (edge scribe area within the frame, see [0033] and Figs. 2-8), and wherein the frame region in exposing the first region and the frame region in exposing the second region forms the overlap region (stitching regions 208A-B, 602), wherein the active region corresponds to a first portion of an integrated circuit estate in the first region and the active region corresponds to a second portion of the same integrated circuit estate in the second region (see Figs. 4-8 and [0037]), and wherein the overlap region is arranged between the first portion of the integrated circuit estate and the second portion of the integrated circuit estate (stitching zones 208A-B 602, see Figs. 4-8).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to provide the shared integrated circuit estate with stitching pattern alignment as taught by Yu in the exposure apparatus control as taught by Leshinsky-Altshuller in order accurately align large area ICs using multiple exposures (see [0015]-[0016] and [0023] of Yu).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Leshinsky-Altshuller in view of Sato et al. [US 2002/0014600].
For claim 3, Leshinsky-Altshuller fails to teach a slit screen arranged between the mask and the photoresist layer, wherein the light pattern exposes the photoresist layer through the slit screen.
Sato teaches a slit screen arranged between the mask and the photoresist layer, wherein the light pattern exposes the photoresist layer through the slit screen (15, see Figs. 2-3b).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to provide the slit screen as taught by Sato in the exposure apparatus as taught by Leshinsky-Altshuller in order to form a penumbra that provides a desired dose uniformity and image size in scanning projection lithography.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Leshinsky-Altshuller in view of Amir et al. [US 2014/0065736].
For claim 27, Leshinsky-Altshuller fails to teach the individual markings comprise a first sub-section and a second sub-section, the first sub-section is configured for an optical based analysis method, and the second sub-section different from the first sub-section is configured for an electron beam based analysis method.
Amir teaches the individual markings (see Fig. 1A-2) comprise a first sub-section (optical overlay mark may include a plurality of working zones, see Figs. 1A-1C and [0028]-[0031]) and a second sub-section (device overlay by CD-SEM in section 118, see Fig. 2 and [0027]), the first sub-section (112i and 122i) is configured for an optical based analysis method, and the second sub-section (118) different from the first sub-section is configured for an electron beam based analysis method.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to provide the hybrid mark as taught by Amit in the mark as taught by Leshinsky-Altshuller in order to verify the accuracy of the optical measurement and thereby improve throughput using faster optical metrology techniques, see [0023] of Amir.
Claims 28 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Leshinsky-Altshuller in view of Smith [US 6,436,589].
For claims 28 and 29, Leshinsky-Altshuller teaches the first unexposed portion in the first region comprises a first corner portion of the first region and the second unexposed portion in the second region comprises a second corner portion of the second region (corner portions in the overlapping region 204, see Figs. 4A-9B); wherein the corner portions are absent any individual markings (see Fig. 4B), and the photoresist layer comprises a positive photoresist layer (unexposed regions remain when using a positive resist, see [0053]).
Leshinsky-Altshuller fails to explicitly teach the exposed portion of the second region is absent of any individual markings and the exposed portion of the first region is absent of any individual markings and the mask is configured to block light to the first corner portion and to the second corner portion.
Smith teaches the first unexposed portion in the first region comprises a first corner portion of the first region and the second unexposed portion in the second region comprises a second corner portion of the second region (unexposed corner kerf regions adjacent to the exposed interleaved corner kerf regions 42, see Fig. 6A and col 4 lines 30-48), wherein the exposed portion of the second region is absent of any individual markings and the exposed portion of the first region is absent of any individual markings (corner kerf region 42 shows no markings, see Figs. 5 and 6A, ), and the mask is configured to block light to the first corner portion and to the second corner portion (chromium layer 32 in corner regions, see Fig. 5).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to provide the exposure regions and unexposed regions as taught by Smith in the exposure process as taught by Leshinsky-Altshuller to provide kerf regions for dicing that can also accommodate a reticle blind during adjacent double patterning exposures.
Response to Arguments
Applicant's arguments filed on September 9, 2026 have been fully considered but they are not persuasive.
The Applicant argues on pages 9-11 of the Remarks, regarding claims 1 and 8, that Leshinsky does not disclose any markings 302, 304 at unexposed top or bottom portions of exposure regions 202a, 202b in the overlapping region 204 based on the Applicant’s annotated Fig. 4B.
The Examiner respectfully disagrees. As described in paragraphs [0074]-[0076] with respect to Figs. 4A and 4B, the overlap region 204 between first exposure field 202 and second exposure field 204 is subject to two separate exposures to form overlay target 300a.
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The unexposed regions in the first exposure field 202a of overlap region 204 identified by dotted lines both above and below the white mark 304 (left) and the unexposed regions in the second exposure field 202b of overlap region 204 identified by dotted line both above and below the black mark 302 (right).
As shown in the annotated Fig. 4B above, mark 304 of the first exposure region 202a is in the unexposed top and/or bottom end regions of the second exposure field 202b and mark 302 of the second exposure region 202b is in the unexposed top and/or bottom end regions of the first exposure field 202a, thereby teaching the salient claim limitations.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Steven H Whitesell whose telephone number is (571)270-3942. The examiner can normally be reached Mon - Fri 9:00 AM - 5:30 PM (MST).
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/Steven H Whitesell/Primary Examiner, Art Unit 1759
