Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/14/2025 has been entered.
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-6, 10 and 11 rejected under 35 U.S.C. 103 as being unpatentable over Hwang (U.S. Patent Pub. No. 2013/0161821) of record, in view of Lee (U.S. Patent Pub. No. 2020/0227434) of record.
Regarding Claim 1
FIG. 3 of Hwang discloses a semiconductor device comprising: a first gate structure (A_C1) including a first sub stack (lower) and a second sub stack (upper) on the first sub stack, wherein the first sub stack includes a first pad staircase structure and the second sub stack includes a first sidewall connected to the first pad staircase structure; a dummy stack (A_D) adjacent to the first gate structure in a first direction and including a first dummy stack and a second dummy stack on the first dummy stack, wherein the first dummy stack includes a dummy staircase structure and the second dummy stack includes a first dummy sidewall connected to the dummy staircase structure, the first dummy sidewall including a plurality of first protrusions (FIG. 4); and a first insulating structure (245) located between the first gate structure and the dummy stack, wherein the first dummy sidewall extends in a second direction intersecting the first direction, wherein the plurality of first protrusions protrude in the first direction toward the first gate structure (FIG. 4).
Hwang is silent with respect to “the first pad staircase structure and the dummy staircase structure have a symmetrical shape; and the first sidewall and the first dummy sidewall face each other in the first direction”.
FIG. 18 of Lee discloses a similar semiconductor device, comprising a first gate structure (within CAR) including a first sub stack (lower layers) and a second sub stack (the topmost layer) on the first sub stack, wherein the first sub stack includes a first pad staircase structure and the second sub stack includes a first sidewall connected to the first pad staircase structure; a dummy stack (DST) adjacent to the first gate structure in a first direction (D1) and including a first dummy stack (lower layers) and a second dummy stack (the topmost layer) on the first dummy stack, wherein the first dummy stack includes a dummy staircase structure and the second dummy stack includes a first dummy sidewall connected to the dummy staircase structure, wherein the first dummy sidewall extends in a second direction (D2) intersecting the first direction, wherein the first pad staircase structure and the dummy staircase structure have a symmetrical shape [0064]; and the first sidewall and the first dummy sidewall face each other in the first direction, wherein the first dummy sidewall including a plurality of first protrusions, and wherein the plurality of first protrusions protrude in the first direction toward the first gate structure (FIG. 21).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Hwang, as taught by Lee, because the claimed configuration was a matter of choice (as shown by various embodiments of Lee), which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant. In re Dailey 149 USPQ 47, 50 (CCPA 1966). See also Glue Co. v. Upton 97 US 3,24 (USSC 1878). MPEP 2144.04. The ordinary artisan would have been motivated to modify Hwang in the above manner for purpose of providing a 3D semiconductor memory device with an increased integration density ([0004] of Lee).
Regarding Claim 2
Lee discloses the plurality of first protrusions protrude into the first insulating structure [0054].
Regarding Claim 3
FIG. 3 of Hwang discloses the first pad staircase structure (A_C1) and the dummy staircase structure (A_D) are positioned at corresponding levels, and the first sidewall and the first dummy sidewall are positioned at corresponding levels.
Regarding Claim 4
FIG. 19 of Lee discloses the first sidewall extends in the second direction.
Regarding Claim 5
The materials of the first dummy sidewall and the first insulating structure used by Hwang are different. It would have been obvious to one of ordinary skill in the art that a crack would be located between the first dummy sidewall and the first insulating structure, because of their different thermal properties.
Regarding Claim 6
The materials of the first dummy sidewall and the first insulating structure used by Hwang are different. It would have been obvious to one of ordinary skill in the art that a crack would be located between the first dummy sidewall and the first insulating structure, because of their different thermal properties.
Regarding Claim 10
FIG. 19 of Lee discloses the dummy stack includes a second dummy sidewall, and the second dummy sidewall includes at least one second protrusion protruding into the second insulating structure.
Regarding Claim 11
FIG. 19 of Lee discloses the plurality of first protrusions and the at least one second protrusion are located at corresponding levels.
Claims 1 and 9 rejected under 35 U.S.C. 103 as being unpatentable over Kang (CN 112786615) of record, in view of Chung (U.S. Patent Pub. No. 2022/0102369) of record, in view of Kim (U.S. Patent Pub. No. 2018/0174661) of record.
Regarding Claim 1
FIG. 6 of Kang discloses a semiconductor device comprising: a first gate structure (GST_B) including a first sub stack and a second sub stack on the first sub stack, wherein the first sub stack includes a first pad staircase structure and the second sub stack includes a first sidewall connected to the first pad staircase structure; a dummy stack (DM) adjacent to the first gate structure in a first direction and including a first dummy stack and a second dummy stack on the first dummy stack, wherein the first dummy stack includes a dummy staircase structure and the second dummy stack includes a first dummy sidewall connected to the dummy staircase structure a dummy staircase structure and a first dummy sidewall connected to the dummy staircase structure; and a first insulating structure (SI, FIG. 5) located between the first gate structure and the dummy stack; and the first sidewall and the first dummy sidewall face each other in the first direction.
Kang is silent with respect to “the first dummy sidewall including a plurality of first protrusions”; “the first dummy sidewall extends in a second direction intersecting the first direction”; “the plurality of first protrusions protrude in the first direction toward the first gate structure” and “the first pad staircase structure and the dummy staircase structure have a symmetrical shape”.
FIG. 3 of Chung discloses a similar semiconductor device, comprising a dummy stack (DS1) including a dummy staircase structure (lower) and a first dummy sidewall (upper) connected to the dummy staircase structure, wherein the first dummy sidewall includes a plurality of first protrusion (FIG. 9B), the first dummy sidewall extends in a second direction intersecting the first direction, and the plurality of first protrusions protrude in the first direction toward the first gate structure (CR), wherein the dummy staircase structure has a symmetrical shape (FIG. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Kang, as taught by Chung, because the claimed configuration was a matter of choice (as shown by various embodiments of Chung), which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant. In re Dailey 149 USPQ 47, 50 (CCPA 1966). See also Glue Co. v. Upton 97 US 3,24 (USSC 1878). MPEP 2144.04. The ordinary artisan would have been motivated to modify Kang in the above manner for purpose of providing a 3D semiconductor memory device with an increased integration density and reliability ([0004] of Chung).
Kang as modified by Chung is silent with respect to the first pad staircase structure has a symmetrical shape.
Kim discloses a similar semiconductor device, comprising a first gate structure (FIG. 4) including a first sub stack and a second sub stack on the first sub stack, wherein the first sub stack includes a first pad staircase structure and the second sub stack includes a first sidewall connected to the first pad staircase structure; a dummy stack (FIG. 7) including a first dummy stack and a second dummy stack on the first dummy stack, wherein the first dummy stack includes a dummy staircase structure and the second dummy stack includes a first dummy sidewall connected to the dummy staircase structure, the first dummy sidewall including a plurality of first protrusions (FIG. 12), wherein the first pad staircase structure and the dummy staircase structure have a symmetrical shape [0053, 0074].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Kang, as taught by Kim, because the claimed configuration was a matter of choice (as shown by various embodiments of Lee), which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant. In re Dailey 149 USPQ 47, 50 (CCPA 1966). See also Glue Co. v. Upton 97 US 3,24 (USSC 1878). MPEP 2144.04. The ordinary artisan would have been motivated to modify Kang in the above manner for purpose of providing a 3D semiconductor memory device with increased performance and reduced manufacturing costs ([0003] of Kim).
Regarding Claim 9
FIG. 6 of Kang discloses a second gate structure (GST_A) including a second pad staircase structure and a second sidewall connected to the second pad staircase structure; and a second insulating structure located between the second gate structure and the dummy stack.
Claims 13-16 rejected under 35 U.S.C. 103 as being unpatentable over Chung (U.S. Patent Pub. No. 2022/0102369) of record, in view of Jung (U.S. Patent Pub. No. 2021/0313343) of record.
Regarding Claim 13
FIG. 7 of Chung discloses a semiconductor device comprising: a peripheral circuit (PERI); an interconnection structure electrically connected to the peripheral circuit; a first dummy stack (lower DS1) located on the interconnection structure and including a dummy staircase structure; a second dummy stack (uppermost portion of DS1) located on the first dummy stack to vertically overlap the first dummy stack, wherein the second dummy stack includes a dummy sidewall including at least one protrusion (FIG. 9B); an insulating structure (190) formed on the first dummy stack and facing the dummy sidewall.
Chung is silent with respect to “a contact plug penetrating the second dummy stack and the first dummy stack, the contact plug electrically connected to the interconnection structure”.
FIG. 4 of Jung discloses a similar semiconductor device comprising: a peripheral circuit (30); an interconnection structure (RL) electrically connected to the peripheral circuit [0024]; a first dummy stack (DSSa) located on the interconnection structure; a second dummy stack (DSSb) located on the first dummy stack; a contact plug (VCT) penetrating the second dummy stack and the first dummy stack, and the contact plug electrically connected to the interconnection structure [0048].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chung, as taught by Jung. The ordinary artisan would have been motivated to modify Chung in the above manner for purpose of improving the degree of integration within a limited area ([0003] of Jung).
Regarding Claim 14
FIG. 9B of Chung discloses the plurality of protrusions protrude into the insulating structure.
Regarding Claim 15
FIG. 3 of Chung discloses a crack located between the dummy sidewall and the insulating structure.
Regarding Claim 16
FIG. 9B of Chung discloses the crack is isolated by the at least one protrusion.
Claims 31 and 33 rejected under 35 U.S.C. 103 as being unpatentable over Kang, in view of Noh (U.S. Patent Pub. No. 2017/0207119).
Regarding Claim 31
FIG. 6 of Kang discloses a semiconductor device comprising: a first gate structure (GST_B) including a first pad staircase structure and a first sidewall connected to the first pad staircase structure; a second gate structure (GST_A) including a second pad staircase structure and a second sidewall connected to the second pad staircase structure, the second gate structure being adjacent to the first gate structure in a first direction; and a dummy stack (DM) disposed between the first gate structure and the second gate structure and including a first dummy sidewall facing the first gate structure and a second dummy sidewall facing the second gate structure.
Kang is silent with respect to “the first dummy sidewall includes first protrusions protruding in the first direction toward the first gate structure”; “the second dummy sidewall includes second protrusions protruding in the first direction toward the second gate structure” and “the first dummy sidewall and the second dummy sidewall extend in the second direction intersecting the first direction”.
FIG. 12D of Noh discloses a similar semiconductor device, the first dummy sidewall includes first protrusions protruding in the first direction (I-I’); the second dummy sidewall includes second protrusions protruding in the first direction; and the first dummy sidewall and the second dummy sidewall extend in the second direction (II-II’) intersecting the first direction.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Kang, as taught by Noh, such that the first dummy sidewall includes first protrusions protruding in the first direction toward the first gate structure; the second dummy sidewall includes second protrusions protruding in the first direction toward the second gate structure and the first dummy sidewall and the second dummy sidewall extend in the second direction intersecting the first direction. The ordinary artisan would have been motivated to modify Kang in the above manner for purpose of forming 3D memory device with improved integration density ([0008] of Noh).
Regarding Claim 33
FIG. 12D of Noh discloses the dummy stack includes a first dummy stack and a second dummy stack on the first dummy stack, wherein the first dummy stack includes a first dummy staircase structure facing the first pad staircase structure and a second dummy staircase structure facing the second pad staircase structure, and wherein the second dummy stack includes the first dummy sidewall and the second dummy sidewall.
Claim 32 rejected under 35 U.S.C. 103 as being unpatentable over Kang and Noh, in view of Jung.
Regarding Claim 32
Kang as modified by Noh discloses Claim 31, comprising a peripheral circuit.
Kang as modified by Noh is silent with respect to “an interconnection structure electrically connected to the peripheral circuit; and a contact plug penetrating the dummy stack and electrically connected to the interconnection structure”.
FIG. 4 of Jung discloses a similar semiconductor device comprising: a peripheral circuit (30); an interconnection structure (RL) electrically connected to the peripheral circuit [0024]; a first dummy stack (DSSa) located on the interconnection structure; a second dummy stack (DSSb) located on the first dummy stack; a contact plug (VCT) penetrating the second dummy stack and the first dummy stack, and the contact plug electrically connected to the interconnection structure [0048].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Kang, as taught by Jung. The ordinary artisan would have been motivated to modify Kang in the above manner for purpose of improving the degree of integration within a limited area ([0003] of Jung).
Claim 34 rejected under 35 U.S.C. 103 as being unpatentable over Chung and Jung, in view of Noh.
Regarding Claim 34
Chung as modified by Jung discloses Claim 13.
Chung as modified by Jung is silent with respect to “the contact plug penetrates one of the plurality of protrusions”.
FIG. 12E of Noh discloses a similar semiconductor device, wherein the contact plug (139) penetrates one of the plurality of protrusions.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chung, as taught by Noh. The ordinary artisan would have been motivated to modify Chung in the above manner for purpose of forming 3D memory device with improved integration density ([0008] of Noh).
Response to Arguments
Applicant’s arguments with respect to Claim 1 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Pertinent Art
Pertinent art includes Kim (U.S. Patent Pub. No. 2018/0174661), Lee (U.S. Patent Pub. No. 2021/0028104), Lee (U.S. Patent Pub. No. 2019/0378857), US 20110147818, 20120149185, 20200303392, and KM 101974352.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897