Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 5, 6 and 9-11 rejected under 35 U.S.C. 103 as being unpatentable over Lee (KR 2018000130, machine-translation provided), in view of Hwang (U.S. Patent Pub. No. 2013/0161821) of record.
Regarding Claim 1
FIG. 7 of Lee discloses a semiconductor device comprising: a first gate structure (right stack) including a first sub stack (lower portion) and a second sub stack (upper portion with vertically extending sidewall) on the first sub stack, wherein the first sub stack includes a first pad staircase structure, and the second sub stack includes a first sidewall connected to the first pad staircase structure; a dummy stack (middle stack) adjacent to the first gate structure in a first direction and including a first dummy stack (41-44) and a second dummy stack on the first dummy stack, wherein the first dummy stack includes a dummy staircase structure, and the second dummy stack includes a first dummy sidewall connected to extending from the dummy staircase structure, wherein the first dummy sidewall extends in a second direction intersecting non-parallel to the first direction, wherein the first pad staircase structure is symmetrical with the dummy staircase structure; and the first sidewall faces the first dummy sidewall face each other in the first direction; and wherein the first sidewall extends away from the first pad staircase structure in the second direction.
Lee is silent with respect to “the first dummy sidewall including a plurality of first protrusions”; “the plurality of first protrusions protrudes in the first direction toward the first gate structure” “a first insulating structure located between the first gate structure and the dummy stack”.
FIG. 4 of Hwang discloses a similar semiconductor device, comprising: a dummy stack (A_D) adjacent to the first gate structure (A_P) in a first direction and including a first dummy stack (ST2) and a second dummy stack (ST1) on the first dummy stack, wherein the first dummy stack includes a dummy staircase structure, and the second dummy stack includes a first dummy sidewall connected to extending from the dummy staircase structure, wherein the first dummy sidewall extends in a second direction intersecting non-parallel to the first direction, wherein the first dummy sidewall including a plurality of first protrusions (FIG. 4A); the plurality of first protrusions protrudes in the first direction toward the first gate structure; and a first insulating structure (245, FIG. 4B) located between the first gate structure and the dummy stack.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lee, as taught by Hwang, because the claimed configuration was a matter of choice (as shown by various embodiments of Lee), which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant. In re Dailey 149 USPQ 47, 50 (CCPA 1966). See also Glue Co. v. Upton 97 US 3,24 (USSC 1878). MPEP 2144.04. The ordinary artisan would have been motivated to modify Lee in the above manner for purpose of forming a nonvolatile memory device including stepped structures ([0015] of Hwang).
Regarding Claim 2
FIG. 4 of Hwang discloses the plurality of first protrusions protrude into the first insulating structure [0054].
Regarding Claim 3
FIG. 7 of Lee discloses the first pad staircase structure and the dummy staircase structure are positioned at corresponding levels, and the first sidewall and the first dummy sidewall are positioned at corresponding levels.
Regarding Claim 5
The materials of the first dummy sidewall and the first insulating structure used by Hwang are different. It would have been obvious to one of ordinary skill in the art that a crack would be located between the first dummy sidewall and the first insulating structure, because of their different thermal properties.
Regarding Claim 6
The materials of the first dummy sidewall and the first insulating structure used by Hwang are different. It would have been obvious to one of ordinary skill in the art that a crack would be located between the first dummy sidewall and the first insulating structure, because of their different thermal properties.
Regarding Claim 9
FIG. 7 of Lee discloses a second gate structure (left stack) including a second pad staircase structure and a second sidewall connected to the second pad staircase structure. FIG. 4 of Hwang discloses a second insulating structure located between the second gate structure and the dummy stack.
Regarding Claim 10
Modified Lee discloses the dummy stack includes a second dummy sidewall, and the second dummy sidewall includes at least one second protrusion protruding into the second insulating structure.
Regarding Claim 11
Modified Lee discloses the plurality of first protrusions and the at least one second protrusion are located at corresponding levels.
Claims 13-16 rejected under 35 U.S.C. 103 as being unpatentable over Chung (U.S. Patent Pub. No. 2022/0102369) of record, in view of Jung (U.S. Patent Pub. No. 2021/0313343) of record, in view of Lee
Regarding Claim 13
FIG. 7 of Chung discloses a semiconductor device comprising: a peripheral circuit (PERI); an interconnection structure electrically connected to the peripheral circuit; a first dummy stack (lower DS1) located on the interconnection structure and including a dummy staircase structure; a second dummy stack (uppermost portion of DS1) located on the first dummy stack to vertically overlap the first dummy stack, wherein the second dummy stack includes a dummy sidewall including at least one protrusion (FIG. 9B); an insulating structure (190) formed on the first dummy stack and facing the dummy sidewall.
Chung is silent with respect to “a contact plug penetrating the second dummy stack and the first dummy stack, the contact plug electrically connected to the interconnection structure” and the second dummy stack “extending from the dummy staircase structure”.
FIG. 4 of Jung discloses a similar semiconductor device comprising: a peripheral circuit (30); an interconnection structure (RL) electrically connected to the peripheral circuit [0024]; a first dummy stack (DSSa) located on the interconnection structure; a second dummy stack (DSSb) located on the first dummy stack; a contact plug (VCT) penetrating the second dummy stack and the first dummy stack, and the contact plug electrically connected to the interconnection structure [0048].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chung, as taught by Jung. The ordinary artisan would have been motivated to modify Chung in the above manner for purpose of improving the degree of integration within a limited area ([0003] of Jung).
Chung as modified by Jung is silent with respect to the second dummy stack “extending from the dummy staircase structure”.
FIG. 7 of Lee discloses a similar semiconductor device comprising: a dummy stack (middle stack) including a first dummy stack (41-44) including a dummy staircase structure and a second dummy stack on the first dummy stack, wherein the second dummy stack extends from the dummy staircase structure.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chung, as taught by Lee. The ordinary artisan would have been motivated to modify Chung in the above manner for purpose of forming a semiconductor device having stable structure and characteristics (Abstract of Lee).
Regarding Claim 14
FIG. 9B of Chung discloses the plurality of protrusions protrude into the insulating structure.
Regarding Claim 15
FIG. 3 of Chung discloses a crack located between the dummy sidewall and the insulating structure.
Regarding Claim 16
FIG. 9B of Chung discloses the crack is isolated by the at least one protrusion.
Claims 31, 33 and 35 rejected under 35 U.S.C. 103 as being unpatentable over Lee, in view of Noh (U.S. Patent Pub. No. 2017/0207119).
Regarding Claim 31
FIG. 7 of Lee discloses a semiconductor device comprising: a first gate structure (right stack) including a first pad staircase structure (lower portion) and a first sidewall (upper portion) connected to the first pad staircase structure; a second gate structure (left stack) including a second pad staircase structure (lower portion) and a second sidewall (upper portion) connected to the second pad staircase structure, the second gate structure being adjacent to the first gate structure in a first direction; and a dummy stack (middle stack) disposed between the first gate structure and the second gate structure and including a first dummy sidewall (41-44) facing the first sidewall and a second dummy sidewall facing the second sidewall, wherein the first dummy sidewall and the second dummy sidewall extend in the second direction intersecting non-parallel to the first direction, wherein the first sidewall extends away from the first pad staircase structure in the second direction; and wherein the second sidewall extends away from the second pad staircase structure in the second direction.
Lee is silent with respect to “the first dummy sidewall includes a plurality of first protrusions protruding in the first direction toward the first gate structure and wherein the second dummy sidewall includes a plurality of second protrusions protruding in the first direction toward the second gate structure”.
FIG. 12D of Noh discloses a similar semiconductor device, the first dummy sidewall includes first protrusions protruding in the first direction (I-I’); the second dummy sidewall includes second protrusions protruding in the first direction; and the first dummy sidewall and the second dummy sidewall extend in the second direction (II-II’) intersecting the first direction.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lee, as taught by Noh, such that the first dummy sidewall includes first protrusions protruding in the first direction toward the first gate structure; the second dummy sidewall includes second protrusions protruding in the first direction toward the second gate structure and the first dummy sidewall and the second dummy sidewall extend in the second direction intersecting the first direction. The ordinary artisan would have been motivated to modify Lee in the above manner for purpose of forming 3D memory device with improved integration density ([0008] of Noh).
Regarding Claim 33
FIG. 12D of Noh discloses the dummy stack includes a first dummy stack and a second dummy stack on the first dummy stack, wherein the first dummy stack includes a first dummy staircase structure facing the first pad staircase structure and a second dummy staircase structure facing the second pad staircase structure, and wherein the second dummy stack includes the first dummy sidewall and the second dummy sidewall.
Regarding Claim 35
FIG. 7 of Lee discloses the first gate structure includes a first sub stack and a second sub stack on the first sub stack, the first sub stack including the first pad staircase structure and the second sub stack including the first sidewall; wherein the second gate structure includes a third sub stack and a fourth sub stack on the third sub stack, the third sub stack including the second pad staircase structure and the fourth sub stack including the second sidewall.
Claim 32 rejected under 35 U.S.C. 103 as being unpatentable over Lee and Noh, in view of Jung.
Regarding Claim 32
Lee as modified by Noh discloses Claim 31, comprising a peripheral circuit.
Lee as modified by Noh is silent with respect to “an interconnection structure electrically connected to the peripheral circuit; and a contact plug penetrating the dummy stack and electrically connected to the interconnection structure”.
FIG. 4 of Jung discloses a similar semiconductor device comprising: a peripheral circuit (30); an interconnection structure (RL) electrically connected to the peripheral circuit [0024]; a first dummy stack (DSSa) located on the interconnection structure; a second dummy stack (DSSb) located on the first dummy stack; a contact plug (VCT) penetrating the second dummy stack and the first dummy stack, and the contact plug electrically connected to the interconnection structure [0048].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lee, as taught by Jung. The ordinary artisan would have been motivated to modify Lee in the above manner for purpose of improving the degree of integration within a limited area ([0003] of Jung).
Claim 34 rejected under 35 U.S.C. 103 as being unpatentable over Chung, Jung and Lee, in view of Noh.
Regarding Claim 34
Chung as modified by Jung and Lee discloses Claim 13.
Chung as modified by Jung and Lee is silent with respect to “the contact plug penetrates one of the plurality of protrusions”.
FIG. 12E of Noh discloses a similar semiconductor device, wherein the contact plug (139) penetrates one of the plurality of protrusions.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chung, as taught by Noh. The ordinary artisan would have been motivated to modify Chung in the above manner for purpose of forming 3D memory device with improved integration density ([0008] of Noh).
Response to Arguments
Applicant’s arguments with respect to Claim 1 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Pertinent Art
Pertinent art includes Kim (U.S. Patent Pub. No. 2018/0174661), Lee (U.S. Patent Pub. No. 2021/0028104), Lee (U.S. Patent Pub. No. 2019/0378857), US 20110147818, 20120149185, 20200303392, and KM 101974352.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897
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