Attorney’s Docket Number: P202201146US01
Filing Date: 08/26/2022
Claimed Foreign Priority Date: none
Applicants: Lanzillo et al.
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the Amendment filed on 04/02/2026.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The Amendment filed on 04/02/2026, responding to the Office action mailed on 01/05/2026, has been entered. The present Office action is made with all the suggested amendments being fully considered. Applicant cancelled claims 1-8 and 15-19, and added new claims 20-32. Accordingly, pending in this application are claims 9-14 and 20-32.
Response to Amendment
Applicant’s amendments to the Drawings have overcome the objections to drawings, as previously formulated in the Non-Final Office action mailed on 01/05/2026. Accordingly, all previous objections to drawings are hereby withdrawn.
Applicant’s amendments to the Claims have overcome the claim rejections under 35 U.S.C. 102, as previously formulated in the same Office action. Accordingly, all previous claim rejections are hereby also withdrawn. However, new grounds for rejection are presented below, as necessitated by Applicant’s amendments to the claims.
Claim Objections
Claims 20, 22, and 28 are objected to because of the following informalities:
- Claim 20, L. 2: amend to -- a first metal line
- Claim 22, L. 2: amend to -- flush with the topmost surfaces of the interconnect jumper. -- in accordance with the language introduced in claim 20, L. 9-10 “wherein a topmost surface of the interlevel dielectric layer is flush with topmost surfaces of the interconnect jumper”.
- Claim 28, L. 2: amend to -- flush with the topmost surfaces of the interconnect jumper. -- in accordance with the language introduced in claim 27, L. 11-12 “wherein a topmost surface of the single interlevel dielectric layer is flush with topmost surfaces of the interconnect jumper”.
Appropriate corrections are required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 9-14 and 20-32 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jun et al. (US2019/0371724).
Regarding Claim 9, Jun (see, e.g., Figs. 1-3) shows all aspects of the instant invention including a semiconductor apparatus, comprising:
- a substrate (e.g., substrate 100)
- a first metal line (e.g., one of line-shaped contacts 170 of 174a extending in a 2nd direction) disposed on the substrate, the first metal line comprising a conductive material (see, e.g., Par. [0057]: metal pattern 162a may include, e.g., cobalt, aluminum, copper, tungsten, nickel, platinum, Au, Ag, etc.)
- a second metal line (e.g., another one of line-shaped contacts 170 of 174a extending in the 2nd direction) disposed on the substrate, the second metal line comprising the conductive material (e.g., 162a)
- a dielectric material (e.g., insulating interlayer 140) at least partially surrounding the first metal line and the second metal line
- an interconnect (e.g., connecting pattern 172 of 174a extending in a 1st direction) between the first metal line and the second metal line, the interconnect comprising the conductive material integral with the first metal line and the second metal line and extending above the first metal line and the second metal line (see, e.g., Par. [0054]: structure 174a having a single body structure).
Regarding Claim 10, Jun (see, e.g., Figs. 18-28) discloses that structure 174a is formed by a sequence of manufacturing steps comprising at least trenching, conductive material filling, and planarization, which are steps characteristic of a damascene process. Accordingly, Jun shows that the first metal line and the second metal line are damascene features comprising the conductive material.
Regarding Claim 11, Jun (see, e.g., Figs. 1-3 and Par. [0057]) shows a metal barrier (e.g., barrier pattern 160a may include, e.g., titanium, titanium nitride, tantalum, tantalum nitride, etc.) between the interconnect and the dielectric material and between each of the first metal line and the second metal line and the dielectric material.
Regarding Claim 12, Jun (see, e.g., Figs. 1-3 and Par. [0057]) shows that the metal barrier (e.g., 160a) comprises Ta, TaN, or TiN.
Regarding Claim 13, Jun (see, e.g., Figs. 1-3 and Par. [0047]) shows that the dielectric material (e.g., 140) is silicon dioxide.
Regarding Claim 14, Jun (see, e.g., Figs. 1-3 and Par. [0057]) shows the conductive material (e.g., 162a) is selected from the group consisting of tungsten, aluminum, silver, cobalt, copper, gold, ruthenium, and alloys thereof.
Regarding Claim 20, Jun (see, e.g., Figs. 5-6) shows all aspects of the instant invention including a semiconductor apparatus, comprising:
- a first metal line (e.g., one of line-shaped contacts 176 of 180a extending in a 2nd direction) embedded in an interlevel dielectric layer (e.g., insulating interlayer 140), the first metal line comprising a conductive material (see, e.g., Par. [0057]: metal pattern 162a may include, e.g., cobalt, aluminum, copper, tungsten, nickel, platinum, Au, Ag, etc.)
- a second metal line (e.g., another one of line-shaped contacts 176 of 180a extending in the 2nd direction) embedded in the interlevel dielectric layer, the second metal line comprising the conductive material (e.g., 162a)
- an interconnect jumper (e.g., connecting pattern 178 of 180a extending in a 1st direction) between and directly contacting both the first metal line and the second metal line, the interconnect jumper comprising the conductive material integral with the first metal line and the second metal line and extending above the first metal line and the second metal line (see, e.g., Par. [0081]: structure 180a having a single body structure), wherein a topmost surface of the interlevel dielectric layer is flush with topmost surfaces of the interconnect jumper, and a bottommost surface of the interlevel dielectric layer is below bottommost surfaces of both the first metal line and the second metal line (see, e.g., Fig. 6).
Regarding Claim 21, Jun (see, e.g., Figs. 5-6 and Par. [0057]) shows a single barrier layer (e.g., barrier pattern 160a may include, e.g., titanium, titanium nitride, tantalum, tantalum nitride, etc.) between and separating the first metal line, the second metal line, and the interconnect jumper from the interlevel dielectric layer.
Regarding Claim 22, Jun (see, e.g., Fig. 6) shows that a topmost surface of the single barrier layer (e.g., 160a) is flush with the topmost surface of the interconnect jumper.
Regarding Claim 23, Jun (see, e.g., Figs. 5-6 and Par. [0057]) shows that the single barrier layer (e.g., 160a) comprises Ta, TaN, or TiN.
Regarding Claim 24, Jun (see, e.g., Fig. 5) shows that a length of the interconnect jumper measured in a first lateral direction (e.g., 1st direction) is less than a length of the first metal line measured in a second lateral direction (e.g., 2nd direction), the second lateral direction being perpendicular to the first lateral direction.
Regarding Claim 25, Jun (see, e.g., Figs. 5-6 and Par. [0047]) shows that the interlevel dielectric layer (e.g., 140) is silicon dioxide.
Regarding Claim 26, Jun (see, e.g., Figs. 5-6 and Par. [0057]) shows the conductive material (e.g., 162a) is selected from the group consisting of tungsten, aluminum, silver, cobalt, copper, gold, ruthenium, and alloys thereof.
Regarding Claim 27, Jun (see, e.g., Figs. 5-6) shows all aspects of the instant invention including a semiconductor apparatus, comprising:
- a first metal line (e.g., one of line-shaped contacts 176 of 180a extending in a 2nd direction) embedded in a single dielectric layer (see, e.g., Par. [0145]: insulating interlayer 140, having insulating interlayers 124 and 138 merged with each other), the first metal line comprising a conductive material (see, e.g., Par. [0057]: metal pattern 162a may include, e.g., cobalt, aluminum, copper, tungsten, nickel, platinum, Au, Ag, etc.)
- a second metal line (e.g., another one of line-shaped contacts 176 of 180a extending in the 2nd direction) embedded in the single dielectric layer, the second metal line comprising the conductive material (e.g., 162a)
- a jumper interconnect (e.g., connecting pattern 178 of 180a extending in a 1st direction) embedded in the single dielectric layer and arranged between the first metal line and the second metal line, the jumper interconnect comprising the conductive material integral with the first metal line and the second metal line, and the jumper interconnect being above the first metal line and the second metal line (see, e.g., Par. [0081]: structure 180a having a single body structure)
- a continuous barrier layer (e.g., barrier pattern 160a may include, e.g., titanium, titanium nitride, tantalum, tantalum nitride, etc.) between and separating the first metal line, the second metal line, and the jumper interconnect from the single dielectric layer, and wherein a topmost surface of the single dielectric layer is flush with topmost surfaces of the jumper interconnect, and a bottommost surface of the single dielectric layer is below bottommost surfaces of the continuous barrier layer (see, e.g., Fig. 6).
Regarding Claim 28, Jun (see, e.g., Fig. 6) shows that a topmost surface of the continuous barrier layer (e.g., 160a) is flush with the topmost surface of the jumper interconnect.
Regarding Claim 29, Jun (see, e.g., Figs. 5-6 and Par. [0057]) shows that the continuous barrier layer (e.g., 160a) comprises Ta, TaN, or TiN.
Regarding Claim 30, Jun (see, e.g., Fig. 5) shows that a length of the jumper interconnect measured in a first horizontal direction (e.g., 1st direction) is less than a length of the first metal line measured in a second horizontal direction (e.g., 2nd direction), the second horizontal direction being perpendicular to the first horizontal direction.
Regarding Claim 31, Jun (see, e.g., Figs. 5-6 and Par. [0047]) shows that the single dielectric layer (e.g., 140) is silicon dioxide.
Regarding Claim 32, Jun (see, e.g., Figs. 5-6 and Par. [0057]) shows the conductive material (e.g., 162a) is selected from the group consisting of tungsten, aluminum, silver, cobalt, copper, gold, ruthenium, and alloys thereof.
Response to Arguments
Applicant’s remarks with respect to the claims filed on 04/02/2026 have been considered but are moot in view of the new grounds of rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional references cited disclose interconnects having a jumper configuration between two metal lines, and having aspects similar to the instant inventions.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul whose telephone number is (571) 270-5514. The examiner can normally be reached Monday-Friday 9am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814
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