DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 24, 2025 has been entered.
Response to Arguments
Regarding the previous objections to claims 10, 11, 19-21, 25, and 26, Applicant’s amendments and cancellations have either resolved the previous issues in these claims or rendered these issues moot.
Regarding the previous rejections under 35 USC 112(b), Applicant’s amendments and arguments overcame the prior issues of indefiniteness or rendered these issues moot. Accordingly, the rejections of 10, 20, 22, and 26 under 35 U.S.C. 112(b) are withdrawn.
Regarding the previous rejections under 35 USC 112(d), Applicant’s amendments and arguments overcame the prior issues of improper dependency or rendered these issues moot. Accordingly, the rejections of 10, 20, 22, and 26 under 35 U.S.C. 112(d) are withdrawn.
Regarding the rejection of the claims under 35 USC 102 and 35 USC 103, Applicant’s amendments and arguments have been fully considered but are mostly rendered moot as further search and consideration have prompted the new grounds of rejection presented herein. Tobioka has been previously cited as a primary reference in the Office Action dated October 16, 2025, and the Examiner will comment on one argument presented by Applicant (other arguments are rendered moot by the new grounds of rejection).
Applicant argues with regard to claim 21, Neither Tobioka nor Sun, whether alone or in combination, teaches or suggests the inclusion of a lower structure with an uppermost etch stop layer directly in contact with an uppermost first electrode layer.
This is factually incorrect. In FIG. 18A Tobioka, the lower structure includes dielectric layers 132 and conductive layers 146.
Tobioka teaches the topmost first insulating layer 132 may be used as an etch stop layer, [0153]. Accordingly, the uppermost 132 is an etch stop layer.
In FIG. 18A, the topmost 132 is directly in contact with the uppermost 146. Accordingly, Tobioka discloses the inclusion of a lower structure with an uppermost etch stop layer directly in contact with an uppermost first electrode layer.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 9-10, 12, 21, 23-24, 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20220344266A1 (“Tobioka”) in view of US20160071592A1 (“Nam”), further in view of US 20160343718 A1 (“Lu”), further in view of US20120003800A1 (“Lee”).
RE: Claim 9, Tobioka discloses A three-dimensional memory device (device in FIG. 18A including 100A, 200, 100B, [0098]) comprising:
a lower structure (combination of 132, 146, excluding the topmost 132 [0100], [0102]; the topmost 132 will be considered as being included in the claimed upper structure as discussed below) including a plurality of first dielectric layers (132 are dielectric oxides, [0142]) and a plurality of first electrode layers (146) that are alternately stacked on a substrate (110), and having an uppermost layer configured by an uppermost first electrode layer of the plurality of first electrode layers (In FIG. 18A, the uppermost 146 is the uppermost layer of the lower structure);
an upper structure including a plurality of second dielectric layers (232 and the topmost 132; 232 have same material as 132, [0155]) and a plurality of second electrode layers (246), which are alternately stacked on the lower structure;
a vertical trench (portion of trench filled by 165 which is between left and right portions of the topmost 132 and between left and right portions of uppermost 146, and also the left portion of trench filled by 265 directly above the edges of 132, 146 in FIG. 18A, excluding the right portion of the trench filled by 265 directly above the uppermost 132) exposing the lower structure by passing through the upper structure;
a first stairway-shaped trench (portion of trench filled by 165 defined by edges of 132, 146 in FIG. 18A, excluding the portion of trench filled by 165 which is between left and right portions of the topmost 132 and between left and right portions of uppermost 146), configured in the lower structure under the vertical trench, that communicates with the vertical trench; and
a second stairway-shaped trench (the portion of the trench filled by 265 directly above the uppermost 132, which is adjacent to 46B, [0206]) configured in the upper structure.
Tobioka does not explicitly disclose:
a plurality of memory cells connected to the plurality of first electrode layers and the plurality of second electrode layers;
wherein a thickness of the uppermost first electrode layer is different from a thickness of each of other first electrode layers underlying the uppermost first electrode layer and the plurality of second electrode layers, and
wherein a memory cell connected to the uppermost first electrode layer is configured not to store data.
However, Tobioka discloses:
The conductive layers 146 function as word lines, the conductive layers 246 function as word lines, [0100].
Each combination of a memory stack structure 55, a dielectric core 62, and a drain region 63 within an inter-tier memory opening 49 constitutes a memory opening fill structure 58. Generally, memory opening fill structures 58 are formed within the memory openings 49. Each of the memory opening fill structures 58 comprises a respective memory film 50 and a respective vertical semiconductor channel 60, [0177], see FIG. 11D.
The stack of the blocking dielectric layer 52, the charge storage layer 54, and the tunneling dielectric layer 56 constitutes a memory film 50 that stores memory bits, [0171].
Each of the memory stack structures 55 comprises a vertical stack of memory elements located at each level of the electrically conductive layers (146, 246), [0209].
In the same field of endeavor, Nam discloses:
a plurality of memory cells MC1-MC8, [0046], FIG. 4.
Nam further discloses Referring to FIG. 4, each memory cell MC of the memory block BLK1 may be either a “main memory cell MMC” or a “dummy memory cell DMC”, where a dummy memory cell DMC is connected to the dummy word line DWL and the main memory cells MMC are connected to the main word lines WL2-WL6 (main word lines MWL as shown in FIG. 3), [0048].
Nam further discloses Each memory cell may be used to store one or more data bits, [0033].
Nam further discloses The collection of word lines WL1.about.WL8 shown in the memory block BLK1 of FIG. 3 includes at least one main word line MWL and at least one dummy word line DWL. The dummy word line DWL is included as a means of protecting the main word line MWL from noise and as a means of improving the fabrication uniformity of memory cells, [0044].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure at least one of the word lines 146, 246 to be a dummy word line as taught by Nam in order to provide protection to other word lines from noise.
It would have been further obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to connect a plurality of memory cells connected to the word lines in 146, 246 and a dummy memory cell to the dummy word line in one of 146, 246 as taught by Nam in order to store data while utilizing the dummy word line as protection against noise. As the dummy word line would be used to provide protection against noise, the dummy memory cell connected to the dummy word line would not be used to store data. Further, in the same field of endeavor, Lu discloses Dummy word line layers DWLL1a, DWLL1b, DWLL2a and DWLL2b connect to dummy memory cells. A dummy memory cell, also referred to as a non-data memory cell, does not store user data, while a data memory cell is eligible to store user data, [0048]. Accordingly, the dummy memory cell in Nam would be understood as being configured not to store data.
In the same field of endeavor, Lee discloses in FIG. 56, The first sub dummy conduction pattern DWLa of the dummy conduction pattern DWL is formed uppermost, and may be thicker than the conduction patterns LSL, WL0 and WL1, [0239].
Lee identifies DWL as a dummy word line, [0078].
In FIGs. 2 and 58, the dummy conduction pattern DWL is shown thicker than each lower conduction pattern below DWL including LSL, WL0, WL1, and thicker than each upper conduction pattern above DWL including WL2, WL3, USL, [0068].
In FIG. 58, the dummy conduction pattern DWLa is shown as being the uppermost layer in the lower structure.
In FIG. 65, the dummy conduction pattern DWL is shown as being the uppermost layer in the lower structure below the middle dielectric 115, 151, and positioned below an upper structure comprising WL2, WL3, USL with dielectric 151, 152, 153, 154.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the uppermost electrode layer 146 in the lower structure as the dummy word line and to modify the uppermost electrode layer 146 to be thicker than each other conductive layer 146 below the uppermost electrode layer 146, and to be thicker than each conductive layer 246 above the uppermost electrode layer 146 as taught by Lee in order to provide more structural support, and to improve protection against noise between the upper structure 246, 232 and the lower structure including 132, and layers below the uppermost 146.
RE: Claim 10, Tobioka in view of Nam, Lu, Lee discloses: The three-dimensional memory device according to claim 9, wherein the uppermost first electrode layer configures a dummy word line (As modified, the uppermost first electrode layer 146 configures a dummy word line).
RE: Claim 12, Tobioka in view of Nam, Lu, Lee discloses: The three-dimensional memory device according to claim 9, further comprising:
a lower channel hole (lower part of hole filled by 58, Tobioka [0116]) extending to the substrate (110, [0120]) by passing through the lower structure;
an upper channel hole (upper part of hole filled by 58) communicating with the lower channel hole by passing through the upper structure; and
a cell plug (58) configured in the lower channel hole and the upper channel hole.
RE: Claim 21, Tobioka discloses A three-dimensional memory device (device in FIG. 18A including 100A, 200, 100B, [0098]) comprising:
a lower structure (combination of 132, 146, [0100], [0102]) including a plurality of first dielectric layers (132 are dielectric oxides, [0142]) and a plurality of first electrode layers (146) that are alternately stacked on a substrate (110), and having an uppermost layer configured by an etch stop layer (uppermost 132; uppermost 132 is used as an etch stop layer, [0153]) that is disposed directly on an uppermost first electrode layer (uppermost 146) of the plurality of first electrode layers (In FIG. 18A, the uppermost 132 is directly on the uppermost 146);
an upper structure including a plurality of second dielectric layers (232 and the topmost 132; 232 have same material as 132, [0155]) and a plurality of second electrode layers (246), which are alternately stacked on the lower structure;
a vertical trench (portion of trench filled by 165 which is between left and right portions of the topmost 132 and between left and right portions of uppermost 146, and also the left portion of trench filled by 265 directly above the edges of 132, 146 in FIG. 18A, excluding the right portion of the trench filled by 265 directly above the uppermost 132) exposing the lower structure by passing through the upper structure;
a first stairway-shaped trench (portion of trench filled by 165 defined by edges of 132, 146 in FIG. 18A, excluding the portion of trench filled by 165 which is between left and right portions of the topmost 132 and between left and right portions of uppermost 146), configured in the lower structure under the vertical trench, that communicates with the vertical trench; and
a second stairway-shaped trench (the portion of the trench filled by 265 directly above the uppermost 132, which is adjacent to 46B, [0206]) configured in the upper structure.
Tobioka does not explicitly disclose:
a plurality of memory cells connected to the plurality of first electrode layers and the plurality of second electrode layers;
wherein a sum of thicknesses of the uppermost first electrode layer and the etch stop layer is different from a thickness of each of other first electrode layers underlying the uppermost first electrode layer,
wherein a memory cell connected to the uppermost first electrode layer is configured not to store data.
However, Tobioka discloses:
The conductive layers 146 function as word lines, the conductive layers 246 function as word lines, [0100].
Each combination of a memory stack structure 55, a dielectric core 62, and a drain region 63 within an inter-tier memory opening 49 constitutes a memory opening fill structure 58. Generally, memory opening fill structures 58 are formed within the memory openings 49. Each of the memory opening fill structures 58 comprises a respective memory film 50 and a respective vertical semiconductor channel 60, [0177], see FIG. 11D.
The stack of the blocking dielectric layer 52, the charge storage layer 54, and the tunneling dielectric layer 56 constitutes a memory film 50 that stores memory bits, [0171].
Each of the memory stack structures 55 comprises a vertical stack of memory elements located at each level of the electrically conductive layers (146, 246), [0209].
In the same field of endeavor, Nam discloses:
a plurality of memory cells MC1-MC8, [0046], FIG. 4.
Nam further discloses Referring to FIG. 4, each memory cell MC of the memory block BLK1 may be either a “main memory cell MMC” or a “dummy memory cell DMC”, where a dummy memory cell DMC is connected to the dummy word line DWL and the main memory cells MMC are connected to the main word lines WL2-WL6 (main word lines MWL as shown in FIG. 3), [0048].
Nam further discloses Each memory cell may be used to store one or more data bits, [0033].
Nam further discloses The collection of word lines WL1.about.WL8 shown in the memory block BLK1 of FIG. 3 includes at least one main word line MWL and at least one dummy word line DWL. The dummy word line DWL is included as a means of protecting the main word line MWL from noise and as a means of improving the fabrication uniformity of memory cells, [0044].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure at least one of the word lines 146, 246 to be a dummy word line as taught by Nam in order to provide protection to other word lines from noise.
It would have been further obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to connect a plurality of memory cells connected to the word lines in 146, 246 and a dummy memory cell to the dummy word line in one of 146, 246 as taught by Nam in order to store data while utilizing the dummy word line as protection against noise. As the dummy word line would be used to provide protection against noise, the dummy memory cell connected to the dummy word line would not be used to store data. Further, in the same field of endeavor, Lu discloses Dummy word line layers DWLL1a, DWLL1b, DWLL2a and DWLL2b connect to dummy memory cells. A dummy memory cell, also referred to as a non-data memory cell, does not store user data, while a data memory cell is eligible to store user data, [0048]. Accordingly, the dummy memory cell in Nam would be understood as being configured not to store data.
In the same field of endeavor, Lee discloses in FIG. 56, The first sub dummy conduction pattern DWLa of the dummy conduction pattern DWL is formed uppermost, and may be thicker than the conduction patterns LSL, WL0 and WL1, [0239].
Lee identifies DWL as a dummy word line, [0078].
In FIGs. 2 and 58, the dummy conduction pattern DWL is shown thicker than each lower conduction pattern below DWL including LSL, WL0, WL1, and thicker than each upper conduction pattern above DWL including WL2, WL3, USL, [0068].
In FIG. 58, the dummy conduction pattern DWLa is shown as being the uppermost layer in the lower structure.
In FIG. 65, the dummy conduction pattern DWL is shown as being the uppermost layer in the lower structure below the middle dielectric 115, 151, and positioned below an upper structure comprising WL2, WL3, USL with dielectric 151, 152, 153, 154.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the uppermost electrode layer 146 in the lower structure as the dummy word line and to modify the uppermost electrode layer 146 to be thicker than each other conductive layer 146 below the uppermost electrode layer 146, and to be thicker than each conductive layer 246 above the uppermost electrode layer 146 as taught by Lee in order to provide more structural support, and to improve protection against noise between the upper structure 246, 232 and the lower structure including 132, and layers below the uppermost 146. As a result, the sum of thickness of the uppermost 146 and uppermost 132 would be greater than the thickness of each of other 146 underlying the uppermost 146.
RE: Claim 23, Tobioka in view of Nam, Lu, Lee discloses: The three-dimensional memory device according to claim 21, wherein the uppermost first electrode layer configures a dummy word line (As modified, the uppermost 146 configures a dummy word line).
RE: Claim 24, Tobioka in view of Nam, Lu, Lee discloses: The three-dimensional memory device according to claim 21, further comprising:
a lower channel hole (lower part of hole filled by 58, Tobioka [0116]) extending to the substrate (110, [0120]) by passing through the lower structure;
an upper channel hole (upper part of hole filled by 58) communicating with the lower channel hole by passing through the upper structure; and
a cell plug (58) configured in the lower channel hole and the upper channel hole.
RE: Claim 26, Tobioka in view of Nam, Lu, Lee discloses: The three-dimensional memory device according to claim 21, wherein the etch stop layer is in contacted with the uppermost first electrode layer (In FIG. 18A Tobioka, the uppermost 132 is in direct contact with the uppermost 146).
Conclusion
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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