DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
RE: the rejection of claim(s) under 35 USC 103, Applicant’s arguments and/or amendments have been fully considered but are moot as further search and consideration have prompted the new grounds of rejection presented herein.
Claim Objections
Claim 28-29, 32-33 are objected to because of the following informalities:
The term “first stairway-trench” in these claims is considered a typographical error of “first stairway-shaped trench” previously introduced. Appropriate correction is required.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 32-34 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 32 includes “a first stairway-trench” and this is indefinite as it is unclear if this refers to the same or different “a first stairway-trench” introduced in claim 28, from which claim 32 depends. As claim 32 is identical to claim 28 with the exception of its dependency, claim 32 will be interpreted as depending from claim 31, making it ultimately depend from independent claim 21.
Claim 33 includes “the stairway structures on each sidewall of the first stairway-trench” and claim 34 includes “the stairway structures” which are not introduced/lack antecedent basis. Accordingly, claim 33 will be interpreted as depending from claim 32 which provides the antecedent basis for claims 33 and 34.
With the above interpretations, the series of claims 31-34 depending from claim 21 will be similar to the series of claims 27-30 depending from claim 9.
Claim Rejections - 35 USC § 112(d)
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 32 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 32 is identical to claim 28 and depends from claim 30 which depends from claim 29 which depends from claim 28. Accordingly, claim 32 does not further limit claim 28 or claim 30.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 9-10, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20200294850A1 (“Lee”) in view of US20220344266A1 (“Tobioka”) further in view of US20160071592A1 (“Nam”), further in view of US 20160343718 A1 (“Lu”), further in view of US20120003800A1 (“Lee-2”).
RE: Claim 9, Lee discloses A three-dimensional memory device (device in FIG. 2A, [0015]; embodiments provide three-dimensional memory device, [0037]) comprising:
a lower structure (LST, [0038]) including a plurality of first layers (plurality of insulating layers 105B in LST in FIG. 2A, [0061], see FIG. 3) and a plurality of first electrode layers (plurality of conductive layers 105A in UST, [0061]) that are alternately stacked on a substrate (101; 105A and 105B are alternately stacked on 101, [0061]);
an upper structure (UST, [0038]) including a plurality of second layers (plurality of 105B in UST in FIG. 2A) and a plurality of second electrode layers (plurality of 105A in UST), which are alternately stacked on the lower structure (105A and 105B are alternately stacked on 101 in FIG. 2A, [0061]);
a plurality of memory cells (memory cells, [0062]) connected to the plurality of first electrode layers and the plurality of second electrode layers (the conductive layers 105A constituting the layers 105[1] to 105[n] included in the gate stack structure ST1 may include gate electrodes, [0062]; The gate electrodes may include word lines connected to memory cells and select lines connected to select transistors, [0062]);
a vertical trench (vertical trench as shown in Annotated FIG. 2A below) exposing the lower structure and extending in a vertical direction through the upper structure with a uniform width in a horizontal direction (Annotated FIG. 2A shows a horizontal dashed line between LST and UST; Annotated FIG. 2A shows the vertical trench exposing the lower structure LST and extending in a vertical direction through the upper structure UST with a uniform width in a horizontal direction);
a first stairway-shaped trench (first stairway-shaped trench as shown in Annotated FIG. 2A below), configured in the lower structure under the vertical trench, that communicates with the vertical trench (Annotated FIG. 2A shows the first stairway-shaped trench configured in the lower structure LST under the vertical trench, that communicates with the vertical trench); and
a second stairway-shaped trench configured in the upper structure (Annotated FIG. 2A shows a second stairway-shaped trench configured in the upper structure UST).
PNG
media_image1.png
609
987
media_image1.png
Greyscale
(Annotated FIG. 2A of Lee)
Lee does not explicitly disclose:
the plurality of first layers (105B in LST) is a plurality of first dielectric layers;
the plurality of second layers (105B in UST) is a plurality of first dielectric layers;
the lower structure having an uppermost layer configured by an uppermost first electrode layer of the plurality of first electrode layers;
wherein a thickness of the uppermost first electrode layer is different from a thickness of each of other first electrode layers underlying the uppermost first electrode layer and the plurality of second electrode layers, and
wherein a memory cell connected to the uppermost first electrode layer is configured not to store data.
However, in the same field of endeavor, Tobioka discloses in FIG. 18A:
a lower structure (combination of 132, 146, [0100]) including a plurality of first dielectric layers (132 are dielectric oxides, [0142]) and a plurality of first electrode layers (146) that are alternately stacked on a substrate (110);
an upper structure including a plurality of second dielectric layers (232; 232 have same material as 132, [0155]) and a plurality of second electrode layers (246), which are alternately stacked on the lower structure.
Accordingly, before the effective filing date of the claimed invention, there was a need to select a type of material for the insulating layers 105B in LST, UST in Lee.
Tobioka further discloses The various embodiments of the present disclosure can be employed to increase the overall device density in a semiconductor die including the three-dimensional memory device, [0233].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first and second pluralities of layers to be first and second dielectric oxide layers as taught by Tobioka in order to increase overall device density and/or this would have been obvious to try since dielectric oxide layers are identified by Tobioka as a solution for insulating layers that alternate with electrode layers in a memory device, and this would have had a reasonable expectation of success, see MPEP 2143.
In the same field of endeavor, Nam discloses:
a plurality of memory cells MC1-MC8, [0046], FIG. 4.
Nam further discloses Referring to FIG. 4, each memory cell MC of the memory block BLK1 may be either a “main memory cell MMC” or a “dummy memory cell DMC”, where a dummy memory cell DMC is connected to the dummy word line DWL and the main memory cells MMC are connected to the main word lines WL2-WL6 (main word lines MWL as shown in FIG. 3), [0048].
Nam further discloses Each memory cell may be used to store one or more data bits, [0033].
Nam further discloses The collection of word lines WL1.about.WL8 shown in the memory block BLK1 of FIG. 3 includes at least one main word line MWL and at least one dummy word line DWL. The dummy word line DWL is included as a means of protecting the main word line MWL from noise and as a means of improving the fabrication uniformity of memory cells, [0044].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure at least one of the word lines 105A to be a dummy word line and to connect a dummy memory cell to the dummy word line as taught by Nam in order to provide protection to other word lines from noise as further taught by Nam. As the dummy word line would be used to provide protection against noise, the dummy memory cell connected to the dummy word line is understood as not being used to store data.
In the same field of endeavor, Lu discloses Dummy word line layers DWLL1a, DWLL1b, DWLL2a and DWLL2b connect to dummy memory cells. A dummy memory cell, also referred to as a non-data memory cell, does not store user data, while a data memory cell is eligible to store user data, [0048]. Accordingly, the dummy memory cell from Nam would be understood as being configured not to store data.
In the same field of endeavor, Lee-2 discloses in FIG. 56, The first sub dummy conduction pattern DWLa of the dummy conduction pattern DWL is formed uppermost, and may be thicker than the conduction patterns LSL, WL0 and WL1, [0239].
Lee-2 discloses the thicknesses of the upper and lower conduction patterns LSL, WL0 to WL3 and USL may be the same, [0190].
Lee-2 identifies DWL as a dummy word line, [0078].
In FIGs. 2 and 58, the dummy conduction pattern DWL is shown thicker than each lower conduction pattern in the lower structure 130h below DWL including LSL, WL0, WL1, and thicker than each upper conduction pattern in the upper structure 160h above DWL including WL2, WL3, USL, [0068], [0090].
In FIG. 58, the dummy conduction pattern DWLa is shown as being the uppermost layer in the lower structure.
Lee-2 teaches The two dummy word lines DWL1 and DWL2 may be used as gate electrodes of the dummy cell transistors DCT, [0142].
Lee-2 further teaches When one of the memory cell transistors MCT is programmed, the dummy cell transistor DCT may be turned-off. By cutting off current by the dummy cell transistor DCT, a boosting effect may be increased. A selected memory cell transistor MCT may be more easily programmed, [0085].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the uppermost electrode layer 105A in the lower structure LST to be the uppermost layer of the lower structure LST, and to be the dummy word line which is thicker than each other conductive layer 105A below the uppermost electrode layer 106 in the lower structure LST, and to be thicker than each conductive layer 105A in the upper structure UST as taught by Lee-2 in order to provide more structural support, to improve protection against noise between the upper structure UST and lower structure LST, and/or to more easily program a selected memory cell transistor as further taught by Lee-2.
RE: Claim 10, Lee in view of Tobioka, Nam, Lu, Lee-2 discloses The three-dimensional memory device according to claim 9, wherein the uppermost first electrode layer configures a dummy word line (As modified, the uppermost first electrode layer 105A in LST configures a dummy word line).
RE: Claim 12, Lee in view of Tobioka, Nam, Lu, Lee-2 discloses) The three-dimensional memory device according to claim 9, further comprising:
a lower channel hole (Lee teaches lower hole for channel structure CH in LST, [0045]) extending to the substrate by passing through the lower structure (Lee teaches The lower structure LST is penetrated by the channel structures CH, [0045]);
an upper channel hole (Lee teaches upper hole for channel structure CH in UST; the conductive layers 105A constituting the layers 105[1] to 105[n] included in the gate stack structure ST1 may include gate electrodes surrounding the channel structures CH shown in FIGS. 1A and 1B, [0062]; the upper stack structure UST′ forming the cell structure CS, [0135]; The cell structure CS is penetrated by the channel structure CH in the cell region R1, [0135]) communicating with the lower channel hole by passing through the upper structure (Tobioka discloses 58 includes a vertical channel, [0104]; Accordingly, 58 in Tobioka is a channel structure; Tobioka FIG. 18A shows an upper part of a channel hole for channel 58 in the upper structure 232, 246 communicates with a lower part of the channel hole for channel 58 in the lower structure 132, 146, [0104]; Accordingly, it would have been obvious to modify the channel structures CH to have an upper channel hole communicating with a lower channel hole so that each channel structure CH penetrates the lower structure and upper structure in order to reduce the number of channel structures CH and prevent the need for separate channel structures for the lower and upper structures); and
a cell plug (In Lee: Each of the channel structures CH may include a semiconductor layer used as a channel region, [0039]; channel structures CH arranged in the cell region R1, [0039]) configured in the lower channel hole and the upper channel hole (Tobioka discloses The memory opening fill structures 58 can be located within memory openings that vertically extend through each layer within the first-tier alternating stack (132, 146) and the second-tier alternating stack (232, 246), [0103]; Each of the memory opening fill structures 58 comprises a respective memory film 50 and a respective vertical semiconductor channel 60, [0177]; Tobioka FIG. 18 shows 58 configured in the lower channel hole penetrating the lower structure 132, 146 and upper channel hole for 58 penetrating the upper structure 232, 246).
Claim(s) 27-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Tobioka, Nam, Lu, Lee-2 as applied to claim 27 above, and further in view of US20190043887A1 (“Lee-3”).
RE: Claim 27, Lee in view of Tobioka, Nam, Lu, Lee-2 discloses The three-dimensional memory device according to claim 9, wherein the first stairway-shaped trench includes opposite sidewalls of the uppermost first electrode layer that communicate with the vertical trench (In Lee Annotated FIG. 2A, the first stairway-shaped trench includes opposite sidewalls of the uppermost layer 105 that communicate with the vertical trench; Lee teaches Referring to FIG. 3, each of the lower layers 105[1] to 105[k], the first upper layers 105[k+1] to 105[m], and the second upper layers 105[m+1] to 105[n], which are shown in FIGS. 2A and 2B, may comprise a conductive layer 105A and an interlayer insulating layer 105B, [0061]; Accordingly, the opposite sidewalls of the uppermost layer 105 in the lower structure would include opposite sidewalls of the uppermost first electrode layer 105A which would communicate with the vertical trench).
Lee in view of Tobioka, Nam, Lu, Lee-2 does not explicitly disclose:
the width in the horizontal direction between the opposite sidewalls through the uppermost first electrode layer is the same as the uniform width.
However, in Lee FIG. 2A, the horizontal width between the opposite sidewalls of the uppermost layer 105 is the same as the uniform width of the vertical trench.
Further, Lee discloses Each of the second trench T12 and the third trenches T13 may have asymmetric sidewalls that face each other and have different gradients, [0070].
In the same field of endeavor, Lee-3 discloses (see Annotated FIG. 5 below):
a first stairway-shaped trench (first stairway-shaped trench in Annotated FIG. 5 below) includes opposite sidewalls of an uppermost first electrode layer (uppermost first electrode layer CP in lower structure in Annotated FIG. 5 below; CP are conductive patterns, [0042]) that communicate with a vertical trench (vertical trench in Annotated FIG. 5 below; Annotated FIG. 5 below shows opposite sidewalls of the uppermost CP in the lower structure communicate with the vertical trench), and the width in the horizontal direction between the opposite sidewalls through the uppermost first electrode layer is the same as the uniform width of the vertical trench (Annotated FIG. 5 below shows the width in the horizontal direction between the opposite sidewalls through the uppermost first electrode layer CP is the same as the uniform width).
Lee-3 teaches the 3D memory device may have a multilayer structure that includes conductive patterns formed at different heights and coupled to the memory cells. In order to independently transmit electrical signals to the conductive patterns formed at different heights, contact plugs have to be coupled to the conductive patterns, respectively, [0004].
PNG
media_image2.png
627
1108
media_image2.png
Greyscale
(Annotated FIG. 5 in Lee-3)
Lee-3 teaches The concave portions STS1 to STS4 each may be formed symmetrically with respect to an axis parallel to the second direction II, [0061].
Accordingly, before the effective filing date of the claimed invention, there was a need to determine if the first stairway-shaped trench would be symmetric or asymmetric.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first stairway-shaped trench to be symmetric as taught by Lee-3 in order to more independently transmit signals to the electrodes 105A formed at different heights and/or this would have been obvious to try since a symmetric stairway-shaped trench is one solution for the shape of a stairway trench identified by Lee-3 for a memory device, and this would have had a reasonable expectation of success, see MPEP 2143.
RE: Claim 28, Lee in view of Tobioka, Nam, Lu, Lee-2, Lee-3 discloses The three-dimensional memory device according to claim 27, wherein the remainder of the first stairway-trench includes a stairway structure disposed on each sidewall of the first stairway-trench (As modified, the remainder of the first stairway-trench includes a stairway structure disposed on each sidewall of the first stairway-trench, as shown in Annotated Lee-3 FIG. 5).
RE: Claim 29, Lee in view of Tobioka, Nam, Lu, Lee-2, Lee-3 discloses The three-dimensional memory device according to claim 28, wherein the stairway structures disposed on each sidewall of the first stairway-trench are symmetrical around a center of the vertical trench (As modified, the stairway structures disposed on each sidewall of the first stairway-trench are symmetrical around a vertical center line of the vertical trench).
RE: Claim 30, Lee in view of Tobioka, Nam, Lu, Lee-2, Lee-3 discloses The three-dimensional memory device according to claim 29 further comprising a plurality of contacts (In Lee FIG. 2A: 171, [0059]), wherein the stairway structures comprise pad portions (In Lee: pad regions, [0059]) of the plurality of first electrode layers (Lee teaches The stepped structure formed in each of the first and second trenches T11 and T12 and the grooves G11 to G15 may be defined by the layers 105[1] to 105[n] of the gate stack structure ST1, and exposed top surfaces of the steps may provide pad regions connected to contact plugs 171, [0059]), and wherein the plurality of contacts are disposed on the plurality of first electrode layers (Each of the contact plugs 171 shown in FIG. 2A extends to be in contact with a conductive layer 105A that is exposed in a step, [0061]).
Claim(s) 21, 23-24, 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Tobioka, further in view of Nam, further in view of Lu, further in view of Lee-2.
RE: Claim 21, Lee discloses A three-dimensional memory device (device in FIG. 2A, [0015]; embodiments provide three-dimensional memory device, [0037]) comprising:
a lower structure (LST, [0038]) including a plurality of first layers (plurality of insulating layers 105B in LST in FIG. 2A, [0061], see FIG. 3) and a plurality of first electrode layers (plurality of conductive layers 105A in UST, [0061]) that are alternately stacked on a substrate (101; 105A and 105B are alternately stacked on 101, [0061]), and having an uppermost layer configured by a layer (uppermost insulating layer 105B in uppermost 105 in LST) that is disposed directly on an uppermost first electrode layer (uppermost 105A in uppermost 105 in LST; FIG. 3 shows for each 105, 105B is disposed directly on 105A; therefore, for the uppermost 105, an uppermost 105B would be disposed directly on an uppermost 105A) of the plurality of first electrode layers (Referring to FIG. 3, each of the lower layers 105[1] to 105[k], the first upper layers 105[k+1] to 105[m], and the second upper layers 105[m+1] to 105[n], which are shown in FIGS. 2A and 2B, may comprise a conductive layer 105A and an interlayer insulating layer 105B, [0061]);
an upper structure (UST, [0038]) including a plurality of second layers (plurality of 105B in UST in FIG. 2A) and a plurality of second electrode layers (plurality of 105A in UST), which are alternately stacked on the lower structure (105A and 105B are alternately stacked on 101 in FIG. 2A, [0061]);
a plurality of memory cells (memory cells, [0062]) connected to the plurality of first electrode layers and the plurality of second electrode layers (the conductive layers 105A constituting the layers 105[1] to 105[n] included in the gate stack structure ST1 may include gate electrodes, [0062]; The gate electrodes may include word lines connected to memory cells and select lines connected to select transistors, [0062]);
a vertical trench (vertical trench as shown in Annotated FIG. 2A below) exposing the lower structure and extending in a vertical direction through the upper structure with a uniform width in a horizontal direction (Annotated FIG. 2A shows a horizontal dashed line between LST and UST; Annotated FIG. 2A shows the vertical trench exposing the lower structure LST and extending in a vertical direction through the upper structure UST with a uniform width in a horizontal direction);
a first stairway-shaped trench (first stairway-shaped trench as shown in Annotated FIG. 2A below), configured in the lower structure under the vertical trench, that communicates with the vertical trench (Annotated FIG. 2A shows the first stairway-shaped trench configured in the lower structure LST under the vertical trench, that communicates with the vertical trench); and
a second stairway-shaped trench (Annotated FIG. 2A shows a second stairway-shaped trench configured in the upper structure UST) configured in the upper structure.
PNG
media_image3.png
609
987
media_image3.png
Greyscale
(Annotated FIG. 2A Lee)
Lee does not explicitly disclose:
the plurality of first layers (105B in LST) is a plurality of first dielectric layers;
the plurality of second layers (105B in UST) is a plurality of first dielectric layers;
the layer disposed directly on the uppermost first electrode layer is an etch stop layer;
wherein a sum of thicknesses of the uppermost first electrode layer and the etch stop layer is different from the thickness of each of other first electrode layers underlying the uppermost first electrode layer,
wherein a memory cell connected to the uppermost first electrode layer is configured not to store data.
However, in the same field of endeavor, Tobioka discloses in FIG. 18A:
a lower structure (combination of 132, 146, [0100]) including a plurality of first dielectric layers (132 are dielectric oxides, [0142]) and a plurality of first electrode layers (146) that are alternately stacked on a substrate (110),
the lower structure having an uppermost layer configured by an etch stop layer (uppermost 132; uppermost 132 is used as an etch stop layer, [0153]) that is disposed directly on an uppermost first electrode layer (uppermost 146) of the plurality of electrode layers;
an upper structure including a plurality of second dielectric layers (232; 232 have same material as 132, [0155]) and a plurality of second electrode layers (246), which are alternately stacked on the lower structure.
Accordingly, before the effective filing date of the claimed invention, there was a need to select a type of material for the insulating layers 105B in LST, UST in Lee.
Tobioka further discloses The various embodiments of the present disclosure can be employed to increase the overall device density in a semiconductor die including the three-dimensional memory device, [0233].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first and second pluralities of layers to be first and second dielectric oxide layers as taught by Tobioka in order to increase overall device density and/or this would have been obvious to try since dielectric oxide layers are identified by Tobioka as a solution for insulating layers that alternate with electrode layers in a memory device, and this would have had a reasonable expectation of success, see MPEP 2143.
Tobioka discloses etching the lower trench occupied by 165 in FIGs. 3-4A before etching an upper trench occupied by 265 in FIG. 8A, [0147], [0162].
Further, Lee discloses The first groove G11 and the first preliminary grooves PG1 are extended to the first depth d1 in the stack structure 300 by the above-described etching process, [0106].
Lee further discloses The second groove G12 and the second preliminary groove PG2 are disposed at the second depth d2 in the stack structure 300 by the above-described etching process, [0112].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the uppermost insulating layer 105B in the uppermost 105 of the lower structure in Lee as an etch stop layer as taught by Tobioka in order to protect underlying layers during the etching of an upper trench.
In the same field of endeavor, Nam discloses:
a plurality of memory cells MC1-MC8, [0046], FIG. 4.
Nam further discloses Referring to FIG. 4, each memory cell MC of the memory block BLK1 may be either a “main memory cell MMC” or a “dummy memory cell DMC”, where a dummy memory cell DMC is connected to the dummy word line DWL and the main memory cells MMC are connected to the main word lines WL2-WL6 (main word lines MWL as shown in FIG. 3), [0048].
Nam further discloses Each memory cell may be used to store one or more data bits, [0033].
Nam further discloses The collection of word lines WL1.about.WL8 shown in the memory block BLK1 of FIG. 3 includes at least one main word line MWL and at least one dummy word line DWL. The dummy word line DWL is included as a means of protecting the main word line MWL from noise and as a means of improving the fabrication uniformity of memory cells, [0044].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure at least one of the word lines 105A to be a dummy word line and to connect a dummy memory cell to the dummy word line as taught by Nam in order to provide protection to other word lines from noise as further taught by Nam. As the dummy word line would be used to provide protection against noise, the dummy memory cell connected to the dummy word line is understood as not being used to store data.
In the same field of endeavor, Lu discloses Dummy word line layers DWLL1a, DWLL1b, DWLL2a and DWLL2b connect to dummy memory cells. A dummy memory cell, also referred to as a non-data memory cell, does not store user data, while a data memory cell is eligible to store user data, [0048]. Accordingly, the dummy memory cell from Nam would be understood as being configured not to store data.
In the same field of endeavor, Lee-2 discloses in FIG. 56, The first sub dummy conduction pattern DWLa of the dummy conduction pattern DWL is formed uppermost, and may be thicker than the conduction patterns LSL, WL0 and WL1, [0239].
Lee-2 discloses the thicknesses of the upper and lower conduction patterns LSL, WL0 to WL3 and USL may be the same, [0190].
Lee-2 identifies DWL as a dummy word line, [0078].
In FIGs. 2 and 58, the dummy conduction pattern DWL is shown thicker than each lower conduction pattern in the lower structure 130h below DWL including LSL, WL0, WL1, and thicker than each upper conduction pattern in the upper structure 160h above DWL including WL2, WL3, USL, [0068], [0090].
In FIG. 65, the dummy conduction pattern DWL is shown as being directly under an uppermost dielectric layer 115 in the lower structure, and positioned below an upper structure comprising WL2, WL3, USL with dielectric 151, 152, 153, 154, [0140].
Lee-2 teaches The two dummy word lines DWL1 and DWL2 may be used as gate electrodes of the dummy cell transistors DCT, [0142].
Lee-2 further teaches When one of the memory cell transistors MCT is programmed, the dummy cell transistor DCT may be turned-off. By cutting off current by the dummy cell transistor DCT, a boosting effect may be increased. A selected memory cell transistor MCT may be more easily programmed, [0085].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the uppermost electrode layer 105A in the lower structure LST to be the dummy word line which is thicker than each other conductive layer 105A below the uppermost electrode layer 106 in the lower structure LST, and to be thicker than each conductive layer 105A in the upper structure UST as taught by Lee-2 in order to provide more structural support, to improve protection against noise between the upper structure UST and lower structure LST, and/or to more easily program a selected memory cell transistor as further taught by Lee-2. As a result, the sum of thickness of the uppermost 105A and uppermost etch stop would be greater than the thickness of each of other 105A underlying the uppermost 146.
RE: Claim 23, Lee in view of Tobioka, Nam, Lu, Lee-2 discloses The three-dimensional memory device according to claim 21, wherein the uppermost first electrode layer configures a dummy word line (As modified, the uppermost first electrode layer 105A in LST configures a dummy word line).
RE: Claim 24, Lee in view of Tobioka, Nam, Lu, Lee-2 discloses The three-dimensional memory device according to claim 21, further comprising:
a lower channel hole (Lee teaches lower hole for channel structure CH in LST, [0045]) extending to the substrate by passing through the lower structure;
an upper channel hole (Lee teaches upper hole for channel structure CH in UST; the conductive layers 105A constituting the layers 105[1] to 105[n] included in the gate stack structure ST1 may include gate electrodes surrounding the channel structures CH shown in FIGS. 1A and 1B, [0062]; the upper stack structure UST′ forming the cell structure CS, [0135]; The cell structure CS is penetrated by the channel structure CH in the cell region R1, [0135]) communicating with the lower channel hole by passing through the upper structure (Tobioka discloses 58 includes a vertical channel, [0104]; Accordingly, 58 in Tobioka is a channel structure; Tobioka FIG. 18A shows an upper part of a channel hole for channel 58 in the upper structure 232, 246 communicates with a lower part of the channel hole for channel 58 in the lower structure 132, 146, [0104]; Accordingly, it would have been obvious to modify the channel structures CH to have an upper channel hole communicating with a lower channel hole so that each channel structure CH penetrates the lower structure and upper structure in order to reduce the number of channel structures CH and prevent the need for separate channel structures for the lower and upper structures); and
a cell plug (In Lee: Each of the channel structures CH may include a semiconductor layer used as a channel region, [0039]; channel structures CH arranged in the cell region R1, [0039]) configured in the lower channel hole and the upper channel hole (Tobioka discloses The memory opening fill structures 58 can be located within memory openings that vertically extend through each layer within the first-tier alternating stack (132, 146) and the second-tier alternating stack (232, 246), [0103]; Each of the memory opening fill structures 58 comprises a respective memory film 50 and a respective vertical semiconductor channel 60, [0177]; Tobioka FIG. 18 shows 58 configured in the lower channel hole penetrating the lower structure 132, 146 and upper channel hole for 58 penetrating the upper structure 232, 246).
RE: Claim 26, Lee in view of Tobioka, Nam, Lu, Lee-2 discloses The three-dimensional memory device according to claim 21, wherein the etch stop layer is in contacted with the uppermost first electrode layer (As shown in Lee FIG. 3, the uppermost insulating layer/etch stop 105B in the lower structure is in direct contact with the uppermost first electrode layer 105A).
Claim(s) 31-34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Tobioka, further in view of Nam, further in view of Lu, further in view of Lee-2 as applied to claim 21, further in view of Lee-3.
RE: Claim 31, Lee in view of Tobioka, Nam, Lu, Lee-2 discloses The three-dimensional memory device according to claim 21, wherein the first stairway-shaped trench includes opposite sidewalls of the uppermost first electrode layer and the etch stop layer that communicate with the vertical trench (In Lee Annotated FIG. 2A, the first stairway-shaped trench includes opposite sidewalls of the uppermost layer 105 that communicate with the vertical trench; Lee teaches Referring to FIG. 3, each of the lower layers 105[1] to 105[k], the first upper layers 105[k+1] to 105[m], and the second upper layers 105[m+1] to 105[n], which are shown in FIGS. 2A and 2B, may comprise a conductive layer 105A and an interlayer insulating layer 105B, [0061]; Accordingly, the opposite sidewalls of the uppermost layer 105 in the lower structure would include opposite sidewalls of the uppermost first electrode layer 105A and opposite sidewalls of the uppermost insulating layer 105B which would communicate with the vertical trench).
Lee in view of Tobioka, Nam, Lu, Lee-2 does not explicitly disclose:
the widths in the horizontal direction between the opposite sidewalls through the uppermost first electrode layer and the etch stop layer are the same as the uniform width.
However, in Lee FIG. 2A, the horizontal width between the opposite sidewalls of the uppermost layer 105 is the same as the uniform width of the vertical trench.
Further, Lee discloses Each of the second trench T12 and the third trenches T13 may have asymmetric sidewalls that face each other and have different gradients, [0070].
In the same field of endeavor, Lee-3 discloses (see Annotated FIG. 5 below):
a first stairway-shaped trench (first stairway-shaped trench in Annotated FIG. 5 below) includes opposite sidewalls of the uppermost first electrode layer and the uppermost insulating layer of a lower structure that communicate with the vertical trench (uppermost first electrode layer CP and uppermost insulating ILD in lower structure in Annotated FIG. 5 below; CP are conductive patterns, [0042]; ILD are insulating films, [0066]) that communicate with a vertical trench (vertical trench in Annotated FIG. 5 below; Annotated FIG. 5 below shows opposite sidewalls of the uppermost CP and uppermost ILD in the lower structure communicate with the vertical trench), and the widths in the horizontal direction between the opposite sidewalls through the uppermost first electrode layer and the uppermost insulating layer in the lower structure are the same as the uniform width (Annotated FIG. 5 below shows the widths in the horizontal direction between the opposite sidewalls through the uppermost first electrode layer CP and the uppermost insulating layer ILD are the same as the uniform width).
Lee-3 teaches the 3D memory device may have a multilayer structure that includes conductive patterns formed at different heights and coupled to the memory cells. In order to independently transmit electrical signals to the conductive patterns formed at different heights, contact plugs have to be coupled to the conductive patterns, respectively, [0004].
Lee-3 teaches The concave portions STS1 to STS4 each may be formed symmetrically with respect to an axis parallel to the second direction II, [0061].
Accordingly, before the effective filing date of the claimed invention, there was a need to determine if the first stairway-shaped trench would be symmetric or asymmetric.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first stairway-shaped trench to be symmetric as taught by Lee-3 in order to more independently transmit signals to the electrodes 105A formed at different heights and/or this would have been obvious to try since a symmetric stairway-shaped trench is one solution for the shape of a stairway trench identified by Lee-3 for a memory device, and this would have had a reasonable expectation of success, see MPEP 2143.
PNG
media_image4.png
627
1108
media_image4.png
Greyscale
(Annotated FIG. 5 in Lee-3)
RE: Claim 32, Lee in view of Tobioka, Nam, Lu, Lee-2, Lee-3 discloses The three-dimensional memory device according to claim 31, wherein the remainder of the first stairway-trench includes a stairway structure disposed on each sidewall of the first stairway-trench (As modified, the remainder of the first stairway-trench includes a stairway structure disposed on each sidewall of the first stairway-trench, as shown in Annotated Lee-3 FIG. 5).
RE: Claim 33, Lee in view of Tobioka, Nam, Lu, Lee-2, Lee-3 discloses The three-dimensional memory device according to claim 32, wherein the stairway structures disposed on each sidewall of the first stairway-trench are symmetrical around a center of the vertical trench (As modified, the stairway structures disposed on each sidewall of the first stairway-trench are symmetrical around a vertical center line of the vertical trench).
RE: Claim 34, Lee in view of Tobioka, Nam, Lu, Lee-2, Lee-3 discloses The three-dimensional memory device according to claim 33 further comprising a plurality of contacts (In Lee FIG. 2A: 171, [0059]), wherein the stairway structures comprise pad portions (In Lee: pad regions, [0059]) of the plurality of first electrode layers (Lee teaches The stepped structure formed in each of the first and second trenches T11 and T12 and the grooves G11 to G15 may be defined by the layers 105[1] to 105[n] of the gate stack structure ST1, and exposed top surfaces of the steps may provide pad regions connected to contact plugs 171, [0059]), and wherein the plurality of contacts are disposed on the plurality of first electrode layers (Each of the contact plugs 171 shown in FIG. 2A extends to be in contact with a conductive layer 105A that is exposed in a step, [0061]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights