Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-9 and 17-20 in the reply filed on December 1, 2025 is acknowledged. Further, new claims 21-27 are further examined below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, 17-19, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US-20200411436-A1 referred as Xie) in view of Chen (US-20160055972-A1).
Regarding claim 1. Xie discloses a semiconductor device, comprising:
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a first transistor comprising a first source/drain region ([0106], [0094], figure 20 annotated above, a first transistor #240a which contains a first source/drain region within);
a second transistor stacked on the first transistor and comprising a second source/drain region ([0106], [0094], figure 20 annotated above, a second transistor #240b is seen stacked on a first transistor #240 and also containing a second source/drain region within. Please note the ‘stack’ is seen in the perspective #1-Pers illustrated above with the second transistor #240b stacked on the first transistor #240a, the semiconductor device shown in figure 20 above, rotated to the left 90 degrees); and
a via structure disposed between a power element and the second source/drain region, wherein the via structure comprises ([0106], figure 20 annotated above, there is a via structure #290b/#295 disposed in between a power element #305 and the second source/region #240b):
a first via having a surface disposed on the power element, the first via having sidewalls ([0106], figure 20 annotated above, a first via #295 having a surface #Ref1 disposed on the power element #305); and
a second via disposed on another surface of the first via ([0106], figure 20 annotated above, a second via #290b is disposed on another surface #Ref2 of the first via #295, wherein the second via #290b is angled with respect to the first via #295. The angle is seen on the sides of the second via #290b which is not vertical).
Xie lacks the second via having second sidewalls respectively extending from the first sidewalls, wherein the second sidewalls of the second via extend at an angle with respect to the first sidewalls of the first via.
Chen discloses the second via having second sidewalls respectively extending from the first sidewalls, wherein the second sidewalls of the second via extend at an angle with respect to the first sidewalls of the first via ([0022], figure 2, the via structure #12 has a second via #1221 having second sidewalls respectively extending from the first sidewalls of the first via #1224. wherein the second sidewalls of the second via #1221 extend at an angle with respect to the first sidewalls of the first via #1224).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Xie to include wherein the second sidewalls of the second via extend at an angle with respect to the first sidewalls of the first via as taught by Chen in order to allow greater circuit versatility, extend connections across the device, and to reduce materials.
Regarding claim 2. Xie as modified discloses wherein the power element comprises a power rail ([0106], its described that the power elements #305, and #300 supply power for the transistor devices, therefore reading as power rail).
Regarding claim 3. Xie as modified discloses further comprising an additional via disposed between an additional power element and the first source/drain region ([0106], figure 20 annotated above, an additional via #290a is disposed in between the additional power element #300a and the first/source drain region #240a).
Regarding claim 4. Xie as modified discloses wherein the additional via is spaced apart from the via structure and contacts a side surface of the first source/drain region ([0106], figure 20 annotated above, the additional via #290a is spaced apart from the via structure #290b/#295 and also contacts a side surface of the first source/drain region #240a).
Regarding claim 6. Xie as modified discloses wherein the second via is angled with respect to a wafer on which the first and second transistors are disposed ([0106], [0041], figure 20 annotated above, the second via #290b is angled with respect to a wafer #110 on which the first transistor #240a and the second transistor #240b is disposed on).
Regarding claim 17. Xie discloses a integrated circuit comprising: a field-effect transistor structure comprising:
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a first field-effect transistor comprising a first source/drain region ([0106], [0094], [0034], figure 20 annotated above, a first field-effect transistor #240a which contains a first source/drain region within);
a second field-effect transistor stacked on the first field-effect transistor and comprising a second source/drain region ([0106], [0094] [0034], figure 20 annotated above, a field-effect second transistor #240b is seen stacked on a field-effect first transistor #240 and also containing a second source/drain region within. Please note the ‘stack’ is seen in the perspective #1-Pers illustrated above with the second field-effect transistor #240b stacked on the field-effect first transistor #240a); and
a via structure disposed between a power element and the second source/drain region, wherein the via structure comprises ([0106], figure 20 annotated above, there is a via structure #290b/#295 disposed in between a power element #305 and the second source/region #240b:
a first via having a surface disposed on the power element, the first via having first sidewalls ([0106], figure 20 annotated above, a first via #295 having a surface #Ref1 disposed on the power element #305); and
a second via disposed on another surface of the first via ([0106], figure 20 annotated above, a second via #290b is disposed on another surface #Ref2 of the first via #295, wherein the second via #290b is angled with respect to the first via #295. The angle is seen on the sides of the second via #290b which is not vertical).
Xie lacks the second via having second sidewalls respectively extending from the first sidewalls, wherein the second sidewalls of the second via extend at an angle with respect to the first sidewalls of the first via.
Chen discloses the second via having second sidewalls respectively extending from the first sidewalls, wherein the second sidewalls of the second via extend at an angle with respect to the first sidewalls of the first via ([0022], figure 2, the via structure #12 has a second via #1221 having second sidewalls respectively extending from the first sidewalls of the first via #1224. wherein the second sidewalls of the second via #1221 extend at an angle with respect to the first sidewalls of the first via #1224).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Xie to include wherein the second sidewalls of the second via extend at an angle with respect to the first sidewalls of the first via as taught by Chen in order to allow greater circuit versatility, extend connections across the device, and to reduce materials.
Regarding claim 18. Xie as modified discloses wherein the power element comprises a power rail ([0106], its described that the power elements #305, and #300 supply power for the transistor devices, therefore reading as power rail).
Regarding claim 19. Xie as modified discloses further comprising an additional via disposed between an additional power element and the first source/drain region ([0106], figure 20 annotated above, an additional via #290a is disposed in between the additional power element #300a and the first/source drain region #240a).
Regarding claim 21. Xie as modified discloses wherein the additional via is spaced apart from the via structure and contacts a side surface of the first source/drain region ([0106], figure 20 annotated above, the additional via #290a is spaced apart from the via structure #290b/#295 and also contacts a side surface of the first source/drain region #240a).
Regarding claim 22. Xie as modified discloses wherein the second via is angled with respect to a wafer on which the first and second field-effect transistors are disposed ([0106], [0041], figure 20 annotated above, the second via #290b is angled with respect to a wafer #110 on which the first field-effect transistor #240a and the second field-effect transistor #240b are disposed on).
Claim 5 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US-20200411436-A1 referred as Xie) and Chen (US-20160055972-A1) in view of Chang et al. (US-10700208-B2 referred as Chang).
Regarding claim 5. Xie as modified lacks wherein the second via contacts the second source/drain region at an acute angle with respect to at least one surface of the second source/drain region.
Chang discloses wherein the second via contacts the second source/drain region at an acute angle with respect to at least one surface of the second source/drain region ([col 7 line 64 – col 8 line 13], figure 4, the second via contact #401 contacts the second source/drain region #201 at an acute angle with respect to at least once surface of the second source/drain region).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Xie as modified to include the second via contacts the second source/drain region at an acute angle as taught by Chang in order to reduce manufacturing materials, improve device stability and to allow more room for additional elements.
Regarding claim 20. Xie as modified lacks wherein the second via contacts the second source/drain region at an acute angle with respect to at least one surface of the second source/drain region.
Chang discloses wherein the second via contacts the second source/drain region at an acute angle with respect to at least one surface of the second source/drain region ([col 7 line 64 – col 8 line 13], figure 4, the second via contact #401 contacts the second source/drain region #201 at an acute angle with respect to at least once surface of the second source/drain region).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Xie as modified to include the second via contacts the second source/drain region at an acute angle as taught by Chang in order to reduce manufacturing materials, improve device stability and to allow more room for additional elements.
Claims 7-9 and 23-27 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US-20200411436-A1 referred as Xie) and Chen (US-20160055972-A1) in view of Zhang et al. (US-10700064-B1 referred as Zhang).
Regarding claim 7. Xie as modified lacks wherein the first and second transistors each comprise a plurality of gate structures alternately stacked with a plurality of channel layers.
Zhang discloses wherein the first and second transistors each comprise a plurality of gate structures alternately stacked with a plurality of channel layers ([col 8 lines 14-29], figure 1a, the first transistor #D1 and second transistor #D2 consists of a plurality of gate structures #161 alternately stacked with a plurality of channel layers #116, #114, #112 and #126, #124, and #122).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Xie as modified to include the first and second transistors each comprise a plurality of gate structures alternately stacked with a plurality of channel layers as taught by Zhang in order to reduce leakage currents, improve electrostatic control and to increase its scalability.
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Regarding claim 8. Xie as modified discloses wherein the first source/drain region is connected to the plurality of channel layers corresponding to the first transistor, and the second source/drain region is connected to the plurality of channel layers corresponding to the second transistor ([0094], figure 20 annotated above with a view of figures 15-16, figure 15 annotated above, the first source/drain region #240a is connected to the plurality of channel layers #150a which is correlated to the first transistor #240a. The second source/drain region #240b is connected to the plurality of channel layers #150b correlated to the second transistor #240b).
Regarding claim 9. Xie as modified lacks wherein the first source/drain region is disposed on a lateral side of the plurality of gate structures and the plurality of channel layers corresponding to the first transistor, and the second source/drain region is disposed on a lateral side of the plurality of gate structures and the plurality of channel layers corresponding to the second transistor.
Zhang discloses wherein the first source/drain region is disposed on a lateral side of the plurality of gate structures and the plurality of channel layers corresponding to the first transistor ([col 8 lines 14-29], figure 1a, the first source/drain region #141 is disposed on a lateral side of the plurality of gate structures #161 and the plurality of channel layers #116, #114, #112 corresponding to the first transistor #D1), and the second source/drain region is disposed on a lateral side of the plurality of gate structures and the plurality of channel layers corresponding to the second transistor ([col 8 lines 14-29], figure 1a, the second source/drain region #142 is disposed on a lateral side of the plurality of gate structures #161 and the plurality of channel layers #126, #124, and #122corresponding to the second transistor #D2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Xie as modified to include the first and second transistors each comprising a source/drain region on the lateral side of its channel and gate layers as taught by Zhang in order to reduce leakage currents, improve electrostatic control and to reduce its power consumption.
Regarding claim 23. Xie as modified lacks wherein the first and second field-effect transistors each comprise a plurality of gate structures alternately stacked with a plurality of channel layers.
Zhang discloses wherein the first and second field-effect transistors each comprise a plurality of gate structures alternately stacked with a plurality of channel layers ([col 8 lines 14-29], figure 1a, the first field-effect transistor #D1 and second field-effect transistor #D2 consists of a plurality of gate structures #161 alternately stacked with a plurality of channel layers #116, #114, #112 and #126, #124, and #122).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Xie as modified to include the first and second field-effect transistors each comprise a plurality of gate structures alternately stacked with a plurality of channel layers as taught by Zhang in order to reduce leakage currents, improve electrostatic control and to increase its scalability.
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Regarding claim 24. Xie as modified discloses wherein the first source/drain region is connected to the plurality of channel layers corresponding to the first field-effect transistor ([0094], figure 20 annotated above with a view of figures 15-16, figure 15 annotated above, the first source/drain region #240a is connected to the plurality of channel layers #150a which is correlated to the first field-effect transistor #240a).
Regarding claim 25. Xie as modified discloses wherein the second source/drain region is connected to the plurality of channel layers corresponding to the second field-effect transistor ([0094], figure 20 annotated above with a view of figures 15-16, figure 15 annotated above, the second source/drain region #240b is connected to the plurality of channel layers #150b correlated to the second field-effect transistor #240b.
Regarding claim 26. Xie as modified lacks wherein the first source/drain region is disposed on a lateral side of the plurality of gate structures and the plurality of channel layers corresponding to the first field-effect transistor.
Zhang discloses wherein the first source/drain region is disposed on a lateral side of the plurality of gate structures and the plurality of channel layers corresponding to the first field-effect transistor ([col 8 lines 14-29] [col 1 lines 6-10], figure 1a, the first source/drain region #141 is disposed on a lateral side of the plurality of gate structures #161 and the plurality of channel layers #116, #114, #112 corresponding to the first field-effect transistor #D1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Xie as modified to include the first field-effect transistors each comprising a source/drain region on the lateral side of its channel and gate layers as taught by Zhang in order to reduce leakage currents, improve electrostatic control and to reduce its power consumption.
Regarding claim 27. Xie as modified lacks wherein the second source/drain region is disposed on a lateral side of the plurality of gate structures and the plurality of channel layers corresponding to the second field-effect transistor.
Zhang discloses wherein the second source/drain region is disposed on a lateral side of the plurality of gate structures and the plurality of channel layers corresponding to the second field-effect transistor ([col 8 lines 14-29], figure 1a, the second source/drain region #142 is disposed on a lateral side of the plurality of gate structures #161 and the plurality of channel layers #126, #124, and #122 corresponding to the second field-effect transistor #D2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Xie as modified to include the second field-effect transistors each comprising a source/drain region on the lateral side of its channel and gate layers as taught by Zhang in order to reduce leakage currents, improve electrostatic control and to reduce its power consumption.
Response to Amendment
Applicant's arguments filed 03/17/2026 have been fully considered but they are not persuasive.
It is noted that Applicant's arguments are related to the amended subject matter, simply stating the new amendments are not seen in the prior art. As is seen in the new rejection above, these amended features are disclosed by the prior art by new prior art. All the arguments relating to limitations previously presented and rejected in the last arguments will be addressed below.
For claims 1 and 17 .... "Applicant's amendments and arguments were persuasive. Upon further search and consideration a new rejection using a different interpretation of Xie et al. in combination with newly cited reference to Chen has been presented with regard to claim 1 and 17."
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JACOB RAUL MARIN/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818