DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Continued Examination Under 37 CFR 1.114
5. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/08/2025 has been entered.
Response to Arguments
6. Applicant’s arguments, see Claim Rejections – 35 U.S.C. § 102 and § 103, filed 9/26/2025, with respect to the rejections of claims 1 and 24 under 35 U.S.C. § 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Ohsawa, Kazuto et al. (Pub No. US 20210210428 A1) (hereinafter, Ohsawa).
Referring to the embodiment of Fig 64 below, Ohsawa anticipates the amended limitations, i.e. “the first stack further includes a first transition layer that is an uppermost first word line layer,” given that in the broadest reasonable interpretation, the first transition layer per the embodiment of Fig 64 below may be considered “an uppermost first word line layer” within the first stack (the stack below the insulating layer 180’).
Further, the first channel structure and second channel structure of Fig 64 anticipates the amended claim limitations “and the first channel structure extends alone a first line perpendicular to the semiconductor layer, the second channel structure extends into the uppermost first word line layer alone a second line perpendicular to the semiconductor laver and is coupled to the first channel structure. and the second line is different from the first line.” The first line may be different from the second line wherein the first line may be interpreted as a vertical line along channel extending from 10 to 170, whereas the second line may be interpreted as a vertical line extending from first dielectric portion 132’ immediately above the first channel structure up to 270.
7. Re claims 2, 3, 5, 6 and 9, Applicant should submit an argument under the heading “Remarks” pointing out disagreements with the examiner’s contentions. Applicant must also discuss the references applied against the claims, explaining how the claims avoid the references or distinguish from them.
Claim Rejections - 35 USC § 102
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
9. Claims 1, 4, 8, 10, 24, 27, 29, 30, 31 and 33 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ohsawa, Kazuto et al. (Pub No. US 20210210428 A1) (hereinafter, Ohsawa).
Ohsawa, Fig 49A/49B: Upper and lower array regions/Staircase regions
PNG
media_image1.png
451
703
media_image1.png
Greyscale
Re Claim 1, (Currently Amended) Ohsawa teaches a semiconductor device, comprising:
a first stack (Alternating Stack; 132/146; Fig 49A; ¶[0275]) of alternating first word line layers (Electrically conductive layers; 146; Fig 49A; Per ¶[0275] may comprise word lines for the memory elements) and first insulating layers (Insulating layers; 132; Fig 49A; ¶[0337]) over a semiconductor layer (Source-level material layers; 10; Fig 49A; ¶[0264]), the first stack including a first array region (Memory array region, lower stack below 180; 100; Fig 49A; ¶[0165]) and a first staircase region (Staircase region dielectric layers 132/146, lower staircase below 180; 200; Fig 49B; ¶[0165]) adjacent to the first array region;
a first channel structure (Vertical semiconductor channel (First channel extends from 10 to 170/180); 60; Fig 49A; ¶[0248]) extending from the semiconductor layer and through the first array region of the first stack;
a second stack (Alternating stack; 232/246; Fig 49A; ¶[0275]) of alternating second word line layers (Electrically conductive layers; 246; Fig 49A; ¶[0272]) and second insulating layers (Second insulating layers; 232; Fig 49A; ¶[0199]) over the first stack, the second stack including a second array region (Memory array region, upper stack above 180; 100; Fig 49A; ¶[0165]) over the first array region and a second staircase region (Retro-stepped dielectric material portion, upper staircase above 180; 265; Fig 49B; ¶[0165]) adjacent to the second array region and over the first staircase region; and
a second channel structure (Vertical semiconductor channel (second channel extends from 180 to 280); 60; Fig 49A; ¶[0248]) extending through the second array region of the second stack, wherein:
the first stack further includes a first transition layer (Transition layers; 132/132'/142/146/170/170’/180/180’; Fig 64; ¶[0172]) that is an uppermost first word line layer (Word line layer 146/142 below 170/170’; Fig 64) of first word line layers,
the first transition layer including a first dielectric portion (Insulating layer directly above Inter-tier dielectric layer (180/180'); 132/132'; Fig 64; ¶[0172]) in the first array region that surrounds the first channel structure,
the first transition layer being disposed between two adjacent first insulating layers (Between 132' and 170'; Fig 64) of the first insulating layers, and
the first channel structure extends alone a first line (A vertical line along channel extending from 10 to 170; Fig 64) perpendicular to the semiconductor layer,
the second channel structure extends into the uppermost first word line layer alone a second line (Line extending from first dielectric portion 132’ immediately above the first channel structure up to 270; Fig 64) perpendicular to the semiconductor laver and is coupled to the first channel structure. and the second line is different from the first line.
Ohsawa, Fig 64: Vertical close-up view of upper and lower array regions
PNG
media_image2.png
515
763
media_image2.png
Greyscale
Re Claim 4, (Original) Ohsawa the semiconductor device of claim 1, further comprising:
a slit structure (Dielectric moat structure and dielectric core; 474/678; Fig 64; ¶¶[0384-0385]) extending through the first stack (Alternating Stack; 132/142; Fig 64; ¶[0275]) and the second stack (Alternating Stack; 232/242; Fig 64; ¶[0275]) in a vertical direction (Up-down; Fig 64) perpendicular to the semiconductor layer (Source-level material layers; 10; Fig 64; ¶[0264]).
Re Claim 8, (Currently Amended) Ohsawa the semiconductor device of claim 4, wherein the slit structure (Dielectric moat structure and dielectric core; 474/678; Fig 64; ¶¶[0384-0385]) includes protrusions (Dielectric fin portions; 474F; Fig 5; ¶[0385]) that extend to the first dielectric portion (Insulating layer directly above Inter-tier dielectric layer (180/180'); 132/132'; Fig 64; ¶[0172]) of the first transition layer (Transition layers; 132/132'/170/170’/180/180’; Fig 64; ¶[0172]) in the horizontal direction (Parallel to source-level material layer (10); Fig 64).
Re Claim 10, (Original) Ohsawa teaches the semiconductor device of claim 1, wherein the first dielectric portion (Insulating layer directly above Inter-tier dielectric layer (180/180'); 132/132'; Fig 64; ¶[0172]) of the first transition layer (Transition layers; 132/132'/170/170’/180/180’; Fig 64; ¶[0172]) includes nitride (Silicon nitride; ¶[0172]).
Re Claim 24, (Currently Amended) Ohsawa teaches a memory system device, comprising:
a control circuitry (Semiconductor devices; 710 (not labelled); Fig 1A; ¶[0152]) coupled with a memory device (Memory array region/staircase region; 100/200; Fig 5; ¶[0164]); and
the memory device comprising:
a first stack (Alternating Stack; 132/146; Fig 49A; ¶[0275]) of alternating first word line layers (Electrically conductive layers; 146; Fig 49A; Per ¶[0275] may comprise word lines for the memory elements) and first insulating layers (Insulating layers; 132; Fig 49A; ¶[0337]) over a semiconductor layer (Source-level material layers; 10; Fig 49A; ¶[0264]), the first stack including a first array region (Memory array region, lower stack below 180; 100; Fig 49A; ¶[0165]) and a first staircase region (Staircase region dielectric layers 132/146, lower staircase below 180; 200; Fig 49B; ¶[0165]) adjacent to the first array region;
a first channel structure (Vertical semiconductor channel (First channel extends from 10 to 170/180); 60; Fig 49A; ¶[0248]) extending from the semiconductor layer and through the first array region of the first stack;
a second stack (Alternating stack; 232/246; Fig 49A; ¶[0275]) of alternating second word line layers (Electrically conductive layers; 246; Fig 49A; ¶[0272]) and second insulating layers (Second insulating layers; 232; Fig 49A; ¶[0199]) over the first stack, the second stack including a second array region (Memory array region, upper stack above 180; 100; Fig 49A; ¶[0165]) over the first array region and a second staircase region (Retro-stepped dielectric material portion, upper staircase above 180; 265; Fig 49B; ¶[0165]) adjacent to the second array region and over the first staircase region; and
a second channel structure (Vertical semiconductor channel (second channel extends from 180 to 280); 60; Fig 49A; ¶[0248]) extending through the second array region of the second stack, wherein:
the first stack further includes a first transition layer (Transition layers; 132/132'/142/146/170/170’/180/180’; Fig 64; ¶[0172]) that is an uppermost first word line layer (Word line layer 146/142 below 170/170’; Fig 64) of first word line layers,
the first transition layer including a first dielectric portion (Insulating layer directly above Inter-tier dielectric layer (180/180'); 132/132'; Fig 64; ¶[0172]) in the first array region that surrounds the first channel structure,
the first transition layer being disposed between two adjacent first insulating layers (Between 132' and 170'; Fig 64) of the first insulating layers, and
the first channel structure extends alone a first line (A vertical line along channel extending from 10 to 170; Fig 64) perpendicular to the semiconductor layer,
the second channel structure extends into the uppermost first word line layer alone a second line (Line extending from first dielectric portion 132’ immediately above the first channel structure up to 270; Fig 64) perpendicular to the semiconductor laver and is coupled to the first channel structure. and the second line is different from the first line.
Re Claim 27, (New) Ohsawa teaches the memory system device of claim 24, further comprising:
a slit structure (Dielectric moat structure and dielectric core; 474/678; Fig 64; ¶¶[0384-0385]) extending through the first stack (Alternating Stack; 132/142; Fig 64; ¶[0275]) and the second stack (Alternating Stack; 232/242; Fig 64; ¶[0275]) in a vertical direction (Up-down; Fig 64) perpendicular to the semiconductor layer (Source-level material layers; 10; Fig 64; ¶[0264]).
Re Claim 29, (New) Ohsawa teaches the memory system device of claim 28, wherein the slit structure (Dielectric moat structure and dielectric core; 474/678; Fig 64; ¶¶[0384-0385]) includes protrusions (Dielectric fin portions; 474F; Fig 5; ¶[0385]) that extend to the second dielectric portion (First insulating cap layer; 170/170'; Fig 49A; Per ¶[0180] may be optionally deposited over first-tier structures 132/142/170/165) of the first transition layer (Transition layers; 132/132'/170/170’/180/180’; Fig 64; ¶[0172]) in the horizontal direction (Parallel to source-level material layer (10); Fig 64).
Re Claim 30, (New) Ohsawa teaches the memory system device of claim 26, wherein the first stack (Alternating Stack; 132/146; Fig 49A; ¶[0275]) further includes a second transition layer (First insulating cap layer; 170/170'; Fig 49A; Per ¶[0180] may be optionally deposited over first-tier structures 132/142/170/165) that is positioned between the first transition layer (Insulating layer directly above Inter-tier dielectric layer (180/180'); 132/132'; Fig 64; ¶[0172]) and the first word line layers,
the second transition layer including a second dielectric portion (First insulating cap layer; 170/170'; Fig 49A; Per ¶[0180] may be optionally deposited over first-tier structures 132/142/170/165) under the first dielectric portion (Insulating layer directly above Inter-tier dielectric layer (180/180'); 132/132'; Fig 64; ¶[0172]) in the first array region (Memory array region, lower stack below 180; 100; Fig 53A; ¶[0165]) that surrounds the first channel structure (Vertical semiconductor channel (First channel extends from 10 to 170/180); 60; Fig 49A; ¶[0248]).
Re Claim 31, (New) Ohsawa teaches the memory system device of claim 24, wherein the first dielectric portion (Insulating layer directly above Inter-tier dielectric layer (180/180'); 132/132'; Fig 64; ¶[0172]) of the first transition layer (Transition layers; 132/132'/170/170’/180/180’; Fig 64; ¶[0172]) includes nitride (Silicon nitride; ¶[0172]).
Re Claim 33, (New) Ohsawa teaches the semiconductor device of claim 5, wherein the first transition layer (Transition layers; 132/132'/142/146/170/170’/180/180’; Fig 64; ¶[0172]) further includes two separate dielectric segments (Segments of 132’ on each side of 588; Fig 64) and a third conductive portion (Portion of Interconnection via structure on same layer as 132/132’; 588; Fig 49A/64; ¶[0277]) that is positioned in the first array region and between the two dielectric segments,
Claim Rejections - 35 USC § 103
10. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
11. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Ohsawa, Kazuto et al. (Pub No. US 20210210428 A1) (hereinafter, Ohsawa) as applied to Claim 1 above, and further in view of Cheng, Chen-Yu et al. (Pub No. US 20210351196 A1) (hereinafter, Cheng).
Cheng, Fig 17: Memory Device
PNG
media_image3.png
525
748
media_image3.png
Greyscale
Re Claim 2, (Previously Presented) Ohsawa does not teach the semiconductor device of claim 1, wherein the first transition layer further includes a first conductive portion that is in the first staircase region.
In the same field of endeavor, Cheng teaches the semiconductor device of claim 1, wherein the first transition layer (Horizontal layers between second tier 125 and first tier 115; Fig 17) further includes a first conductive portion (Word lines; 161; Fig 17; ¶[0067]) that is in the first staircase region (Staircase region; 2000; Fig 17; ¶[0067]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have added the first conductive portion to the first staircase region, as taught by Cheng. One would have been motivated to do this with a reasonable expectation of success in order to connect conductive pillars to the staircase region, establishing a direct connection to memory strings of cells in the first tier/array region (Cheng; ¶[0067]).
12. Claims 3, 5, 9, 26 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Ohsawa, Kazuto et al. (Pub No. US 20210210428 A1) (hereinafter, Ohsawa) as applied to Claim 1 and 24 above, and further in view of Manthena, Raja Kumar Varma et al. (Pub No. US 20240040787 A1) (hereinafter, Manthena).
Manthena, Fig 5: Transition layers and conductive portions
PNG
media_image4.png
458
720
media_image4.png
Greyscale
Re Claim 3, (Previously Presented) Ohsawa does not teach the semiconductor device of claim 1, wherein the first transition layer further includes a first conductive portion that is in the first array region.
In the same field of endeavor, Manthena teaches the semiconductor device of claim 1, wherein the first transition layer (1st transition layer; Fig 5) further includes a first conductive portion (Material on right side of voids (405) between material (341) on same layer as 1st transition layer of Fig 5 above; 505; Fig 5; ¶[0065]) that is in the first array region (Lower portion of stack 340; Fig 5).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have added the first conductive portion to the first array region, as taught by Manthena. One would have been motivated to do this with a reasonable expectation of success in order to form word lines which may connect to the bit line structures to have access and selection to memory cells within the first array region (Manthena; ¶¶[0020, 0071]).
Re Claim 5, (Currently Amended) Ohsawa does not teach the semiconductor device of claim 4, wherein the first transition layer further includes a second conductive portion positioned in the first array region and arranged between the first dielectric portion and the slit structure, and
the slit structure includes protrusions that extend to and contact the first transition layer, the first word line layers, and the second word line layers in a horizontal direction parallel to the semiconductor layer.
In the same field of endeavor, Manthena teaches the semiconductor device of claim 4, wherein the first transition layer (Material in 1st transition layer of Fig 5 above; 342; Fig 5) further includes a second conductive portion (Material on right side of voids (405) in 2nd transition layer of Fig 5 above; 505; Fig 5; ¶[0065]) is positioned in the first array region (Lower portion of stack 340; Fig 5) and arranged between the first dielectric portion (Material; 341; Fig 5; ¶[0051]; Contains nitride) and the slit structure (Trench; 370; Fig 5; ¶[0058]),
and the slit structure includes protrusions (Voids; 405; Fig 5; ¶[0064]) that extend to and contact the first transition layer, the first word line layers (Material in 1st transition layer; 505; Fig 5; Per ¶[0083] comprises a sacrificial material for etching conductor materials (505) for formation of word lines (265)), and the second word line layers (Material in 2nd transition layer; 505; Fig 5; ¶[0083]) in a horizontal direction (X-direction; Fig 5) parallel to the semiconductor layer (Substrate; 315; Fig 5; ¶[0048]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used the second conductive portion to be between the slit structure and a dielectric portion, and for the slit structure to include protrusions extending to the word line layers and transition layers, as taught by Manthena. One would have been motivated to do this with a reasonable expectation of success in order to form word lines which are electrically isolated from other structures such as local isolation regions (channels), preventing conductive portions from disturbing charge carrier flow in channels such that data may be effectively stored and retrieved in memory cells.
Re Claim 9, (Previously Presented) Ohsawa teaches the semiconductor device of claim 3, wherein the first stack (Alternating Stack; 132/146; Fig 49A; ¶[0275]) further includes a second transition layer (First insulating cap layer; 170/170'; Fig 49A; Per ¶[0180] may be optionally deposited over first-tier structures 132/142/170/165) that is positioned between the first transition layer (Insulating layer directly above Inter-tier dielectric layer (180/180'); 132/132'; Fig 64; ¶[0172]) and the first word line layers,
the second transition layer including a second dielectric portion (First insulating cap layer; 170/170'; Fig 49A; Per ¶[0180] may be optionally deposited over first-tier structures 132/142/170/165) under the first dielectric portion (Insulating layer directly above Inter-tier dielectric layer (180/180'); 132/132'; Fig 64; ¶[0172]) in the first array region (Memory array region, lower stack below 180; 100; Fig 53A; ¶[0165]) that surrounds the first channel structure (Vertical semiconductor channel (First channel extends from 10 to 170/180); 60; Fig 49A; ¶[0248]).
Re Claim 26, (New) Ohsawa does not teach the memory system device of claim 24, wherein the first transition layer further includes a first conductive portion that is in the first array region.
In the same field of endeavor, Manthena teaches the semiconductor device of claim 1, wherein the first transition layer (1st transition layer; Fig 5) further includes a first conductive portion (Material on right side of voids (405) between material (341) on same layer as 1st transition layer of Fig 5 above; 505; Fig 5; ¶[0065]) that is in the first array region (Lower portion of stack 340; Fig 5).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have added the first conductive portion to the first array region, as taught by Manthena. One would have been motivated to do this with a reasonable expectation of success in order to form word lines which may connect to the bit line structures to have access and selection to memory cells within the first array region (Manthena; ¶¶[0020, 0071]).
Re Claim 28, (New) Ohsawa does not teach the semiconductor device of claim 27, wherein the first transition layer further includes a second conductive portion positioned in the first array region and arranged between the first dielectric portion and the slit structure, and
the slit structure includes protrusions that extend to and contact the first transition layer, the first word line layers, and the second word line layers in a horizontal direction parallel to the semiconductor layer.
In the same field of endeavor, Manthena teaches the memory system device of claim 27, wherein the first transition layer (Material in 1st transition layer of Fig 5 above; 342; Fig 5) further includes a second conductive portion (Material on right side of voids (405) in 2nd transition layer of Fig 5 above; 505; Fig 5; ¶[0065]) is positioned in the first array region (Lower portion of stack 340; Fig 5) and arranged between the first dielectric portion (Material; 341; Fig 5; ¶[0051]; Contains nitride) and the slit structure (Trench; 370; Fig 5; ¶[0058]),
and the slit structure includes protrusions (Voids; 405; Fig 5; ¶[0064]) that extend to and contact the first transition layer, the first word line layers (Material in 1st transition layer; 505; Fig 5; Per ¶[0083] comprises a sacrificial material for etching conductor materials (505) for formation of word lines (265)), and the second word line layers (Material in 2nd transition layer; 505; Fig 5; ¶[0083]) in a horizontal direction (X-direction; Fig 5) parallel to the semiconductor layer (Substrate; 315; Fig 5; ¶[0048]).
13. Claims 11 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Ohsawa, Kazuto et al. (Pub No. US 20210210428 A1) (hereinafter, Ohsawa) as applied to Claims 1 and 24 above, and further in view of Alzate Vinasco, Juan G. et al. (Pub No. US 20210305255 A1) (hereinafter, Alzate).
Re Claim 11, (Original) Ohsawa teaches the semiconductor device of claim 10, wherein the first dielectric portion (Insulating layer directly above Inter-tier dielectric layer (180/180'); 132/132'; Fig 64; ¶[0172]) of the first transition layer (Insulating layer directly above Inter-tier dielectric layer (180/180'); 132/132'; Fig 64; ¶[0172]).
However, Ohsawa does not teach a dielectric portion doped with one of carbon, boron and phosphorous.
a dielectric portion (Channel layer; 107; Fig 1(b); ¶[0043]) doped with one of carbon, boron and phosphorous (Polygermanium doped with boron; ¶[0043]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined the dielectric portion of Ohsawa and dielectric portion doped with boron of Alzate. One would have been motivated to do this with a reasonable expectation of success in order create a p-type material which could have a high breakdown voltage and low dielectric constant in order to enhance current flow throughout the memory cell array.
Re Claim 32, (New) Ohsawa does not teach the memory system device of claim 31, a dielectric portion doped with one of carbon, boron and phosphorous.
In the same field of endeavor, Alzate teaches a dielectric portion (Channel layer; 107; Fig 1(b); ¶[0043]) doped with one of carbon, boron and phosphorous (Polygermanium doped with boron; ¶[0043]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined the dielectric portion of Ohsawa and dielectric portion doped with boron of Alzate. One would have been motivated to do this with a reasonable expectation of success in order create a p-type material which could have a high breakdown voltage and low dielectric constant in order to enhance current flow throughout the memory cell array.
14. Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Ohsawa, Kazuto et al. (Pub No. US 20210210428 A1) (hereinafter, Ohsawa), and further in view of Toyama, Fumiaki et al. (Pub No. US 20170179026 A1) (hereinafter, Toyama)
Re Claim 25, (New) Ohsawa does not teach the memory system device of claim 24, wherein the first transition layer further includes a first conductive portion that is in the first staircase region.
In the same field of endeavor, Toyama teaches the memory system device of claim 24, wherein the first transition layer (Conductive layer/insulating cap layer/inter-tier dielectric layer; 146/170/180; Fig 15C; ¶[0228]) further includes a first conductive portion (Conductive layer; 146; Fig 15C; ¶[0228]) that is in the first staircase region (Word line contact via region; 200; Fig 15C; ¶[0166]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have added the first transition layer further includes a first conductive portion that is in the first staircase region, as taught by Toyama. One would have been motivated to do this with a reasonable expectation of success in order to enable electrical connection to word line layers, allowing for the creation of contact pads for each layer, facilitating control of the memory cells. This structure is critical for addressing the high-density storage needs of 3D NAND technology.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOTHY EDWARD DUREN whose telephone number is (703)756-1426. The examiner can normally be reached 07:30 - 17:00 PST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/RATISHA MEHTA/Primary Examiner, Art Unit 2817
/T.E.D./
Examiner
Art Unit 2817