DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A in the reply filed on 04 April 2025 is acknowledged.
Claims 5-9,11-12,17 and 23-30 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04 April 2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 10, 13-16, and 19-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US-20210005700-A1 by Park (hereinafter PARK).
Claim 1. PARK discloses a display device (Fig. 1; [0002]), comprising:
a stretchable lower substrate (Fig. 1/10, [0064], lines 8-12); and
a pattern layer (Fig. 1/repeated U basic unit, [0057]) disposed on the lower substrate and including a plurality of plate patterns (Fig. 9/merged portions of 102a and 102b which are within boundary of 200 and which are a plurality, [0048] line 3) and a plurality of line patterns (Fig. 9/102a and 102b, [0090] lines 4-10);
a plurality of pixels disposed on each of the plurality of plate patterns (Fig. 9/OLED R, G, and B); and
a plurality of connection lines disposed on each of the plurality of line patterns to couple the plurality of pixels (Fig. 9/PL1 and PL2, [0099] lines 1-4),
wherein each of the plurality of pixels includes a plurality of insulating layers (Fig. 8 cross sectional view/at least 201 buffer layer, [0107], and 203 gate insulating layer, [0110]), and
wherein at least one of the plurality of insulating layers includes at least one extension pattern extending to the plurality of line patterns (Fig. 8/101 are defined as islands, [0051] lines 1-2, so the portion of the insulating layers extending beyond 101 is an extension pattern; see circled area in annotated Fig. 8, below).
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Annotated Figure 8 of PARK
Claim 2. PARK discloses the display device of claim 1, wherein the plurality of connection lines are disposed on the at least one extension pattern (Fig 9/PL2 is disposed on the extension pattern).
Claim 3. PARK discloses the display device of claim 1, wherein each of the plurality of pixels includes a transistor (Fig. 8/TFT) including an active layer (Fig. 8/Act), a gate electrode (Fig. 8/GE), a source electrode (Fig. 8/SE) and a drain electrode (Fig. 8/DE), a storage capacitor (Fig. 8/Cst) including an intermediate metal layer (Fig. 8/CE2), and a light emitting element (Fig. 8/OLED) driven by the transistor (Fig. 8/DE connected to OLED at 221),
wherein the plurality of insulating layers include:
a buffer layer disposed between the plate patterns and the active layer (Fig. 8/201, [0107]);
a gate insulating layer disposed between the active layer and the gate electrode (Fig. 8/203, [0110]);
a first interlayer insulating layer disposed between the gate electrode and the intermediate metal layer (Fig. 8/205, [0112]);
a second interlayer insulating layer disposed between the intermediate metal layer and the source electrode and the drain electrode (Fig. 8/207, [113]);
a passivation layer disposed on the source electrode and the drain electrode (Fig. 8/PVX, [0116]); and
a planarization layer configured to planarize the transistor (Fig. 8/209, [0119]).
Claim 4. PARK discloses the display device of claim 3, wherein the at least one extension pattern (annotated Fig. 9, below/areas between inner and outer dashed lines, highlighted with arrows) includes a first extension pattern extending from the buffer layer (annotated Fig. 8, above/201 buffer layer extends into circled extension pattern) formed on each of the plurality of plate patterns to a top surface of each of the plurality of line patterns (Fig. 8/extension areas extend to 102a and 102b).
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Annotated Figure 9 of PARK
Claim 10. PARK discloses the display device of claim 1, wherein the plurality of connection lines are connected to a plurality of pads through contact holes formed in the plurality of plate patterns (Fig. 8/PL2 is connected to contact electrode COE through contact hole CCNT, [0140] lines 1-5).
Claim 13. PARK discloses the display device of claim 1, wherein the plurality of connection lines are electrically connected to a plurality of pads through contact holes formed in the plurality of line patterns (Fig. 8/PL2 is electrically connected to contact electrode COE through contact hole CCNT, [0140] lines 10-11).
Claim 14. PARK discloses a display device (Fig. 1; [0002]), comprising:
a stretchable substrate (Fig. 1/10, [0064], lines 8-12); and
a plurality of island patterns (Fig. 9/200 which are a plurality, [0048] line 3) spaced apart from each other on the stretchable substrate (Fig. 1);
a plurality of pixels disposed on each of the plurality of island patterns (Fig. 9/OLED R, G, and B); and
a plurality of connection lines coupling the plurality of pixels (Fig. 9/PL1 and PL2, [0099] lines 1-4),
wherein each of the plurality of pixels includes a plurality of insulating layers (Fig. 8 cross sectional view/at least 201 buffer layer, [0107], and 203 gate insulating layer, [0110]), and
wherein at least one of the plurality of insulating layers overlaps the plurality of connection lines (Fig. 8/201 overlaps PL2 in region W2) and includes at least one extension pattern extending to outsides of the plurality of island patterns (Fig. 8/101 are defined as islands, [0051] lines 1-2, so the portion of the insulating layers extending beyond 101 is an extension pattern; see circled area in annotated Fig. 8, above).
Claim 15. PARK discloses the display device of claim 14, further comprising:
a plurality of connection patterns (Fig. 9/102a and 102b, [0090] lines 4-10; note that in the instant application “line patterns” may also be referred to as “connection patterns”, [0056]) coupling the plurality of island patterns (Fig. 2) and overlapping the plurality of connection lines (Fig. 9/102a and 102b overlap PL2 and PL1, respectively),
wherein the at least one extension pattern is formed on the plurality of connection patterns (annotated Fig. 9, above/extension patterns are areas between inner and outer dashed lines, highlighted with arrows, and these are on the connection patterns 102a and 102b).
Claim 16. PARK discloses the display device of claim 14, wherein the plurality of connection lines apply a driving signal to the plurality of pixels through contact holes formed in the plurality of island patterns (Fig. 8/PL2 is a power line, [0138] line 1).
Claim 19. PARK discloses a display device (Fig. 1; [0002]), comprising:
a substrate (Fig. 1/10, [0064], lines 8-12);
a plurality of plate patterns on the substrate, each plate pattern of the plurality of plate patterns (Fig. 9/merged portions of 102a and 102b which are within boundary of 200 and which are a plurality, [0048] line 3) spaced apart from each other (Fig. 1/U are spaced apart);
a plurality of line patterns coupling adjacent plate patterns of the plurality of plate patterns (Fig. 9/102a and 102b, [0090] lines 4-10);
a plurality of insulating layers on each plate pattern, the plurality of insulating layers including a first insulating layer (Fig. 8 cross sectional view/at least 201 buffer layer which is a first layer, [0107], and 203 gate insulating layer, [0110]);
an extension pattern extending from the first insulating layer and overlapping a line pattern of the plurality of line patterns (Fig. 8/101 are defined as islands, [0051] lines 1-2, so the portion of the insulating layers extending beyond 101 is an extension pattern; see circled area in annotated Fig. 8, above);
a plurality of pixels disposed on each plate pattern (Fig. 9/OLED R, G, and B); and
a plurality of connection lines coupled to the plurality of pixels (Fig. 9/PL1 and PL2, [0099] lines 1-4), the plurality of connection lines including a first connection line (PL2),
wherein the plurality of plate patterns and the plurality of line patterns are disposed on a same layer as each other (Fig. 8/200 and PL2 are disposed on 100),
wherein the first connection line is disposed on the extension pattern and the first insulating layer (Fig. 8/PL2 is disposed on extension pattern and on 201).
Claim 20. PARK discloses the display device of claim 19, wherein the first insulating layer has a first thickness and the extension pattern has a second thickness different from the first thickness (annotated Fig. 8, above/201 as a thickness t1 in 101 and a different thickness t2 where is tapers in the extension pattern).
Claim 21. PARK discloses the display device of claim 19, wherein the extension pattern has an upper surface (annotated Fig. 8 above/Up) and a side surface (annotated Fig. 8 above/Sd) extending from the upper surface, the upper surface and the side surface of the extension pattern contacting the first connection line (both Up and Sd are in indirect contact with PL2 through 202).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 18 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over PARK, in view of US-20190326383-A1 by Yamanaka (hereinafter YAMANAKA).
Claim 18. PARK discloses the display device of claim 14.
PARK does not disclose wherein the plurality of connection lines apply a driving signal to the plurality of pixels through contact holes passing through the at least one extension pattern.
YAMANAKA teaches wherein the plurality of connection lines (Fig. 11/22bb branch wiring lines) apply a driving signal (Fig. 11/12ba connects to 22bb to provide a signal wiring to 12bb gate conductive layer, [0048] lines 13-14) to the plurality of pixels ([0064] line 3) through contact holes (Fig. 11/Cb) passing through the at least one extension pattern (Fig. 11/12c first insulating layer and 12d second insulating layer).
There is motivation to provide signals to drive the organic display device (Fig. 11/30b, [0056] lines 3-4) by connection wiring that goes through the overlying first and second interlayer insulating layers. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to incorporate the connection lines of YAMANAKA into the display device of PARK to connect to the pixels.
Claim 22. PARK discloses the display device of claim 19.
PARK does not disclose it comprising:
a gate pad, the gad pad, in operation, transfers gate voltage to plurality of pixels, the gate pad disposed on the plurality of insulating layers; and
a contact hole extending from the first connection line to electrically connect to the gate pad.
YAMANAKA teaches it comprising:
a gate pad (Fig. 11/12bb), the gad pad, in operation, transfers gate voltage to plurality of pixels (12bb connects to the terminal, [0048] lines 16-17, which connects with the light-emitting element, [0007] lines 9-10), the gate pad disposed on the plurality of insulating layers (Fig. 11/12bb is disposed on 11b insulating layer – [0083] – and 12a insulating film – [0085]; and
a contact hole (Fig. 11/Cb) extending from the first connection line to electrically connect to the gate pad (Fig. 11/Cb extends from 22bb to 12bb).
There is a motivation to connect driving voltage to the gate in order to operate the light-emitting element ([0052]). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to incorporate the contact between the connection lines and gate pad of YAMANAKA into the display device of PARK to operate the light-emitting elements.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lawrence Scipioni whose telephone number is (571)272-2240. The examiner can normally be reached Monday-Friday 6:30AM-4:30PM.
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/Lawrence Scipioni/
Patent Examiner
AU 2897
17 April 2025
/Andres Munoz/ Supervisory Patent Examiner, Art Unit 2897
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