DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 10, 13-16 and 18-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US 2021/0005700).
Regarding claim 1, Park discloses a display device, comprising:
a stretchable lower substrate (100, fig. 5 and paragraphs 0062-0063); and
a pattern layer disposed on the lower substrate and including a plurality of plate patterns (101, figs. 2, 5 and paragraphs 0051-0052)
and a plurality of line patterns (102, figs. 2, 5 and paragraphs 0051, 0054);
a plurality of pixels disposed on each of the plurality of plate patterns (R, G, B, Fig. 4 and paragraphs 0070-0096); and
a plurality of connection lines disposed on each of the plurality of line patterns to couple
the plurality of pixels (PL2, fig. 4 and paragraphs 0099-0100),
wherein each of the plurality of pixels includes a plurality of insulating layers (208, 209, fig. 5), and
wherein at least one of the plurality of insulating layers includes at least one extension
pattern extending to the plurality of line patterns (208, fig. 5) and
wherein the plurality of plate patterns is disposed between the stretchable lower substrate (100,fig. 5) and at least one of the plurality of insulating layers (208, fig. 5).
Regarding claim 2, Park further discloses wherein the plurality of connection lines (PL2, fig. 5) are disposed on the at least one extension pattern (208, fig. 5).
Regarding claim 3, Park further discloses wherein each of the plurality of pixels
includes a transistor (TFT, fig. 5) including an active layer (Act, fig. 5), a gate electrode (GE, fig. 5), a source electrode (SE, fig. 5) and a drain electrode (DE, fig. 5), a storage capacitor (Cst, fig. 5) including an intermediate metal layer (CE2, fig. 5), and a light emitting element (OLED, fig. 5) driven by the transistor,
wherein the plurality of insulating layers include:
a buffer layer (201, fig. 5 and paragraph 0107) disposed between the plate patterns and the active layer (fig. 5);
a gate insulating layer (203, fig. 5 and paragraph 0108) disposed between the active layer and the gate electrode;
a first interlayer insulating layer (205, fig. 5 and paragraph 0112) disposed between the gate electrode and the intermediate metal layer;
a second interlayer insulating layer (207, fig. 5 and paragraph 0113) disposed between the intermediate metal layer and the source electrode and the drain electrode;
a passivation layer (PVX, fig. 5 and paragraph 0115) disposed on the source electrode and the drain electrode; and
a planarization layer (208, fig. 5 and paragraph 0117) configured to planarize the transistor.
Regarding claim 4, Park further discloses wherein the at least one extension
pattern includes a first extension pattern extending from the buffer layer (201, fig. 5) formed on each of the plurality of plate patterns to a top surface of each of the plurality of line patterns (fig. 5).
Regarding claim 10, Park further discloses wherein the plurality of connection lines are connected to a plurality of pads through contact holes formed in the plurality of plate patterns (CCNT, figs. 4, 5 and paragraphs 0102-0104).
Regarding claim 13, Park further discloses wherein the plurality of connection lines are electrically connected to a plurality of pads through contact holes formed in the plurality of line patterns (CCNT, figs. 4, 5 and paragraphs 0102-0104).
Regarding claim 14, Park discloses a display device, comprising:
a stretchable substrate (100, fig. 5 and paragraphs 0062-0063); and
a plurality of island patterns (101, figs. 2, 5 and paragraphs 0051-0052)
spaced apart from each other on the stretchable substrate;
a plurality of pixels (R, G, B, Fig. 4 and paragraphs 0070-0096) disposed on each of the plurality of island patterns; and
a plurality of connection lines (PL2, fig. 4 and paragraphs 0099-0100) coupling the plurality of pixels,
wherein each of the plurality of pixels includes a plurality of insulating layers (208, 209, fig. 5), and
wherein at least one of the plurality of insulating layers overlaps the plurality of
connection lines and includes at least one extension pattern extending to outsides of the plurality of island patterns (208, 209, fig. 5), and
wherein the plurality of island patterns is disposed between the stretchable substrate and at least one of the plurality of insulating layers (fig. 5).
Regarding claim 15, Park further discloses a plurality of connection patterns coupling the plurality of island patterns and overlapping the plurality of connection lines (CCNT, figs. 4, 5 and paragraphs 0102-0104),
wherein the at least one extension pattern is formed on the plurality of connection
patterns (fig. 5).
Regarding claim 16, Park further discloses wherein the plurality of connection
lines apply a driving signal to the plurality of pixels through contact holes formed in the plurality of island patterns (CCNT, figs. 4, 5 and paragraphs 0102-0104).
Regarding claim 18, Park further discloses wherein the plurality of connection
lines apply a driving signal to the plurality of pixels through contact holes passing through the at least one extension pattern (CCNT, figs. 4, 5 and paragraphs 0102-0104).
Regarding claim 19, Park discloses a display device, comprising:
a substrate (100, fig. 5 and paragraphs 0062-0063);
a plurality of plate patterns on the substrate, each plate pattern of the plurality of plate
patterns spaced apart from each other (101, figs. 2, 5 and paragraphs 0051-0052);
a plurality of line patterns coupling adjacent plate patterns of the plurality of plate
patterns (102, figs. 2, 5 and paragraphs 0051, 0054);
a plurality of insulating layers on each plate pattern (209, 208, 207, fig. 5), the plurality of insulating layers including a first insulating layer (208, fig. 5);
an extension pattern extending from the first insulating layer and overlapping a line
pattern of the plurality of line patterns (PL2, fig. 5);
a plurality of pixels (R, G, B, Fig. 4 and paragraphs 0070-0096) disposed on each plate pattern (101, fig. 5); and
a plurality of connection lines coupled to the plurality of pixels, the plurality of
connection lines including a first connection line (PL2, figs. 4-5),
wherein the plurality of plate patterns and the plurality of line patterns are disposed on a
same layer as each other (fig. 5, both disposed on layer 100),
wherein the first connection line is disposed on the extension pattern and the first
insulating layer (208, fig. 5), and
wherein the plurality of plate patterns is disposed between the substrate the first
insulating layer (fig. 5).
Regarding claim 20, Park further discloses wherein the first insulating layer (208, fig. 5) has a first thickness and the extension pattern has a second thickness different from the first thickness (fig. 5, extension pattern is portion of 208 extending beyond 101 into 102 region, fig. 5).
Regarding claim 21, Park further discloses wherein the extension pattern has an
upper surface and a side surface extending from the upper surface, the upper surface and the side surface of the extension pattern contacting the first connection line (fig. 5).
Regarding claim 22, Park further discloses a gate pad (GE, fig. 5), the gate pad, in operation, transfers gate voltage to plurality of pixels, the gate pad disposed on the plurality of insulating layers (inherent feature of operation); and
a contact hole extending from the first connection line to electrically connect to the gate
pad (CCNT, fig. 5).
Response to Arguments
Applicant's arguments filed 7/1826 have been fully considered but they are not persuasive. Applicant has amended the independent claims to include the limitation that “the plurality of plate or island patterns is disposed between the stretchable lower substrate and at least one of the plurality of insulating layers”, and argues that Park fails to disclose such features because Park merely discloses a plurality of display units 200, for which those skilled in the art would not interpret the display units 200, which define a display region, to correspond to the plurality of plate patterns that are spatially separated from one another as in the present application. Examiner disagrees, as mentioned in the above rejection, Applicant’s plate patterns or island patterns (claim 14) correspond to Park’s islands 101 for which park explicitly discloses as being spatially separated from one another (see paragraph 0052) which states, “The islands 101 are arranged to be separated or spaced apart from each other…..”. The display units 200 are formed on top of the islands (fig. 2). The at least one insulating layer can be layer 208 as mentioned in the above rejection. Applicant is advised to amend the independent claims to more precisely define Applicant’s invention.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application Publication 2018/0046221 discloses a stretchable display device.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS M MENZ whose telephone number is (571)272-1877. The examiner can normally be reached Monday-Friday 8:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DOUGLAS M MENZ/Primary Examiner, Art Unit 2897 8/11/26
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