DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/21/2026 has been entered.
Claim Objections
Claims 1, 3-9, 21-22, and 24-31 are objected to because of the following informalities:
Claim 1 recites “the semiconductor” (line 16) which should be replaced with “the semiconductor layer” for consistence with claim language.
Claim 9 recites “the semiconductor” (line 18) which should be replaced with “the semiconductor layer” for consistence with claim language.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, 6-8, 21, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0134819 to Zhang et al. (hereinafter Zhang) in view of Huo et al. (US 2020/0395373, hereinafter Huo).
With respect to claim 1, Zhang discloses a three-dimensional (3D) memory device (Zhang, Figs. 11A-11B, 19-20, ¶0001, ¶0033, ¶0038-¶0141), comprising:
a stack structure (32/46) (Zhang, Figs. 11A-11B, 19, ¶0042-¶0050, ¶0097-¶0100) comprising interleaved conductive layers (46) and dielectric layers (32) on a semiconductor layer (e.g., an upper portion of the semiconductor substrate 8);
channel structures (60) (Zhang, Figs. 11A-11B, 19, ¶0064-¶0083), each of the channel structures (60) extending through the stack structure (32/46) and in contact with the semiconductor layer (e.g., 8);
a slit structure (e.g., 184/186, extending to the isolations structure 120) (Zhang, Figs. 11B, 19, ¶0111-¶0118) extending through the stack structure (32/46);
a peripheral device (e.g., a second semiconductor die 2000 including logic die) (Zhang, Figs. 11B, 19, 20, ¶0141) disposed above the stack structure (32/46) and in electric contact (e.g., through the memory-side interconnect structures (664,666,98,665)) (Zhang, Figs. 11A-11B, 19, ¶0119-¶0122) with the channel structures (60);
an interconnect structure (e.g., backside interconnect 780 on a back-side surface of the semiconductor layer 8 and including via structure 480) (Zhang, Fig. 19-20, ¶0133-¶0136, ¶0140-¶0141) disposed below the stack structure (32/46); and
a contact (e.g., contact via 8P) (Zhang, Figs. 19-20, ¶0111-¶0112, ¶0141) extending between the peripheral device (2000) and the interconnect structure (780),
wherein the slit structure (184/186) (Zhang, Figs. 19-20, ¶0114) extends through whole of the semiconductor layer (e.g., the upper portion of the semiconductor substrate 8 including the isolations structure 120), and
the interconnect structure (e.g., backside interconnect 780 on a back-side surface of the semiconductor layer 8 and including via structure 480) (Zhang, Fig. 19-20, ¶0133-¶0136, ¶0140-¶0141) comprises a first portion (e.g., backside interconnect 780) below the semiconductor (8) away from the stack structure (32/46) and a second portion (e.g., via 480 extending through whole of the upper portion of the semiconductor substrate 8 including the isolations structure 120) extending through whole of the semiconductor layer, and the second portion (480) is in contact with the contact (8P).
Further, Zhang does not specifically disclose that a first outer width of the slit structure in a bottom portion of the stack structure is greater than a second outer width of the slit structure in a top portion of the stack structure.
However, Huo teaches forming a slit structure (140) (Huo, Figs. 1A-1B, ¶0042-¶0044, ¶0046-¶0060) penetrating the stack structure (111) with reduced susceptibility of the slit structure to the deformation and improved adhesion of the insulating layer of the slit structure to the sidewalls of the stack structure (111) in contact with the slit structure (140), wherein a width D (Huo, Figs. 1A-1B, ¶0056) of the slit structure (140) increases form the top portion toward lower portion of the slit structure, such that a first outer width of the slit structure (140) in a bottom portion of the stack structure (111) is greater than a second outer width of the slit structure in a top portion of the stack structure, in order to provide improved 3D memory device with reduced susceptibility to deformation and improved structural stability (Huo, Figs. 1A-1B, ¶0044, ¶0056).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the 3D memory device of Zhang by forming the slit structure with variable width as taught by Huo to have the 3D memory device, wherein a first outer width of the slit structure in a bottom portion of the stack structure is greater than a second outer width of the slit structure in a top portion of the stack structure, in order to provide improved 3D memory device with reduced susceptibility to deformation, improved adhesion of the insulating layer of the slit structure to the sidewalls of the stack, and improved structural stability (Huo, ¶0044, ¶0056).
Regarding claim 3, Zhang in view of Huo discloses the 3D memory device of claim 1. Further, Zhang discloses the 3D memory device, wherein the interconnect structure (780) (Zhang, Figs. 19-20, ¶0111-¶0112, ¶0141) and the peripheral device (2000) are disposed at opposite sides of the stack structure (32/46).
Regarding claim 4, Zhang in view of Huo discloses the 3D memory device of claim 1. Further, Zhang discloses the 3D memory device, further comprising: contact structures (86) (Zhang, Fig. 11A-11B, 19, ¶0111-¶0112, ¶0118) extending to the stack structure (32/46), each of the contact structures (86) in electric contact with one of the conductive layers (e.g., 46), respectively.
Regarding claim 6, Zhang in view of Huo discloses the 3D memory device of claim 4. Further, Zhang discloses the 3D memory device, wherein a stair-like structure (e.g., staircase region 300) (Zhang, Figs. 11A-11B, 19, ¶0041-¶0053) is formed between the bottom portion of the stack structure (32/46) and the top portion of the stack structure (32/46).
Regarding claim 7, Zhang in view of Huo discloses the 3D memory device of claim 4. Further, Zhang does not specifically disclose that a smooth structure is formed between the bottom portion of the stack structure and the top portion of the stack structure.
However, Huo teaches forming a slit structure (140) (Huo, Figs. 1A-1B, ¶0042-¶0044, ¶0046-¶0060) penetrating the stack structure (111) with reduced susceptibility of the slit structure to the deformation and improved adhesion of the insulating layer (142) (Huo, Figs. 1A-1B, ¶0055-¶0056) of the slit structure (140) to the sidewalls of the stack structure (111) in contact with the slit structure (140), wherein the sidewalls of the slit structure (140) (Huo, Figs. 1A-1B, ¶0055) include a plurality of protruding portions on insulating layers (104) of the stacked structure (111) and a plurality of recessed portions on conductor layers (132/123/134) of the stacked structure (111), and the insulating layer (142) on the plurality of protruding portions and the plurality of recessed portions provides a smooth structure formed between the bottom portion of the stack structure (111) and the top portion of the stack structure (111).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the 3D memory device of Zhang/Huo by forming the slit structure with sidewalls including a plurality of protruding portions and a plurality of recessed portions covered with the insulating layer as taught by Huo to have the 3D memory device, wherein a smooth structure is formed between the bottom portion of the stack structure and the top portion of the stack structure, in order to improve adhesion of the insulating layer of the slit structure to the sidewalls of the stack, and to provide improved 3D memory device with reduced susceptibility to deformation and improved structural stability (Huo, ¶0044, ¶0055-¶0056).
Regarding claim 8, Zhang in view of Huo discloses the 3D memory device of claim 1. Further, Zhang discloses the 3D memory device, wherein the peripheral device (2000) (Zhang, Figs. 19-20, ¶0138-¶0141) is in electric contact with the channel structures (60) through a distribution layer (e.g., metal lines 666) (Zhang, Figs. 19-20, ¶0121).
Regarding claim 21, Zhang in view of Huo discloses the 3D memory device of claim 1. Further, Zhang discloses the 3D memory device, wherein the slit structure (e.g., 184/186, extending to the isolations structure 120) (Zhang, Fig. 19, ¶0111-¶0118) extends through the semiconductor layer (8) farther than the channel structures (60).
Regarding claim 22, Zhang in view of Huo discloses the 3D memory device of claim 1. Further, Zhang discloses the 3D memory device, wherein the slit structure (e.g., 184/186, extending to the isolations structure 120) (Zhang, Fig. 19, ¶0111-¶0118) penetrates the semiconductor layer e.g., the upper portion of the semiconductor substrate 8 including the isolation structure 120) while the channel structures (60) do not penetrate the semiconductor layer (8).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0134819 to Zhang in view of Huo (US 2020/0395373) as applied to claim 4, and further in view of Kanno et al. (US 2019/0148392, hereinafter Kanno).
Regarding claim 5, Zhang in view of Huo discloses the 3D memory device of claim 4. Further, Zhang does not specifically disclose that the conductive layers are in electric contact with the contact structures at a portion of the conductive layers, and the portion of the conductive layers has a thickness greater than that of other portions of the conductive layers.
However, Kanno teaches forming a stack structure (46/32) (Kanno, Fig. 16A, ¶0002, ¶0004, ¶0162-¶0163) comprising conductive layer (46), wherein the conductive layers are in electric contact with the contact structures (86) at a portion (e.g., a distal end portion) of the conductive layers (46) in a stepped terrace region, and the portion of the conductive layers (46) has a thickness (t2) greater than a thickness (t1) of other portions(e.g., in the memory array region) of the conductive layers (46), to reduce the probability of electrical shorting multiple conductive layers by contact structures (86).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the 3D memory device of Zhang/Huo by forming distal end portions of the conductive layers of the stack in the stepped terrace region as taught by Kanno, wherein the distal end portions have an increased thickness to have the 3D memory device, wherein the conductive layers are in electric contact with the contact structures at a portion of the conductive layers, and the portion of the conductive layers has a thickness greater than that of other portions of the conductive layers, in order to reduce the probability of electrical shorting multiple conductive layers by contact structures, and to provide improved 3D memory device (Kanno, ¶0002, ¶0004, ¶0162-¶0163).
Claims 9, 24-25, and 27-31 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0134819 to Zhang in view of Huo (US 2020/0395373) and Lee et al. (US 2024/0389365, filing date of 04/28/2022 of foreign priority application KR 10-2022-0052911, hereinafter Lee).
With respect to claim 9, Zhang discloses a three-dimensional (3D) memory device (Zhang, Figs. 11A-11B, 19-20, ¶0001, ¶0033, ¶0038-¶0141), comprising:
a memory device, comprising:
a stack structure (32/46) (Zhang, Figs. 11A-11B, 19, ¶0042-¶0050, ¶0097-¶0100) comprising interleaved conductive layers (46) and dielectric layers (32) on a semiconductor layer (e.g., an upper portion of the semiconductor substrate 8);
channel structures (60) (Zhang, Figs. 11A-11B, 19, ¶0064-¶0083), each of the channel structures (60) extending through the stack structure (32/46) and in contact with the semiconductor layer (e.g., 8);
a slit structure (e.g., 184/186, extending to the isolations structure 120) (Zhang, Figs. 11B, 19, ¶0111-¶0118) extending through the stack structure (32/46);
a peripheral device (e.g., a second semiconductor die 2000 including logic die) (Zhang, Figs. 11B, 19, 20, ¶0141) disposed above the stack structure (32/46) and in electric contact (e.g., through the memory-side interconnect structures (664,666,98,665)) (Zhang, Figs. 11A-11B, 19, ¶0119-¶0122) with the channel structures (60);
an interconnect structure (e.g., backside interconnect 780 on a back-side surface of the semiconductor layer 8 and including via structure 480) (Zhang, Fig. 19-20, ¶0133-¶0136, ¶0140-¶0141) disposed below the stack structure (32/46); and
a contact (e.g., contact via 8P) (Zhang, Figs. 19-20, ¶0111-¶0112, ¶0141) extending between the peripheral device (2000) and the interconnect structure (780),
wherein the slit structure (184/186) (Zhang, Figs. 19-20, ¶0114) extends through whole of the semiconductor layer (e.g., the upper portion of the semiconductor substrate 8 including the isolations structure 120) and is in direct contact with the interconnect structure (789/480), and
the interconnect structure (e.g., backside interconnect 780 on a back-side surface of the semiconductor layer 8 and including via structure 480) (Zhang, Fig. 19-20, ¶0133-¶0136, ¶0140-¶0141) comprises a first portion (e.g., backside interconnect 780) below the semiconductor (8) away from the stack structure (32/46) and a second portion (e.g., via 480 extending through whole of the upper portion of the semiconductor substrate 8 including the isolations structure 120) extending through whole of the semiconductor layer, and the second portion (480) is in contact with the contact (8P).
Further, Zhang does not specifically disclose that (1) a first outer width of the slit structure in a bottom portion of the stack structure is greater than a second outer width of the slit structure in a top portion of the stack structure, (2) a memory system, comprising: a memory controller coupled to the 3D memory device and configured to control operations of the 3D memory device.
Regarding (1), Huo teaches forming a slit structure (140) (Huo, Figs. 1A-1B, ¶0042-¶0044, ¶0046-¶0060) penetrating the stack structure (111) with reduced susceptibility of the slit structure to the deformation and improved adhesion of the insulating layer of the slit structure to the sidewalls of the stack structure (111) in contact with the slit structure (140), wherein a width D (Huo, Figs. 1A-1B, ¶0056) of the slit structure (140) increases form the top portion toward lower portion of the slit structure, such that a first outer width of the slit structure (140) in a bottom portion of the stack structure (111) is greater than a second outer width of the slit structure in a top portion of the stack structure, in order to provide improved 3D memory device with reduced susceptibility to deformation and improved structural stability (Huo, Figs. 1A-1B, ¶0044, ¶0056).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the 3D memory device of Zhang by forming the slit structure with variable width as taught by Huo to have the 3D memory device, wherein a first outer width of the slit structure in a bottom portion of the stack structure is greater than a second outer width of the slit structure in a top portion of the stack structure, in order to provide improved 3D memory device with reduced susceptibility to deformation, improved adhesion of the insulating layer of the slit structure to the sidewalls of the stack, and improved structural stability (Huo, ¶0044, ¶0056).
Regarding (2), Lee teaches forming a memory system (e.g., an electronic system 1000 including a semiconductor device 1100 and a controller 1200) (Lee, Figs. 1-9, 16, ¶0037-¶0077, ¶0123-¶0131) comprising: a three-dimensional (3D) memory device (1100) (Lee, Figs. 1-4, 16, ¶0037-¶0077, ¶0123-¶0124), comprising: a memory device (e.g., NAND flash memory device) (Lee, Figs. 1-9, ¶0037-¶0077) and a memory controller (1200) (Lee, Fig. 3, ¶0129-¶0131) coupled (e.g., through the input/output pad 1101 connected to the logic circuit 1130) to the 3D memory device and configured to control operations of the 3D memory device.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the 3D memory device of Zhang by forming a memory system as taught by Lee to have a memory system, comprising: a memory controller coupled to the 3D memory device and configured to control operations of the 3D memory device, in order to provide improved an electronic system including a semiconductor device with imported electrical properties and capable of storing high-capacity data (Lee, ¶0004-¶0005, ¶0123-¶0124, ¶0129-¶0131).
Regarding claim 24, Zhang in view of Huo and Lee discloses the memory system of claim 9. Further, Zhang discloses the memory system, wherein the interconnect structure (780) (Zhang, Figs. 19-20, ¶0111-¶0112, ¶0141) and the peripheral device (2000) are disposed at opposite sides of the stack structure (32/46).
Regarding claim 25, Zhang in view of Huo and Lee discloses the memory system of claim 9. Further, Zhang discloses the memory system, further comprising: contact structures (86) (Zhang, Fig. 11A-11B, 19, ¶0111-¶0112, ¶0118) extending to the stack structure (32/46), each of the contact structures (86) in electric contact with one of the conductive layers (e.g., 46), respectively.
Regarding claim 27, Zhang in view of Huo and Lee discloses the memory system of claim 25. Further, Zhang discloses the memory system, wherein a stair-like structure (e.g., staircase region 300) (Zhang, Figs. 11A-11B, 19, ¶0041-¶0053) is formed between the bottom portion of the stack structure (32/46) and the top portion of the stack structure (32/46).
Regarding claim 28, Zhang in view of Huo and Lee discloses the memory system of claim 25. Further, Zhang does not specifically disclose that a smooth structure is formed between the bottom portion of the stack structure and the top portion of the stack structure.
However, Huo teaches forming a slit structure (140) (Huo, Figs. 1A-1B, ¶0042-¶0044, ¶0046-¶0060) penetrating the stack structure (111) with reduced susceptibility of the slit structure to the deformation and improved adhesion of the insulating layer (142) (Huo, Figs. 1A-1B, ¶0055-¶0056) of the slit structure (140) to the sidewalls of the stack structure (111) in contact with the slit structure (140), wherein the sidewalls of the slit structure (140) (Huo, Figs. 1A-1B, ¶0055) include a plurality of protruding portions on insulating layers (104) of the stacked structure (111) and a plurality of recessed portions on conductor layers (132/123/134) of the stacked structure (111), and the insulating layer (142) on the plurality of protruding portions and the plurality of recessed portions provides a smooth structure formed between the bottom portion of the stack structure (111) and the top portion of the stack structure (111).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the memory system of Zhang/Huo/Lee by forming the slit structure with sidewalls including a plurality of protruding portions and a plurality of recessed portions covered with the insulating layer as taught by Huo to have the memory system, wherein a smooth structure is formed between the bottom portion of the stack structure and the top portion of the stack structure, in order to improve adhesion of the insulating layer of the slit structure to the sidewalls of the stack, and to provide improved 3D memory device with reduced susceptibility to deformation and improved structural stability (Huo, ¶0044, ¶0055-¶0056).
Regarding claim 29, Zhang in view of Huo and Lee discloses the memory system of claim 9. Further, Zhang discloses the memory system, wherein the peripheral device (2000) (Zhang, Figs. 19-20, ¶0138-¶0141) is in electric contact with the channel structures (60) through a distribution layer (e.g., metal lines 666) (Zhang, Figs. 19-20, ¶0121).
Regarding claim 30, Zhang in view of Huo and Lee discloses the memory system of claim 9. Further, Zhang discloses the memory system, wherein the slit structure (e.g., 184/186, extending to the isolations structure 120) (Zhang, Fig. 19, ¶0111-¶0118) extends through the semiconductor layer (8) farther than the channel structures (60).
Regarding claim 31, Zhang in view of Huo and Lee discloses the memory system of claim 9. Further, Zhang discloses the memory system, wherein the slit structure (e.g., 184/186, extending to the isolations structure 120) (Zhang, Fig. 19, ¶0111-¶0118) penetrates the semiconductor layer e.g., the upper portion of the semiconductor substrate 8 including the isolation structure 120) while the channel structures (60) do not penetrate the semiconductor layer (8).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0134819 to Zhang in view of Huo (US 2020/0395373) and Lee (US 2024/0389365) as applied to claim 25, and further in view of Kanno (US 2019/0148392).
Regarding claim 26, Zhang in view of Huo and Lee discloses the memory system of claim 25. Further, Zhang does not specifically disclose that the conductive layers are in electric contact with the contact structures at a portion of the conductive layers, and the portion of the conductive layers has a thickness greater than that of other portions of the conductive layers.
However, Kanno teaches forming a stack structure (46/32) (Kanno, Fig. 16A, ¶0002, ¶0004, ¶0162-¶0163) comprising conductive layer (46), wherein the conductive layers are in electric contact with the contact structures (86) at a portion (e.g., a distal end portion) of the conductive layers (46) in a stepped terrace region, and the portion of the conductive layers (46) has a thickness (t2) greater than a thickness (t1) of other portions(e.g., in the memory array region) of the conductive layers (46), to reduce the probability of electrical shorting multiple conductive layers by contact structures (86).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the memory system of Zhang/Huo/Lee by forming distal end portions of the conductive layers of the stack in the stepped terrace region as taught by Kanno, wherein the distal end portions have an increased thickness to have the memory system, wherein the conductive layers are in electric contact with the contact structures at a portion of the conductive layers, and the portion of the conductive layers has a thickness greater than that of other portions of the conductive layers, in order to reduce the probability of electrical shorting multiple conductive layers by contact structures, and to provide improved 3D memory device (Kanno, ¶0002, ¶0004, ¶0162-¶0163).
Response to Arguments
Applicant’s arguments with respect to claims 1, 3-9, 21-22, and 24-31 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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