DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1-22, and 25 remain pending in this application. Claims 12-22 remain withdrawn. Acknowledgement is made of the amendment received 03/02/2026. Claims 1 and 11 are amended.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Korea on 03/08/2022. It is noted, however, that applicant has not filed a certified copy of the KR 10-2022-0029233 application as required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 2, 4-7, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al (KR 20210040708 A, English translation of description provided in a previous office action, hereafter Choi) in view of Kim et al (US 20160307999 A1, hereafter Kim), Park et al (US 20120261747 A1, hereafter Park), and Yamashita et al (US 20110309416 A1, hereafter Yamashita).
Regarding claim 1, Choi teaches: A semiconductor device (Choi ¶0016, fig 1, 2B) comprising: a device isolation layer (Choi 112, 122-2), buried in an isolation trench (Choi 112T) of a substrate (Choi 110) defining a plurality of active regions (Choi AC)(Choi ¶0017, “A plurality of active areas (AC) defined by a device isolation film (112)”) in the substrate (Choi ¶0017, “element isolation film (112) … fills an element isolation trench (112T) formed in the substrate (110)”, therefore under a broadest reasonable interpretation, 112 is buried in 112T),
the device isolation layer (Choi 112, 122-2) including:
a first region (Choi R1, annotated fig 1/2B below) where the active regions are spaced apart from each other at a first interval (Choi R1, annotated fig 1/2B) along a first direction (Choi X dir, annotated fig 1/2B) and
a second region (Choi R2, annotated fig 1/2B) where the active regions are spaced apart from each other at a second interval (Choi R2, annotated fig 1/2B) along the first direction (Choi X dir, annotated fig 1/2B),
the second interval being wider than the first interval (Choi R2 > R1, annotated fig 1/2B);
a gate trench (Choi 120T2) extending in the first direction (Choi X dir, annotated fig 1/2B)(Choi ¶0019) to cross the active regions (Choi AC) and the device isolation layer (Choi 112, 122-2)(Choi TP2A, TP2B, ¶0021, annotated fig 1/2B); and
a buried gate structure (Choi 120G2, 124-2, at least buried below 142, annotated fig 2b) formed in the gate trench (Choi 120T2)(Choi annotated fig 2b, 2a).
Choi does not teach: a hydrogen containing layer disposed between the substrate and an air gap, wherein the second region of the device isolation layer includes the air gap in a lower portion, wherein the air gap includes hydrogen.
Kim, in the same field of endeavor of semiconductor device manufacturing, teaches: a device isolation region (Kim I1, I2, fig 1, ¶0033), buried in an isolation trench (Kim 103, 104) of a substrate (Kim 100) defining a plurality of active regions (Kim ACT, 102I) in the substrate (Kim ¶0033, 0040, “active region ACT may be defined by the first and second device isolation regions I1 and I2”), wherein
a second region (Kim I2) of the device isolation region includes an air gap (Kim AG, 109, ¶0033) in a lower portion (Kim 104L, fig 2B, ¶0010, “air gap may be formed in the lower isolation trench”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the second region of the device isolation layer of Choi to include an air gap, as taught by Kim, in order to reduce parasitic capacitance between neighboring active regions and/or buried bit lines of the device, thus improving performance (Kim ¶0005, 0035, 0055, 0197).
Choi in view of Kim does not explicitly teach: a hydrogen containing layer disposed between the substrate and an air gap, wherein the air gap includes hydrogen.
Kim further teaches: a liner layer (Kim 20A, ¶0073, “silicon oxide”) disposed between the substrate (Kim 100) and the air gap (Kim AG)(Kim fig 4F, ¶0073, the applicants “hydrogen containing layer” corresponds to liner oxide layer 104, a silicon oxide layer (spec ¶0039) that is transformed into a “hydrogen containing layer” through processing (spec ¶0041). Similarly, Kim 20A is the same material in the same structural position. See MPEP 2112.01, 2113).
Park, in the same field of endeavor of semiconductor device manufacturing, teaches: an silicon oxide layer containing hydrogen (Park 150, ¶0044, 0069, 0071, “containing hydroxide ions (OH-) or hydrogen ions (H+)”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the liner layer Choi in view of Kim to contain hydrogen, as taught by Park, such that “a hydrogen containing layer [is] disposed between the substrate and an air gap”, in order to passivate dangling bonds while providing a shorter hydrogen diffusion path (Park ¶0057), thereby reducing interface trap density and improving refresh characteristics (Park ¶0047, 0053).
Choi in view of Kim and Park does not explicitly teach: wherein the air gap includes hydrogen.
Yamashita, in the same field of endeavor of semiconductor device manufacturing, and in at least one embodiment, teaches: an air gap (Yamashita 55) includes hydrogen (Yamashita ¶0062).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the air gap of Choi in view of Kim and Park to be filled with hydrogen, and such that “the air gap includes hydrogen”, in order to reduce the dielectric constant of the air gap (Yamashita ¶0062), thereby reducing a capacitive effect (Yamashita ¶0062) between neighboring active regions and/or buried bit lines of the device, thus improving performance (Kim ¶0005, 0035, 0055, 0197).
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Choi, annotated fig 2b (left) and 1 (right)
Regarding claim 2, Choi in view of Kim, Park, and Yamashita teaches: The semiconductor device of claim 1, wherein the air gap (Choi 112, 122-2 as modified to include Kim AG, 109, and as further modified by Yamashita) is positioned at a lower level than the buried gate structure (Choi 120G2, similar to Kim G1, G2, 120)(Choi annotated fig 2b, 112 is below 120G2, similar to Kim fig 2B, 109 is below a buried gate structure G1, G2, 120).
Regarding claim 4, Choi in view of Kim, Park, and Yamashita teaches: The semiconductor device of claim 1, wherein a bottom surface (Choi Surface 1, annotated fig 1/2B) of the gate trench (Choi 120T2) in the first region (Choi R1, annotated fig 1/2B) of the device isolation layer (Choi 112, 122-2 as modified to include Kim AG, 109, and as further modified by Yamashita) is positioned at a lower level than a bottom surface (Choi TP2A) of the gate trench (Choi 120T2) in the active region (Choi AC)(Choi annotated fig 2B).
Regarding claim 5, Choi in view of Kim, Park, and Yamashita teaches: The semiconductor device of claim 1, wherein a bottom surface (Choi TP2B) of the gate trench (Choi 120T2) in the second region (Choi R2, annotated fig 1/2B) of the device isolation layer (Choi 112, 122-2 as modified to include Kim AG, 109, and as further modified by Yamashita) is positioned at a lower level than a bottom surface (Choi TP2A) of the gate trench (Choi 120T2) in the active region (Choi AC)(Choi annotated fig 2B, ¶0021).
Regarding claim 6, Choi in view of Kim, Park, and Yamashita teaches: The semiconductor device of claim 1, wherein the device isolation layer (Choi 112, 122-2 as modified to include Kim AG, 109, and as further modified by Yamashita) has different insulating structures (Choi has at least different width and depth, similarly Kim teaches I2 differs from I1 by inclusion of an air gap AG, 109) in the first region (Choi R1, annotated fig 1/2B) and the second region (Choi R2, annotated fig 1/2B)(Choi annotated fig 1/2B).
Regarding claim 7, Choi in view of Kim, Park, and Yamashita teaches: The semiconductor device of claim 1, wherein the device isolation layer (Choi 112, 122-2 as modified to include Kim AG, 109, and as further modified by Yamashita) of the first region (Choi R1, annotated fig 1/2B) includes an oxide layer (Choi 124-1, 124-2, ¶0027, fig 2A, “… include at least one of silicon oxide …”, similar to Kim 110, 111, ¶0033 “I1 and I2 may include one or more of silicon oxide …”, in 103, I1, and Kim 15, 16, in 13, I1, ¶0061-0062, fig 8G).
Regarding claim 25, Choi in view of Kim, Park, and Yamashita teaches: The semiconductor device of claim 1, including an interface (Choi an interface between 122-2 and 110, similar to Kim 106) between the substrate (Choi 110, similar to Kim 100) and the buried gate structure (Choi 120G2, similar to Kim G1, G2, 120), and the hydrogen (Kim AG as modified by Yamashita to include hydrogen).
Choi in view of Kim, Park, and Yamashita does not explicitly teach: an interface includes the hydrogen diffused from the air gap.
Park further teaches: an interface (Park 102, ¶0047) between a substrate (Park 100) and a buried gate structure (Park 135, ¶0037, fig 1C)(Park 110, fig 1C) includes diffused hydrogen (Park ¶0045).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the interface of Choi in view of Kim, Park, and Yamashita to include diffused hydrogen, as taught by Park, in order to reduce interface defects by combining with dangling bonds (Park ¶0051), thereby improving the electrical characteristics of the device (Park ¶0081).
Further, the claim recites “hydrogen diffused from the air gap”, which is a process limitation that does not appear to impart a distinct structural characteristic to the device. The process of forming a device is not germane to the issue of patentability of the device itself (MPEP 2113). Therefore, this limitation has not been given patentable weight. In this instant case, “diffused from the air gap” describes a process or mechanism by which hydrogen reaches the interface, and does not appear to impart a distinctive structural characteristic. Hydrogen atoms at an interface are chemically identical regardless of their source.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al (KR 20210040708 A, English translation of description provided in a previous office action, hereafter Choi) in view of Kim et al (US 20160307999 A1, hereafter Kim), Park et al (US 20120261747 A1, hereafter Park), and Yamashita et al (US 20110309416 A1, hereafter Yamashita), as applied to claim 1, and further in view of Kim et al (US 20140353743 A1, hereafter Kim-743).
Regarding claim 3, Choi in view of Kim, Park, and Yamashita teaches: The semiconductor device of claim 1, including a bottom surface (Choi Surface 1, annotated fig 1/2B) of the gate trench (Choi 120T2) in the first region (Choi R1, annotated fig 1/2B) of the device isolation layer (Choi 112, 122-2 as modified to include Kim AG, 109, and as further modified by Yamashita) and a bottom surface (Choi TP2B, annotated fig 1/2B) of the gate trench (Choi 120T2) in the second region (Choi R2, annotated fig 1/2B) of the device isolation layer (Choi 112, 122-2 as modified to include Kim AG, 109, and as further modified by Yamashita).
Choi in view of Kim, Park, and Yamashita does not teach: wherein a bottom surface of the gate trench in the first region of the device isolation layer is positioned at a lower level than a bottom surface of the gate trench in the second region of the device isolation layer.
Kim-743, in the same field of endeavor of semiconductor device manufacturing, teaches: a bottom surface (Kim-743, a bottom surface of 19 as best shown by 12B, fig 4D) of a gate trench (Kim-743 18, 19, gets filled by gate electrode 21) in a first region (Kim-743, region as best shown by 12B between adjacent active regions 13, fig 4D) of a device isolation layer (Kim-743 12) is positioned at a lower level than a bottom surface (Kim-743, a bottom surface of 18 corresponding to top surface of F, fig 4D) of the gate trench (Kim-743 18, 19) in a second region (Kim-743, region as best shown by 12A, fig 4D) of the device isolation layer (Kim-743 12)(Kim-743 fig 4D).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the gate trench of Choi in view of Kim, Park, and Yamashita by reducing a depth of a bottom surface of the gate trench in the second region, as taught by Kim-743, in order to reduce a gate induced drain leakage and/or row hammering (Kim-743 ¶0038, 0059).
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al (KR 20210040708 A, English translation of description provided in a previous office action, hereafter Choi) in view of Kim et al (US 20160307999 A1, hereafter Kim), Park et al (US 20120261747 A1, hereafter Park), and Yamashita et al (US 20110309416 A1, hereafter Yamashita), as applied to claim 1, and further in view of Sim et al (US 20150380421 A1, hereafter Sim).
Regarding claim 8, Choi in view of Kim, Park, and Yamashita teaches: The semiconductor device of claim 1, wherein the device isolation layer (Choi 112, 122-2 as modified to include Kim AG, 109, and as further modified by Yamashita) of the second region (Choi R2, annotated fig 1/2B) includes a stacked structure (Choi 112, 122-2 as modified to include Kim AG, 109, 120G2, 124-2, fig 2a, at least stacked vertically with respect to the figure) including the air gap (Kim AG, 109), and an oxide layer (Choi 122-2, ¶0025, at least oxide materials, similar to Kim 106, ¶0040).
Choi in view of Kim, Park, and Yamashita does not teach: an isolation capping layer.
Kim further teaches: an isolation dielectric layer (Kim 107) capping an isolation region (Kim I2)(Kim fig 2B).
Sim, in the same field of endeavor of semiconductor device manufacturing, teaches: a stacked structure (Sim 31, 17, 45b, fig 15), including an air gap (Sim 17), an oxide layer (Sim 31, ¶0059), and an isolation capping layer (Sim 45b, at least is capping a trench providing an air gap that defines active regions ¶0008, 0102, fig 15)(Sim fig 15).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Choi in view of Kim, Park, and Yamashita to include an isolation capping layer to the stacked structure, as taught by Sim, in order to prevent conductive material from being diffused in to the air gap (Sim ¶0099).
Regarding claim 9, Choi in view of Kim, Park, Yamashita, and Sim teaches: The semiconductor device of claim 8, wherein the oxide layer (Choi 122-2) includes silicon oxide (Choi ¶0025, “silicon oxide”).
Regarding claim 10, Choi in view of Kim, Park, Yamashita, and Sim teaches: The semiconductor device of claim 8, wherein the isolation capping layer (Sim 45b, similar to Kim 107) includes silicon nitride (Kim ¶0040, “silicon nitride”, similar to Kim 22, ¶0075).
Further, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to choose any number of suitable materials, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice (MPEP 2144.07).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al (KR 20210040708 A, English translation of description provided in a previous office action, hereafter Choi) in view of view of Kim et al (US 20140353743 A1, hereafter Kim-743), Kim et al (US 20160307999 A1, hereafter Kim), Park et al (US 20120261747 A1, hereafter Park), and Yamashita et al (US 20110309416 A1, hereafter Yamashita).
Regarding claim 11, Choi teaches: A semiconductor device (Choi ¶0016, fig 1, 2B) comprising:
a substrate (Choi 110) including a device isolation layer (Choi 112, 122-2) and an active region (Choi AC) defined by the device isolation layer (Choi ¶0017),
a gate trench (120T2) formed both in the active region and the device isolation layer (Choi annotated fig 1/2B above); and
a buried gate structure (Choi 120G2, 124-2, at least buried below 142, annotated fig 2b) formed in the gate trench (Choi 120T2)(Choi annotated fig 2b, 2a),
wherein the device isolation layer includes:
a first region (Choi R1, annotated fig 1/2B above) having a first width (Choi a width shown by R1 in the x direction, annotated fig 1/2B above) and a first thickness (Choi a thickness shown by R1 in the z direction, annotated fig 2B above); and
a second region having a second width (Choi a width shown by R2 in the x direction, annotated fig 1/2B above) greater than the first width (Choi R2 > R1, annotated fig 1/2B) and a second thickness (Choi a thickness shown by R2 in the z direction, annotated fig 2B above).
Choi does not teach: a hydrogen containing layer disposed between the substrate and an air gap, the second thickness greater than the first thickness, wherein the second region of the device isolation layer includes the air gap disposed at a lower level than the buried gate structure, wherein the air gap includes hydrogen.
Kim-743, in the same field of endeavor of semiconductor device manufacturing, teaches:
a substrate (Kim-743 11) including a device isolation region (Kim-743 12) and an active region (Kim-743 13) defined by the device isolation region (Kim-743 ¶0042), a device isolation region includes:
a first region (Kim-743 12B) having a first width and a first thickness; and a second region (Kim-743 12A) having a second width greater than the first width and a second thickness greater than the first thickness (Kim-743 ¶0042, fig 4A, “12A having the wide line width may be formed deeper than a second element isolation region 12B having the narrow line width due”, therefore 12A has a width and thickness greater than a width and thickness of 12B).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device isolation layer of Choi, such that the second region has a thickness greater than the first thickness, as taught by Kim-743, in order to eliminate a need to compensate for a loading effect caused by dissimilar region widths during trench formation (Kim-743 ¶0042).
Choi in view of Kim-743 does not teach: a hydrogen containing layer disposed between the substrate and an air gap, wherein the second region of the device isolation layer includes the air gap disposed at a lower level than the buried gate structure, wherein the air gap includes hydrogen.
Kim, in the same field of endeavor of semiconductor device manufacturing, teaches: a substrate (Choi 110) including a device isolation region (Kim I1, I2, fig 1, ¶0033) and an active region (Kim ACT, 102I) defined by the device isolation region (Kim ¶0033, 0040, “active region ACT may be defined by the first and second device isolation regions I1 and I2”),
a gate trench (Kim 113), and a buried gate structure (Kim G1, G2, ¶0046, “the first and second gate electrodes G1 and G2 may be buried gate electrodes”) formed in the gate trench (Kim fig 2B, ¶0046),
wherein the device isolation region includes a second region (Kim I2), and the second region of the device isolation region includes an air gap (Kim AG, 109, ¶0033) disposed at a lower level than the buried gate structure (Kim fig 2B).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the second region of the device isolation layer of Choi in view of Kim-743 to include an air gap within the second region of the device isolation layer, and at a lower level than the buried gate structure, as taught by Kim, in order to reduce parasitic capacitance between neighboring active regions and/or buried bit lines of the device, thus improving performance (Kim ¶0005, 0035, 0055, 0197).
Choi in view of Kim-743 and Kim does not explicitly teach: a hydrogen containing layer disposed between the substrate and an air gap, wherein the air gap includes hydrogen.
Kim further teaches: a liner layer (Kim 20A, ¶0073, “silicon oxide”) disposed between the substrate (Kim 100) and the air gap (Kim AG)(Kim fig 4F, ¶0073, the applicants “hydrogen containing layer” corresponds to liner oxide layer 104, a silicon oxide layer (spec ¶0039) that is transformed into a “hydrogen containing layer” through processing (spec ¶0041). Similarly, Kim 20A is the same material in the same structural position. See MPEP 2112.01, 2113).
Park, in the same field of endeavor of semiconductor device manufacturing, teaches: an silicon oxide layer containing hydrogen (Park 150, ¶0044, 0069, 0071, “containing hydroxide ions (OH-) or hydrogen ions (H+)”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the liner layer Choi in view of Kim-743 and Kim to contain hydrogen, as taught by Park, such that “a hydrogen containing layer [is] disposed between the substrate and an air gap”, in order to passivate dangling bonds while providing a shorter hydrogen diffusion path (Park ¶0057), thereby reducing interface trap density and improving refresh characteristics (Park ¶0047, 0053).
Choi in view of Kim-743, Kim, and Park does not explicitly teach: wherein the air gap includes hydrogen.
Yamashita, in the same field of endeavor of semiconductor device manufacturing, and in at least one embodiment, teaches: an air gap (Yamashita 55) includes hydrogen (Yamashita ¶0062).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the air gap of Choi in view of Kim-743, Kim, and Park to be filled with hydrogen, and such that “the air gap includes hydrogen”, in order to reduce the dielectric constant of the air gap (Yamashita ¶0062), thereby reducing a capacitive effect (Yamashita ¶0062) between neighboring active regions and/or buried bit lines of the device, thus improving performance (Kim ¶0005, 0035, 0055, 0197).
Response to Arguments
Applicant's arguments filed 03/02/2026 have been fully considered but they are not persuasive.
Regarding claims 1-11 and 25, the applicant argues at pages 12-22:
Any combination of all cited references fails to disclose, teach and even teach "an air gap including hydrogen and a hydrogen containing layer disposed between the air gap and the substrate" of the claimed invention.”
Examiners response:
The Examiner respectfully disagrees. As set forth in the above rejection, Kim teaches a liner layer comprising silicon oxide disposed between a substrate and an air gap, and Park further teaches a process in which a silicon oxide layer is made to contain hydrogen for passivating dangling bonds at a substrate/insulating layer interface, and that a shorter diffusion path improves the effectiveness (Park ¶0044-0048, 0069-0071). Modifying the silicon oxide liner of Kim to contain hydrogen, as taught by Park, results in the claimed limitation.
Furthermore, in response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
The applicant further argues at page 15:
The presence of hydrogen within the specific lattice structure of the hydrogen containing layer(104) represents a compositional difference compared to the prior art.
Examiners response:
The Examiner respectfully disagrees. The applicant concedes that Kim teaches “A second liner layer(20) is formed between the air gap (109, 21) and the substrate (101), and include silicon oxide” (page 20), and that “the liner oxide layer(104) is transformed into the hydrogen containing layer(104)” through processing (page 14); therefore the distinction between the claimed hydrogen containing layer and Kim’s silicon oxide liner is the processing applied to applicants layer. The process of forming a product is not germane to the patentability of the product itself; see MPEP 2113. The claim recites a structural element (a hydrogen containing layer”), not a process; how the hydrogen was incorporated does not distinguish the claimed structure from the prior art structure.
The applicant further argues at page 15:
“The presence of hydrogen within the specific lattice structure of the hydrogen containing layer (104) represents a compositional difference compared to the prior art … The claimed device is characterized by a specific concentration gradient and localization of hydrogen within the deeper second region (R2) … Applicant's invention is not merely the presence of an air-gap (108), but its strategic placement in the deeper second region (R2) to serve as a persistent "hydrogen pocket" that interacts with the hydrogen containing layer (104).”
Examiners response:
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e. “specific lattice structure”, “specific concentration gradient”, “localization of hydrogen”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
The applicant further argues at pages 15-16:
“Such localized hydrogen enrichment provides a clear physical distinction that results in superior device performance (i.e., improved retention time) … This configuration significantly shortens the diffusion path of hydrogen, leading to an unexpected improvement in refresh characteristics (Pause characteristics) that is neither taught nor suggested by the cited references.”
Examiners response:
The Examiner respectfully disagrees. Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references. The claims broadly recite “a hydrogen containing layer” without specifying any particular concentration, structure, retention time, refresh characteristic, or any other parameter that could support the general allegation that distinguishes them from the references.
Furthermore, Park teaches a shortened diffusion path improving improves effectiveness of diffusion of hydrogen atom with respect to the target interface (Park ¶0057), and that curing of defects such as dangling bonds improves refresh time (Park ¶0047, 0053). Predictable results flowing from a known prior art combination are not unexpected; See MPEP 2143.
The applicant further argues at page 15:
“Yamashita discloses an air-gap(55) with hydrogen, it does so to reduce interference and row Hammer between adjacent cells, not to enhance cell interface passivation through a liner medium.”
Examiners response:
Yamashita is relied upon for the structural teaching that hydrogen may be present in an air gap (Yamashita ¶0062). The fact that the inventor has recognized another advantage which would flow naturally from following the suggestion of the prior art cannot be the basis for patentability when the differences would otherwise be obvious. See Ex parte Obiaya, 227 USPQ 58, 60 (Bd. Pat. App. & Inter. 1985).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS B. MICHAUD whose telephone number is (703)756-1796. The examiner can normally be reached Monday-Friday, 0800-1700 Eastern Time.
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/NICHOLAS B. MICHAUD/
EXAMINER
Art Unit 2818
/Mounir S Amer/Primary Examiner, Art Unit 2818
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