DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I, with claims 1-16 indicated by Applicant to read thereon, in the reply filed on 4/20/2026 is acknowledged.
While Examiner acknowledges that Applicant indicated that claims 11-16 read on the elected Species I, claims 11-16 are drawn to non-elected species II and are hereby withdrawn from further consideration therefor.
Claims 11-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention/species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 4/20/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Re claim 1, the phrase “processing a plurality of semiconductor wafers in a fabrication flow having a sequence of process steps including a targeted process step, wherein the targeted process step adds to or subtracts from a material layer over the semiconductor wafers” is unclear and indefinite (what is the process? i.e., Etching, annealing etc.? what are they? i.e., the sequence of the process steps? And/or what is the targeted process step and/or how? i.e., does it mean depositing/forming or etching/removing a material layer over the semiconductor wafers? etc).
Re claim 1, the phrase “performing an inspection of a first sampled fraction of the plurality of semiconductor wafers for a quality characteristic of the material layer, the first sampled fraction having a first sampling size based on a first sampling rate determined responsive to a continuous sampling scheme that satisfies a first quality level of the quality characteristic, the first quality level defined based on a variable quality level corresponding to the targeted process step” is unclear and indefinite (i.e., how? Since the material layer is no longer there because the inspection step is performed after the step of subtracting a material layer from the wafer; what is the first quality level? What is the variable quality level and/or targeted process step).
Re claim 1, the phrase “on the condition that the inspection identifies one or more defective wafers in the first sampled fraction that do not meet a quality threshold of the quality characteristic, determining a second sampling rate for sampling a subsequent plurality of semiconductor wafers” is unclear and indefinite (the phrase “the condition” lacks antecedent basis. And/or what is the quality threshold?).
Re claim 1, the phrase “adjusting one or more processing conditions of the targeted process step in response to detecting the one or more defective wafers” is unclear and indefinite (i.e., what is the processing condition and/or it’s upper limit?).
Re claim 1, the phrase “processing a semiconductor substrate containing the IC at a partially completed manufacturing stage using the targeted process step after the adjusting” is unclear and indefinite (i.e., at least the active processing step for forming the IC is lacking and/or what is the targeted process step).
Re claim 9, the phrase “threshold rejection level” is unclear and indefinite (i.e.,what is the level?).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK CHEN whose telephone number is (571)272-1689. The examiner can normally be reached Monday to Friday, 8am to 4pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached at (571)270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACK S CHEN/Primary Examiner, Art Unit 2893
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