DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 1/9/2026 have been fully considered but they are not persuasive.
Applicant argues on pages 7-8 that “a first test key transistor located at a corner of the deep trench isolation structure and a second test key transistor located at a side of the deep trench isolation structure.” Examiner takes the position that this limitation is unsupported in the elected embodiment of fig. 6 and also not found in the specification as filed, as outlined below in the new matter rejection below. Further, examiner interpreted these limitations as shown in fig. 6, therefore Examiner has shown below in the art rejection that Jin still teaches each and every limitation of claim 1.
The rejection is being maintained and has been updated to include the amended portion of the claim.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-5, 9, 10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The specification as filed, nor the elected embodiment of fig. 6, is silent as to providing support for the claim limitation of “a first test key transistor located at a corner of the deep trench isolation structure and a second test key transistor located at a side of the deep trench isolation structure” recited at the 6th from last line of claim 1. Test key transistor as shown in fig. 6 shows the source and drain of the transistor straddling the location of a side of the DTI. There does not exist a two different test key transistors but rather a test key transistor that has segments of it in different locations of the DTI structure.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jin et al. (US PGPub 2019/0296070; hereinafter “Jin”).
Re claim 1: Jin teaches (e.g. figs. 12 and 14) a semiconductor device, comprising: a test key transistor (collection of elements 110, 100, 130; hereinafter “TKT”) comprising a source (left doping well 110; e.g. paragraph 92; hereinafter “S”), a drain (right doping well 110; e.g. paragraph 92; hereinafter “D”), a channel (substrate 100; e.g. paragraph 90) connected to the source (S) and the drain (D), and a gate (photogates 130; e.g. paragraph 91); and a deep trench isolation structure (180, 190 as shown in fig. 12; hereinafter “DS”) having deep trench isolation (DTI 190; e.g. paragraph 133) therein, wherein the deep trench isolation structure (DS) has horizontal (horizontal parts of 190 as shown in fig. 12; hereinafter “HL”) and vertical lines (vertical parts of 190 as shown in fig. 12; hereinafter “VL”), the intersections of the horizontal (HL) and vertical (VL) lines are corners (corners of HL and VL intersections; hereinafter “C”) and sections between the corners are sides (sections between adjacent C; hereinafter “S”), wherein: the test key transistor (TKT) has deep trench isolation (190) encroaching into the channel (100) of the test key transistor (TKT), the test key transistor (TKT) is associated with a specification including a preset gate voltage, a preset source-drain voltage difference, and a predetermined current (these associations do not impart a structure of the device, therefore they are not given patentable weight; see MPEP 2112.01(i) and 2114(i) & (ii)), and the test key transistor (TKT) is configured to (claims reciting how a device is configured to operate in a certain way does not impart a structure of the device, therefore they are not given patentable weight; see MPEP 2112.01(i) and 2114(i) & (ii)) generate a current within a threshold difference from the predetermined current in the channel in response to receiving the preset gate voltage at the gate (130) and the preset source-drain voltage difference at the source (S) and the drain (D), and the deep trench isolation (190) encroaches into the channel (100) at a preset depth (d1), wherein the test key transistor (TKT) comprises a first test key transistor (similar to what is shown in fig. 6 of instant application, left half of TKT as shown in fig. 14; hereinafter “TKT1”) located at (just like the structure of fig. 6 of the instant application shows a first transistor at a corner, fig. 12, 14 show the first transistor TKT1 at a corner C) a corner (C) of the deep trench isolation structure (DS) and a second test key transistor (similar to what is shown in fig. 6 of instant application, right half of TKT as shown in fig. 14; hereinafter “TKT2”) located at a side (just like the structure of fig. 6 of the instant application shows a second transistor at a side, fig. 12, 14 show the second transistor TKT2 at a side S) of the deep trench isolation structure (DS), the first test key transistor (TKT1) has deep trench isolation (left 190 with height d2) encroaching into the channel of the first test key transistor (TKT1) at a first preset depth, the second test key transistor (TKT2) has deep trench isolation (middle 190 with height d1) encroaching into the channel of the second test key transistor (TKT2) at a second preset depth, and the first preset depth is different (d1 and d2 are different heights) from the second preset depth.
Re claim 2: Jin teaches the semiconductor device according to claim 1, wherein the test key transistor (TKT) is configured to generate, in the channel (100), a current more than a threshold difference from the predetermined current in response to the deep trench isolation encroaching into the channel (100) at a depth that is smaller than the preset depth (claims reciting how a device is configured to operate in a certain way does not impart a structure of the device, therefore they are not given patentable weight; see MPEP 2112.01(i) and 2114(i) & (ii)).
Re claim 3: Jin teaches the semiconductor device according to claim 2, wherein the semiconductor device (device of TKT) is configured to be determined as defective in response to the test key transistor (TKT) generating the current more than the threshold difference from the predetermined current (claims reciting how a device is configured to operate in a certain way does not impart a structure of the device, therefore they are not given patentable weight; see MPEP 2112.01(i) and 2114(i) & (ii)).
Re claim 4: Jin teaches the semiconductor device according to claim 1, wherein the predetermined current is equal to 0A, and the threshold difference is in a range between 1nA and 1µA (claims reciting an arbitrarily chosen value and how to determine when a value is out of spec does not impart a structure of the device, therefore they are not given patentable weight; see MPEP 2112.01(i) and 2114(i) & (ii)).
Re claim 5: Jin teaches the semiconductor device according to claim 1, wherein: the test key transistor (TKT) further comprises an insulation layer (depletion region is formed by a gate voltage; e.g. paragraph 57; therefore a gate dielectric is implied as being present otherwise a depletion region could not be formed) below the gate (190), and the insulation layer is configured to reduce a cross-sectional area of the channel (100).
Re claim 9: Jin teaches the semiconductor device according to claim 1, wherein: the semiconductor device is a complementary metal-oxide semiconductor image sensor (element in pixel P1), the channel (100) comprises photodiode (photoelectric device PD 120; e.g. paragraph 89), and the deep trench isolation (190) is configured to provide isolation between pixels (P1) of the complementary metal-oxide semiconductor image sensor.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jin as applied to claim 1 above, and further in view of Hynecek et al. (US PGPub 2012/0273653; hereinafter “Hynecek”).
Re claim 10: Jin teaches substantially the entire device as claimed in claim 1 except explicitly teaching the semiconductor device, wherein the test key transistor (TKT) is a p-type junction-gate field transistor or an n-type junction-gate field transistor.
Hynecek teaches (e.g. fig. 2) the test key transistor (TKT) is a p-type junction-gate field transistor or an n-type junction-gate field transistor (junction gate photodiode 200; e.g. paragraph 17).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the junction gate of Hynecek in the device of Jin in order to have the predictable result of using an alternative imaging sensor pixel which allows for the elimination of the need for transfer gates (see paragraph 2 of Hynecek).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898