DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 27, 2026 has been entered.
Response to Arguments
RE: Claims 1 and 11, Applicant argues as agreed upon in the interview of December 17, 2025, Kawasaki fails to teach the features of claims 1 and 11.
However, in that interview the Examiner agreed the limitation “contact plug extending … into the source structure” as presented in proposed claim 1 for that interview is not disclosed by Kawasaki but further search and consideration would be necessary to determine patentability. The above limitation is absent in pending claim 1, but is found in claim 30. Additionally, upon further consideration and under a broad reasonable interpretation, the word “into” is herein interpreted to mean “toward” or “in the direction of” based on dictionary definitions as discussed further below. Accordingly, Kawasaki discloses the features of claim 30. A first rejection of claim 30 is based on Kawasaki and alternatively in view of Kawasaki and Choi, and a parallel rejection of claim 30 is based on Choi and Wu. A first rejection of claims 1, 11 is still based on Kawasaki, and a parallel rejection of claims 1, 11 is based on Choi and Wu.
Applicant argues referring to FIG. 48 of Kawasaki, the outer dielectric fill material portion 673 does not surround the outmost sidewall of the conductive plug 178.
However, Kawasaki (see Annotated FIG. 48 below) does disclose a stressor surrounding an outermost sidewall of the contact plug since in Kawasaki FIG. 48 stressor 673 (white region in Annotated FIG. 48 below) surrounds a bottom portion of the outermost sidewall of the contact plug 178 formed by 178A.
PNG
media_image1.png
789
710
media_image1.png
Greyscale
Annotated FIG. 48 in Kawasaki
(color/grayscale modified to better emphasize the different layers)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7, 9-13 are rejected under 35 U.S.C. 103 as being unpatentable over US20200312765A1 to Kawasaki et al. (hereinafter “Kawasaki”).
RE: Claim 1, Kawasaki discloses A semiconductor device (structure in FIG. 48 including 186, [0327]) comprising:
a source structure (110, [0301]);
a gate structure (132, 146, 232, 246) located over the source structure (110, [0301]), the gate structure comprising conductive layers (146, 246; The control gate electrodes within each electrically conductive layer (146, 246) are the control gate electrodes for a vertical memory device including the memory stack structure 55, [0313]) and insulating layers (132, 232, [0306]) that are alternately stacked on each other;
a contact plug (178 which is the combination of 178A and 178B, [0318], [0325], [0327]) extending through the gate structure, the contact plug electrically connected to the source structure (FIG. 48 shows 178 extending through some layers 232, 246; FIG. 48 shows contact plug in direct contact with 182; conductive liner 182 continuously extends from the source-level material layers 110 to a top surface of the first contact level dielectric layer 280, [0318]; Accordingly, contact plug 178 is electrically connected to source structure 110 through conductive liner 182);
a stressor (673, inner segments of the semiconductor fill material portions 373 can be converted into dielectric semiconductor oxide material portions, which are herein referred to as outer dielectric fill material portions 673, [0333]; The non-metallic material of the composite non-metallic core (176, 276, 376, 476, or 576) reduces mechanical stress, [0382]; the composite non-metallic core 376 comprises at least one semiconductor fill material portion 373 including a semiconductor fill material, wherein the at least one outer dielectric fill material portion 673 comprises an oxide of the semiconductor fill material, [0379]) surrounding an outermost sidewall of the contact plug (FIG. 48 shows stressor 673 surrounding a bottom portion of the outermost sidewall of contact plug 178 formed by 178A); and
a seed layer (373, [0332]) surrounding the stressor.
Kawasaki does not explicitly disclose that 673 comprises compressive stress.
However, paragraph [0027] of the instant application states The stressor 25 may be formed by oxidizing the seed layer 24, and expand in volume during the oxidation process. The compressive stress of the stressor 25 may be induced by the expansion in volume during a formation process thereof. The seed layer 24 may include a material having a volume that expands upon oxidation. In an embodiment, the seed layer 24 may include silicon, and the stressor 25 may include silicon oxide.
Further, in Kawasaki, as 673 is silicon oxide formed by converting an inner portion of 373 to silicon oxide, 373 would inherently expand in volume when partially oxidized and therefore 673 would apply compressive stress on the sidewalls of 182 and 373.
Below is an annotated version of FIG. 48 from Kawasaki, which was color/grayscale modified to better emphasize the different layers in the plug structure. The color/grayscale modification was based on the original color drawings filed in U.S. Patent Application No. 16/516,726. Kawasaki was published from U.S. Patent Application No. 16/516,726.
PNG
media_image2.png
907
584
media_image2.png
Greyscale
Annotated FIG. 48 in Kawasaki
(color/grayscale modified to better emphasize the different layers)
RE: Claim 2, Kawasaki discloses The semiconductor device of claim 1, wherein the seed layer includes a material, the material comprising a volume that expands upon oxidation (As discussed above, 373 would inherently expand in volume upon oxidation).
RE: Claim 3, Kawasaki discloses The semiconductor device of claim 1, wherein the seed layer includes silicon, and wherein the stressor includes silicon oxide (Each outer dielectric fill material portion 673 can include, and may consist essentially of, a dielectric oxide of the semiconductor material of the semiconductor fill material portions 373. For example, if the semiconductor fill material portions include amorphous silicon or polysilicon, the outer dielectric fill material portions 673 can include thermal silicon oxide, [0333]; Accordingly, it would have been obvious to try selecting silicon or polysilicon for the semiconductor fill portion 373 and selecting silicon oxide for the material in 673 as these are identified solutions for the materials in 373, 673 provided by Kawasaki and these would have had a reasonable expectation of success, see MPEP 2143).
RE: Claim 4, Kawasaki discloses The semiconductor device of claim 1, wherein the seed layer includes polysilicon, silicon nitride, silicon oxynitride or combinations thereof (Each outer dielectric fill material portion 673 can include, and may consist essentially of, a dielectric oxide of the semiconductor material of the semiconductor fill material portions 373. For example, if the semiconductor fill material portions include amorphous silicon or polysilicon, the outer dielectric fill material portions 673 can include thermal silicon oxide, [0333]; Accordingly, it would have been obvious to try selecting polysilicon for the semiconductor fill portion 373 as this is one solution for the material in 373 identified by Kawasaki and this would have had a reasonable expectation of success, see MPEP 2143).
RE: Claim 5, Kawasaki discloses The semiconductor device of claim 1, wherein the seed layer surrounds a sidewall of the stressor (FIG. 48 shows 373 surrounding a sidewall of 673).
RE: Claim 6, Kawasaki discloses The semiconductor device of claim 1, wherein the seed layer surrounds a sidewall of the stressor and is disposed between the contact plug and the source structure (FIG. 48 shows 373 surrounding sidewall of 673 and is disposed between 178 and 110).
RE: Claim 7, Kawasaki discloses The semiconductor device of claim 1, further comprising an insulating spacer (172, [0319]) surrounding the seed layer.
RE: Claim 9, Kawasaki discloses The semiconductor device of claim 1, wherein the seed layer is interposed between the contact plug and the source structure (FIG. 48 shows 373 interposed between 178 and 110), and the contact plug is electrically connected to the source structure through the seed layer (The conformal semiconductor fill material layer includes a doped semiconductor material, [0331]; Remaining portions of the conformal semiconductor fill material layer in the backside trenches 79 constitute the semiconductor fill material portion 373, [0331]; Accordingly, 178 is electrically connected to 110 through the doped 373).
RE: Claim 10, Kawasaki does not explicitly disclose The semiconductor device of claim 1, wherein tensile stress of the semiconductor device is offset by the compressive stress of the stressor.
However, Kawasaki discloses The non-metallic material of the composite non-metallic core (176, 276, 376, 476, or 576) reduces mechanical stress in the backside trenches 79, [0382].
Kawasaki further discloses the composite non-metallic core (176, 276, 376, 476, or 576) can reduce the stress and the resultant substrate warping, [0382].
Accordingly, since 673 is nonmetallic, 673 in part reduces the stress in the trenches 79. Further, as discussed above for claim 1, 373 inherently expands in volume when oxidized and therefore 673 applies compressive stress on the sidewalls of 182 and 373 while also reducing the stress in the trench. It is considered inherent that the sidewalls of the trench would include tensile stress since when the trench is formed, material around the trench would be pushed inward into the trench, pulling on the layers 146, 246, creating tensile stress therein. When tensile stress in the sidewalls of the trench is counteracted by compressive stress applied by 673 pushing outward, the overall stress would be reduced as taught by Kawasaki.
RE: Claim 11, Kawasaki discloses A semiconductor device (structure in FIG. 48 including 186, [0327]) comprising:
a gate structure (132, 146, 232, 246) including conductive layers (146, 246; The control gate electrodes within each electrically conductive layer (146, 246) are the control gate electrodes for a vertical memory device including the memory stack structure 55, [0313]) and insulating layers (132, 232, [0306]) that are alternately stacked on each other;
a contact plug (178 which is the combination of 178A and 178B, [0318], [0325], [0327]) extending through the gate structure (FIG. 48 shows 178 extending through some layers 232, 246);
a stressor (673, inner segments of the semiconductor fill material portions 373 can be converted into dielectric semiconductor oxide material portions, which are herein referred to as outer dielectric fill material portions 673, [0333]; The non-metallic material of the composite non-metallic core (176, 276, 376, 476, or 576) reduces mechanical stress, [0382]; the composite non-metallic core 376 comprises at least one semiconductor fill material portion 373 including a semiconductor fill material, wherein the at least one outer dielectric fill material portion 673 comprises an oxide of the semiconductor fill material, [0379]) surrounding an outermost sidewall of the contact plug (FIG. 48 shows stressor 673 surrounding a bottom portion of the outermost sidewall of contact plug 178 formed by 178A); and
a seed layer (373, [0332]) surrounding the stressor.
Kawasaki does not explicitly disclose that 673 comprises compressive stress.
However, paragraph [0027] of the instant application states The stressor 25 may be formed by oxidizing the seed layer 24, and expand in volume during the oxidation process. The compressive stress of the stressor 25 may be induced by the expansion in volume during a formation process thereof. The seed layer 24 may include a material having a volume that expands upon oxidation. In an embodiment, the seed layer 24 may include silicon, and the stressor 25 may include silicon oxide.
Further, in Kawasaki, as 673 is silicon oxide formed by converting an inner portion of 373 to silicon oxide, 373 would inherently expand in volume when partially oxidized and therefore 673 would apply compressive stress on the sidewalls of 182 and 373.
Kawasaki does not explicitly disclose that the gate structure comprises tensile stress.
However, Kawasaki discloses that stress is generated by the electrically conductive layers (146, 246) in the alternating stacks (132, 146, 232, 246), [0382].
Kawasaki discloses The non-metallic material of the composite non-metallic core (176, 276, 376, 476, or 576) reduces mechanical stress in the backside trenches 79, [0382]. FIGs. 44-45 show a trench formed in 132, 146, 232, 246.
Kawasaki further discloses the composite non-metallic core (176, 276, 376, 476, or 576) can reduce the stress and the resultant substrate warping, [0382].
Accordingly, since 673 is nonmetallic, 673 in part reduces the stress in the trench. Further, as discussed above, 373 inherently expands in volume when oxidized and therefore 673 applies compressive stress on the sidewalls of 182 and 373 while also reducing the stress in the trench. It is considered inherent that 146, 246 would include tensile stress since when the trench is formed therein, material around the trench would be pushed inward into the trench, pulling on the layers 146, 246. When tensile stress in 146, 246 is counteracted by compressive stress applied by 673 pushing outward, the overall stress would be reduced as taught by Kawasaki.
Below is an annotated version of FIG. 48 from Kawasaki, which was color/grayscale modified to better emphasize the different layers in the plug structure. The color/grayscale modification was based on the original color drawings filed in U.S. Patent Application No. 16/516,726. Kawasaki was published from U.S. Patent Application No. 16/516,726.
PNG
media_image2.png
907
584
media_image2.png
Greyscale
Annotated FIG. 48 in Kawasaki
(color/grayscale modified to better emphasize the different layers)
RE: Claim 12, Kawasaki discloses The semiconductor device of claim 11, wherein the seed layer includes a material, the material comprising a volume that expands upon oxidation (As discussed above, 373 would inherently expand in volume upon oxidation).
RE: Claim 13, Kawasaki discloses The semiconductor device of claim 11, wherein the seed layer includes silicon, and wherein the stressor includes silicon oxide (Each outer dielectric fill material portion 673 can include, and may consist essentially of, a dielectric oxide of the semiconductor material of the semiconductor fill material portions 373. For example, if the semiconductor fill material portions include amorphous silicon or polysilicon, the outer dielectric fill material portions 673 can include thermal silicon oxide, [0333]; Accordingly, it would have been obvious to try selecting silicon for the semiconductor fill portion 373 and selecting silicon oxide for the material in 673 as these are identified solutions for the materials in 373, 673 provided by Kawasaki and these would have had a reasonable expectation of success, see MPEP 2143).
Claim(s) 8, 30-32 are rejected under 35 U.S.C. 103 as being unpatentable over Kawasaki as applied to claim 1 or 11, further in view of US 20220392918 A1 (“Choi”).
RE: Claim 8, Kawasaki does not explicitly disclose The semiconductor device of claim 1, wherein the contact plug is directly connected to the source structure.
However, in the same field of endeavor, Choi discloses in FIG. 12:
wherein a contact plug (common source plug CSP, [0107]) is directly connected to a source structure (CSR, [0106]; FIG. 12 shows the plug CSP directly connected to CSR).
It would have been obvious to one of ordinary skill in the art to modify the contact plug 178 to directly connect to the source structure 110 as taught by Choi in order to make a more direct connection between the contact plug 178 and the source structure 110, thereby reducing resistance between them.
Re: Claim 30, Kawasaki discloses The semiconductor device of claim 11, further comprising a source structure (110, [0301]), wherein the contact plug is electrically connected to the source structure (conductive liner 182 continuously extends from the source-level material layers 110 to a top surface of the first contact level dielectric layer 280, [0318]; Accordingly, contact plug 178 is electrically connected to source structure 110 through conductive liner 182).
Kawasaki does not explicitly disclose wherein the contact plug extends into the source structure.
However, the word “into” is not defined in the instant specification.
The word “into” has been defined as “in the direction of,” see definition 6 by Collins Dictionary at <https://www.collinsdictionary.com/us/dictionary/english/into>.
The word “into” has also been defined as “toward or in the direction of,” see definition 2 by Dictionary.com at <https://www.dictionary.com/browse/into>.
The word “into” has also been defined as “in the direction of” see definition 2 by Merriam-Webster’s Dictionary at <https://www.merriam-webster.com/dictionary/into>.
In Kawasaki FIG. 48, since the contact plug 178 extends toward or extends in the direction of the source structure 110, under a broad reasonable interpretation, the contact plug 178 extends into the source structure 110.
Alternatively, in the same field of endeavor, Choi discloses in FIG. 12:
wherein a contact plug (common source plug CSP, [0107]) extends into a source structure (common source region CSR; FIG. 12 Choi shows a portion of plug CSP inside source structure CSR).
It would have been obvious to one of ordinary skill in the art to modify the contact plug 178 to extend into the source structure 110 as taught by Choi in order to make a more direct connection between the contact plug 178 and the source structure 110, thereby reducing resistance between them.
Re: Claim 31, Kawasaki or Kawasaki in view of Choi discloses The semiconductor device of claim 30, wherein the seed layer surrounds a sidewall of the stressor and is disposed between the contact plug and the source structure (FIG. 48 Kawasaki shows 373 surrounding sidewall of 673 and is disposed between 178 and 110).
Re: Claim 32, Kawasaki or Kawasaki in view of Choi discloses The semiconductor device of claim 31, wherein the contact plug is electrically connected to the source structure through the seed layer (Kawasaki FIG. 48 shows 373 interposed between 178 and 110; Kawasaki discloses The conformal semiconductor fill material layer includes a doped semiconductor material, [0331]; Remaining portions of the conformal semiconductor fill material layer in the backside trenches 79 constitute the semiconductor fill material portion 373, [0331]; Accordingly, as modified, 178 is electrically connected to 110 through the doped 373).
Claim(s) 1, 8, 11, and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of US20200105909A1 (“Wu”).
RE: Claim 1, Choi, discloses A semiconductor device (semiconductor device in FIG. 12) comprising:
a source structure (CSR, [0106]);
a gate structure (gate electrodes EL and dielectric layers ILD, [0127]-[0128]) located over the source structure, the gate structure comprising conductive layers (gate electrodes EL) and insulating layers (dielectric layers ILD) that are alternately stacked on each other;
a contact plug (common source plug CSP, [0107]) extending through the gate structure, the contact plug electrically connected to the source structure (FIG. 12 shows the plug CSP in direct contact with CSR; Accordingly, CSP is electrically connected to CSR).
Choi does not explicitly disclose:
a stressor surrounding an outermost sidewall of the contact plug, the stressor comprising compressive stress; and
a seed layer surrounding the stressor.
However, in a similar field of endeavor, Wu discloses a FinFET device 10 (FIG. 1) including:
a contact plug (78, [0019]) extending through a gate structure (70), the contact plug electrically connected to a source structure (54, [0019]; FIG. 1 shows contact plug 78 in direct contact with source structure 54; Accordingly, contact plug 78 is electrically connected to 54);
a stressor (60a; 60 is oxidized and expands in volume, [0053]; the oxidized portion of 60 includes 60a, [0054]) surrounding an outermost sidewall of the contact plug (FIG. 1 shows 60a surrounding outermost sidewall of 78), the stressor comprising compressive stress (As a result, compressive stresses, as indicated by arrows 66, are introduced to the channel regions, [0054]); and
a seed layer (lower portions of 60b that remain, [0066]) surrounding the stressor (instead of removing the entirety of the dummy spacers 60 b, upper portions of the dummy spacers 60 b are removed. As a result, an air gap exists at an upper portion of a space between the respective protection layer 62 and the BCESL 58 (or the spacer 52). For example, portions of the dummy spacers 60 b above a height higher or lower than the top of the fin 42 are removed. As a result, lower portions of the dummy spacers 60 b below the height remain, and air gaps between the later-formed source/drain contacts and the replacement gates are obtained, [0066]; FIG. 10A shows lowermost portions of 60b surrounding a portion of 60a; Accordingly, lower portions of 60b that remain below a height would surround 60a).
Wu further discloses air gaps are implemented for reducing parasitic capacitance between contacts and the gate structure, and stress liners are implemented for enhancing carrier mobility in the channel, [0077].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to introduce a stressor surrounding the source plug CSP and a seed layer surrounding the stressor as taught by Wu in order to reduce parasitic capacitance between the source plug CSP and the gate electrodes EL.
RE: Claim 8, Choi in view of Wu discloses The semiconductor device of claim 1, wherein the contact plug is directly connected to the source structure (Choi FIG. 12 shows the source plug CSP is directly connected to source structure CSR; Wu FIG. 1 shows the contact plug 78 directly connected to source 54 structure).
RE: Claim 11, Choi discloses A semiconductor device comprising:
a gate structure (gate electrodes EL and dielectric layers ILD, [0127]-[0128]) including conductive layers (gate electrodes EL) and insulating layers (dielectric layers ILD) that are alternately stacked on each other;
a contact plug (common source plug CSP, [0107]) extending through the gate structure.
Choi does not explicitly disclose:
the gate structure comprising tensile stress;
a stressor surrounding an outermost sidewall of the contact plug, the stressor comprising compressive stress; and
a seed layer surrounding the stressor.
However, Choi FIG. 18 shows trenches TR in which common source plugs CSP are formed, [0131].
Accordingly, the gate electrodes EL and dielectric layers ILD would include tensile stress since when the trench TR is formed, material of the electrodes EL and dielectric layers ILD around the trench would be pushed inward into the trench, pulling on the layers EL, ILD.
In a similar field of endeavor, Wu discloses a FinFET device 10 (FIG. 1) including:
a contact plug (78, [0019]) extending through a gate structure (70);
a stressor (60a; 60 is oxidized and expands in volume, [0053]; the oxidized portion of 60 includes 60a, [0054]) surrounding an outermost sidewall of the contact plug (FIG. 1 shows 60a surrounding outermost sidewall of 78), the stressor comprising compressive stress (As a result, compressive stresses, as indicated by arrows 66, are introduced to the channel regions, [0054]); and
a seed layer (lower portions of 60b that remain, [0066]) surrounding the stressor (instead of removing the entirety of the dummy spacers 60 b, upper portions of the dummy spacers 60 b are removed. As a result, an air gap exists at an upper portion of a space between the respective protection layer 62 and the BCESL 58 (or the spacer 52). For example, portions of the dummy spacers 60 b above a height higher or lower than the top of the fin 42 are removed. As a result, lower portions of the dummy spacers 60 b below the height remain, and air gaps between the later-formed source/drain contacts and the replacement gates are obtained, [0066]; FIG. 10A shows lowermost portions of 60b surrounding a portion of 60a; Accordingly, lower portions of 60b that remain below a height would surround 60a).
Wu further discloses air gaps are implemented for reducing parasitic capacitance between contacts and the gate structure, and stress liners are implemented for enhancing carrier mobility in the channel, [0077].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to introduce a stressor surrounding the source plug CSP and a seed layer surrounding the stressor as taught by Wu in order to reduce parasitic capacitance between the source plug CSP and the gate electrodes EL.
RE: Claim 30, Choi in view of Wu discloses The semiconductor device of claim 11, further comprising a source structure (Choi FIG. 12: CSR, [0106]), wherein the contact plug extends into the source structure and is electrically connected to the source structure (FIG. 12 shows contact plug CSP extends into source structure CSR and in direct contact with CSR; Accordingly, CSP is electrically connected to CSR; Similarly, in Wu FIG. 1, contact plug 78 extends into source structure 54 and in direct contact with 54; Accordingly in Wu, 78 is electrically connected to 54).
Claims 31-32 are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Wu as applied to claim 30, further in view of Kawasaki.
RE: Claim 31, Choi in view of Wu discloses The semiconductor device of claim 30, wherein the seed layer surrounds a sidewall of the stressor (Wu discloses instead of removing the entirety of the dummy spacers 60 b, upper portions of the dummy spacers 60 b are removed. As a result, an air gap exists at an upper portion of a space between the respective protection layer 62 and the BCESL 58 (or the spacer 52). For example, portions of the dummy spacers 60 b above a height higher or lower than the top of the fin 42 are removed. As a result, lower portions of the dummy spacers 60 b below the height remain, and air gaps between the later-formed source/drain contacts and the replacement gates are obtained, [0066]; FIG. 10A shows lowermost portions of 60b surrounding a sidewall of 60a; Accordingly, lower portions of 60b that remain below a height would surround a sidewall of 60a).
Choi in view of Wu does not explicitly disclose:
wherein the seed layer is disposed between the contact plug and the source structure.
However, in the same field of endeavor, Kawasaki discloses in FIG. 48 (see also Annotated FIG. 48 below):
wherein a seed layer (373, [0332]) surrounds a sidewall of a stressor (673) and is disposed between a contact plug (178 which is the combination of 178A and 178B, [0318], [0325], [0327]) and a source structure (110, [0301]).
Kawasaki further discloses inner segments of the semiconductor fill material portions 373 can be converted into dielectric semiconductor oxide material portions, which are herein referred to as outer dielectric fill material portions 673, [0333]; The non-metallic material of the composite non-metallic core (176, 276, 376, 476, or 576) reduces mechanical stress, [0382]; the composite non-metallic core 376 comprises at least one semiconductor fill material portion 373 including a semiconductor fill material, wherein the at least one outer dielectric fill material portion 673 comprises an oxide of the semiconductor fill material, [0379].
Kawasaki further discloses The conformal semiconductor fill material layer includes a doped semiconductor material, [0331]; Remaining portions of the conformal semiconductor fill material layer in the backside trenches 79 constitute the semiconductor fill material portion 373, [0331]; Accordingly, 178 is electrically connected to source structure 110 through the doped 373; FIG. 48 shows a portion of 373 interposed between a portion of 178, 182 and 110, and so this portion of 182 is electrically connected to 110 through the portion of 373 interposed between a portion of 178, 182 and 110.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wu’s seed layer 60b to be doped and to dispose Wu’s seed layer 60b between Choi’s contact plug CSP and Choi’s source structure CSR so that Choi’s contact plug CSP is electrically connected to Choi’s source structure CSP through Wu’s seed layer 60b as taught by Kawasaki in order to increase the amount of conductive regions between the contact plug CSP and the source structure CSR, thereby increasing conductivity between the contact plug CSP and the source structure CSR and reducing resistance.
PNG
media_image2.png
907
584
media_image2.png
Greyscale
Annotated FIG. 48 in Kawasaki
(color/grayscale modified to better emphasize the different layers)
RE: Claim 32, Choi in view of Wu, Kawasaki discloses The semiconductor device of claim 31, wherein the contact plug is electrically connected to the source structure through the seed layer (As modified by Kawasaki, Choi’s contact plug CSP is electrically connected to Choi’s source structure CSP through Wu’s seed layer 60b).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached on (571) 270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL ANGUIANO/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights