DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election
Applicant’s election without traverse of Group II, claims 1-11 and 19, in the reply filed on 10/20/2025 is acknowledged.
IDS
The IDS document(s) filed on 08/29/2022 have been considered. Copies of the PTO-1449 documents are herewith enclosed with this office action.
Claim Objections
Claim 1 and 7 are objected to because of the following informalities: “through a first an interlevel dielectric level” (emphasis added”) in Line 3. Appropriate correction is required.
Claim 7 recites “the skip level via opening” in line 7”. There is insufficient antecedent basis for this limitation in the claim.
Claim 19 is objected to under 37 CFR 1.75 as being a substantial duplicate of claim 10. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim Rejections - 35 U.S.C. § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 7 recite the following limitations:
“the at least two interlevel dielectric levels” in line 2, and
“the substrate level” in lines 2-3.
There is insufficient antecedent basis for this limitation in the claim.
Claims 2-6, 8-11, and 19 are rejected based on their dependency of claims 1 and 7.
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 5-8, 10-11 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Mignot et al. (US 2020/0388567 A1), hereafter “Mignot”, and further in view of Murray et al. (US 2016/0358859 A1), hereafter “Murray”.
As to claim 1, Mignot teaches a microelectronics structure comprising:
a skip level via (132, Fig. 13 ⁋ [0045]) extending from an upper level metal line (208, ⁋ [0046]) in an upper level (see annotated Fig. 13 below) of the at least two interlevel dielectric levels through a first an interlevel dielectric level (120, Fig. 10, ⁋ [0029]) that is on the substrate level (102, ⁋ [0026]) without contacting an interlevel metal line (M1, ⁋ [0029]), the skip level via extends into electrical contact with a first element of electrical contact features (M0, ⁋ [0028]) in a lower level (see annotated Fig. 13 below) of the at least two interlevel dielectric levels; and
a single level via (V0, Fig. 10, ⁋ [0029]) extending from the interlevel metal line (M1) into electrical contact with at least a second element of the electrical contact features (M0) (⁋ [0029], “a normal height via (V0) vertically extends and electrically couples the patterned metal layers M0 and M1”), wherein a dielectric material of the spacer of the skip level via is not present on the sidewalls of the single level via (Fig. 10 shows no spacer present).
Mignot fails to teach wherein the skip level via includes a spacer that is present on sidewalls of the skip level via.
Murray, in the same field of endeavor, teaches a liner/spacer (30, Fig. 6, ⁋ [028]) present on sidewalls of a via (45, ⁋ [0038]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the liner as taught by Murray into the device of Mignot as it obstructs copper (Cu) atoms from migrating into the interlevel dielectric (ILD) layer and provides good adhesion for the subsequently deposited metal fill (⁋ [0028]).
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As to claim 2, Mignot in view of Murray teach the microelectronics structure of claim 1, Murray teaches wherein the spacer (30) extends along an entire height of the skip level via.
As to claim 3, Mignot in view of Murray teach the microelectronics structure of claim 1, Murray teaches wherein the spacer is composed of a dielectric selected from the group consisting of silicon oxide (⁋ [0028], “SiO2”), silicon nitride, silicon oxynitride, aluminum oxide and combinations thereof.
As to claim 5, Mignot in view of Murray teach the microelectronics structure of claim 1, Murray teaches wherein the spacer has a thickness ranging from 2 nm to 5 nm (⁋ [0028], “1nm to 10nm”).
As to claim 6, Mignot in view of Murray teach the microelectronics structure of claim 1, wherein the liner/spacer (Murray, 30) is positioned between an electrically conductive fill of the skip level via (Mignot, 132, ⁋ [0034], “the super via opening 130 is filled with a conductive material”) and the interlevel metal (Murray, M1) line to obstruct the skip level via from shorting to the interlevel metal line (Examiner notes the combination of Mignot in view of Murray teach the structural limitations and the functional language does not distinguish the invention from the prior art unless it results in a structural difference).
As to claim 7, Mignot teaches an electrical communication structure comprising:
a skip level via (132, Fig. 13 ⁋ [0045]) extending from an upper level metal line (208, ⁋ [0046]) in an upper level (see annotated Fig. 13 above) of the at least two interlevel dielectric levels through a first an interlevel dielectric level (120, Fig. 10, ⁋ [0029]) that is on the substrate level (102, ⁋ [0026]) without contacting an interlevel metal line (M1, ⁋ [0029]), wherein the skip level via extends into electrical contact with a first element of electrical contact features (M0, ⁋ [0028]) in a lower level (see annotated Fig. 13 above) of the at least two interlevel dielectric levels; and
a single level via (V0, Fig. 10, ⁋ [0029]) extending from the interlevel metal line (M1) into electrical contact with at least a second element of the electrical contact features (M0) (⁋ [0029], “a normal height via (V0) vertically extends and electrically couples the patterned metal layers M0 and M1”), wherein the dielectric material of the spacer for the skip level via is not present on the sidewalls of the single level via (Fig. 10 shows no spacer present).
Mignot fails to teach a spacer that is present on a lower portion of sidewalls of the skip level via opening.
Murray, in the same field of endeavor, teaches a liner/spacer (30, Fig. 6, ⁋ [028]) present on sidewalls of a via (45, ⁋ [0038]). Examiner notes 30 is formed on both lower and upper portions of 45.
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the liner as taught by Murray into the device of Mignot as it obstructs copper (Cu) atoms from migrating into the interlevel dielectric (ILD) layer and provides good adhesion for the subsequently deposited metal fill (⁋ [0028]).
As to claim 8, Mignot in view of Murray teach the microelectronics structure of claim 7, Murray teaches wherein the spacer is composed of a dielectric selected from the group consisting of silicon oxide (⁋ [0028], “SiO2”), silicon nitride, silicon oxynitride, aluminum oxide and combinations thereof.
As to claim 10, Mignot in view of Murray teach the microelectronics structure of claim 7, Murray teaches wherein the spacer has a thickness ranging from 2nm to 5nm (⁋ [0028], “1nm to 10nm”).
As to claim 11, Mignot in view of Murray teach the microelectronics structure of claim 7, wherein the liner/spacer (Murray, 30) is positioned between an electrically conductive fill of the skip level via (Mignot, 132, ⁋ [0034], “the super via opening 130 is filled with a conductive material”) and the interlevel metal (Murray, M1) line to obstruct the skip level via from shorting to the interlevel metal line (Examiner notes the combination of Mignot in view of Murray teach the structural limitations and the functional language does not distinguish the invention from the prior art unless it results in a structural difference).
As to claim 19, Mignot in view of Murray teach the microelectronics structure of claim 7, Murray teaches wherein the spacer has a thickness ranging from 2 nm to 5 nm (⁋ [0028], “1nm to 10nm”).
Claims 4 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Mignot in view of Murray, as applied to claims 1 and 7 respectively, and further in view of Yang et al. (US 10319629 B1), hereafter “Yang”.
As to claim 4, Mignot in view of Murray teach the microelectronics structure of claim 1, but fail to teach wherein the spacer is comprised of a low-k dielectric.
Yang, in the same field of endeavor, teaches a spacer (52, Fig. 5, Col. 8, Lines 35-40), in a via opening (50, Fig. 4, Col. 8, Line 11), comprised of a low-k material (Col. 8, Lines 40-41).
It would have been obvious to one having ordinary skill in the art before the effective filing date to incorporate the low-k material as taught by Yang into the device of Mignot in view of Murray, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
As to claim 9, Mignot in view of Murray teach the microelectronics structure of claim 7, but fail to teach wherein the spacer is comprised of a low-k dielectric.
Yang, in the same field of endeavor, teaches a spacer (52, Fig. 5, Col. 8, Lines 35-40), in a via opening (50, Fig. 4, Col. 8, Line 11), comprised of a low-k material (Col. 8, Lines 40-41).
It would have been obvious to one having ordinary skill in the art before the effective filing date to incorporate the low-k material as taught by Yang into the device of Mignot in view of Murray, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Conclusion
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/CARNELL HUNTER III/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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