Prosecution Insights
Last updated: April 19, 2026
Application No. 17/897,974

RECESS LEAD FOR A SURFACE MOUNT PACKAGE

Final Rejection §103§112
Filed
Aug 29, 2022
Examiner
FAN, SU JYA
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
2 (Final)
75%
Grant Probability
Favorable
3-4
OA Rounds
2y 9m
To Grant
86%
With Interview

Examiner Intelligence

Grants 75% — above average
75%
Career Allow Rate
700 granted / 929 resolved
+7.3% vs TC avg
Moderate +11% lift
Without
With
+11.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
53 currently pending
Career history
982
Total Applications
across all art units

Statute-Specific Performance

§101
3.4%
-36.6% vs TC avg
§103
47.6%
+7.6% vs TC avg
§102
24.9%
-15.1% vs TC avg
§112
19.7%
-20.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 929 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Response to Amendment The following office action is in response to the amendment and remarks filed on 10/16/25. Applicant’s amendment to claims 1, 2, 7, 8 and 15 is acknowledged. Claims 1-20 are pending and claims 6 and 13 are withdrawn. Claims 1-5, 7-12 and 14-20 are subject to examination at this time. Response to Arguments Applicant's arguments with respect to claim 1 have been considered but are moot in view of the new ground(s) of rejection. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 8-12 and 14-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In claim 8, the limitation “the lead does not extend beyond planes along the first surface and the adjacent second surface of the package” is indefinite in view of Applicant’s fig. 3. Referring to fig. 3 annotated below, the lead does extend beyond planes along the first surface and the adjacent second surface of the package. Furthermore, the lead is a 3-dimensional object so it extends in 3 directions. PNG media_image1.png 468 375 media_image1.png Greyscale Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-5, 7-12 and 14-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara et al., US Publication No. 2021/0296216 A1. Regarding claim 1: Referring to MPEP § 2141, Examination Guidelines for Determining Obviousness Under 35 U.S.C. 103: “A person of ordinary skill in the art is also a person of ordinary creativity, not an automaton.” KSR, 550 U.S., 82 USPQ2d at 1397. “[I]n many cases a person of ordinary skill will be able to fit the teachings of multiple patents together like pieces of a puzzle.” Office personnel may also take into account “the inferences and creative steps that a person of ordinary skill in the art would employ.”, 82 USPQ2d at 1396. In fig. 1, Fujiwara does not designate regions in the lead as a central segment, a first extension and a second extension. However, it would have been obvious to one of ordinary skill in the art to designate regions in the lead as a central segment, a first extension and a second extension since this is considered within the creativity of one of ordinary skill in the art. For example, in fig. 1C annotated below, one of ordinary skill in the art drawing a partition line across the lead would create regions designated as central segment, a first extension and a second extension. PNG media_image2.png 700 773 media_image2.png Greyscale PNG media_image3.png 336 602 media_image3.png Greyscale Thus, Fujiwara teaches: 1. A lead of a semiconductor package (100), comprising (see fig. 1, also see fig. 9): a central segment (e.g. center 24) having a first side (e.g. left side) and a second side (e.g. right side); a first extension (e.g. left 24) from a portion of the first side; a second extension (e.g. right 24) from a portion of the second side; and a recess (22) extending from a plane along a bottom surface of the semiconductor package (100) at a height less than a full thickness of the lead (24), the recess (22) extending through portions of the central segment, the first extension and the second extension; wherein: the recess (22) does not project beyond the plane along the bottom surface (e.g. bottom plane in fig. 1B) and a plane a side surface (e.g. right side plane in fig. 1B) along of the semiconductor package; the first extension (e.g. left 24) includes an angular edge (e.g. angular edge annotated in fig. 1C above); the first extension (e.g. left 24) intersects a junction (e.g. junction annotated in fig. 1C above) between the central segment and the recess on the first side of the central segment; and the angular edge and the junction contact a single plane (e.g. single plane annotated in fig. 1C), and the central segment extends into the package beyond the single plane (e.g. See annotation in figs. 1C showing the central segment extends into the package beyond the single plane). 2. The lead as recited in Claim 1, wherein the second extension (e.g. right 24) intersects a junction between the central segment and the recess (22) on the second side of the central segment (e.g. The second extension and junction is a mirror image of the first extension and junction of claim 1 and annotated in fig. 1C.) 3. The lead as recited in Claim 1, wherein the central segment (e.g. center 24) has a thickness greater than a thickness of the first extension (e.g. left 24) and the second extension (e.g. right 24), fig. 1C. 4. The lead as recited in Claim 1, wherein a thickness of the first extension (e.g. left 24) is substantially equal to a thickness of the second extension (e.g. right 24) (e.g. The first extension and second extension are mirror images as annotated in fig. 1C.) 5. The lead as recited in Claim 1, wherein the recess (22) comprises a concave shape, fig. 1C. 7. (Currently amended) The lead as recited in Claim 1, wherein angular edge (e.g. angular edge annotated in fig. 1C) is opposite the recess (22), fig. 1C. Regarding claim 8: Fujiwara teaches the limitations as applied to claim 1 above, and further teaches: (see fig. 1) a semiconductor die (10) attached to a die attach pad (205); and a lead (20) coupled to the semiconductor die… the lead (20) does not extend beyond planes along the first surface (e.g. bottom plane in fig. 1B) and the adjacent second surface (e.g. right side plane in fig. 1B) of the package. Regarding claim 9: Fujiwara teaches the limitations as applied to claim 2 above. Regarding claim 10: Fujiwara teaches the limitations as applied to claim 3 above. Regarding claim 11: Fujiwara teaches the limitations as applied to claim 4 above. Regarding claim 12: Fujiwara teaches the limitations as applied to claim 5 above. Regarding claim 14: Fujiwara teaches the limitations as applied to claim 7 above. Fujiwara further teaches: 15. The package as recited in Claim 8, further comprising: another lead coupled to the semiconductor die and terminating on the first surface and the second surface of the package, including: a central segment having a first side and a second side; a first extension from a portion of the first side; a second extension from a portion of the second side; and a recess extending through a portion of the central segment, the first extension and the second extension of the another lead, a portion of the another lead being exposed from a molding compound covering the semiconductor die (e.g. In fig. 1, there are a plurality of leads 20. In claim 1, the lead is the lead 20 on the right of fig. 1B. In claim 15, the another lead is the lead on the left of fig. 1B having the same designated central segment, first extension and second extension as annotate above in fig. 1C.) 16. The package as recited in Claim 15, wherein the lead is adjacent the another lead (e.g. Figs. 1A and 1C shows there are a plurality of leads 20.) 17. The package as recited in Claim 16, wherein a separation distance between the second extension (e.g. right 24) of the lead (22) and the first extension (e.g. left 24) of the another lead (e.g. adjacent 22) is sufficient to avoid electrical conduction between the lead and the another lead, figs. 1A, 1C. 18. The package as recited in Claim 8, wherein a portion of the die attach pad (205) is exposed on the first surface (e.g. bottom plane in fig. 1B) of the package. 19. The package as recited in Claim 8, wherein the lead is configured to provide an electrical connection to a printed circuit board (90 in fig. 9), para. [0073]. 20. The package as recited in Claim 8, wherein the package is a quad flat no-lead (QFN) package, para. [0077]. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini, can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Michele Fan/ Primary Examiner, Art Unit 2818 29 December 2025
Read full office action

Prosecution Timeline

Aug 29, 2022
Application Filed
Jul 14, 2025
Non-Final Rejection — §103, §112
Oct 16, 2025
Response Filed
Dec 29, 2025
Final Rejection — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
75%
Grant Probability
86%
With Interview (+11.2%)
2y 9m
Median Time to Grant
Moderate
PTA Risk
Based on 929 resolved cases by this examiner. Grant probability derived from career allow rate.

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