DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Acknowledgement has been made to the amendment received on 02/19/2026. Claims 1-20 are pending in this application . Claims 19-20 are withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20160056198A1) in view of Horikoshi et al (US 20220077215 A1).
Re claim 1 Lee teaches, an integrated circuit (fig 8), comprising:
a photodiode region (100) [0107, 0116] disposed in a substrate (1, fig 8) [0141],
wherein:
the photodiode region (100) [0107, 0116] is configured to accumulate charge photogenerated in the photodiode region in response to incoming light [0075],
the photodiode region (100) comprises a top surface (top of 102) and a bottom surface (10b)[0084], the top surface (top of 102) being smaller than the bottom surface (10b is longer than top of 100c) [0084],
the photodiode region (100) comprises at least two doping concentrations (100b and 100c), and
a first doping concentration (100b) [0116] of the two doping concentrations that is closer to the top surface (top of 102) is higher [0116] than a second doping concentration (100c) of the two doping concentrations that is closer to the bottom surface 10b); and
a vertical transfer gate (111b) [0092] in the substrate (1), wherein:
the vertical transfer gate (111b) is above the top surface (top of 102) of the photodiode region (100) and is centrally symmetric in the center of 102, fig 8) to the top surface of the photodiode region (fig 8), and
Lee does not teach the vertical transfer gate is configured to transfer the photogenerated charge from the photodiode region to a transfer gate disposed on a surface of the substrate, wherein the vertical transfer gate disposed on a surface of the substrate, wherein the vertical transfer gate is disposed in the substrate vertically below the transfer gate.
Horikoshi teaches the vertical transfer gate (17, that transfers a signal charge from the photoelectric conversion, fig 3A) is configured to transfer the photogenerated charge from the photodiode region (11/12, fig 3A) [0066] to a transfer gate(16, fig3A) [0069] [0189] disposed on a surface of the substrate (from a top surface of 20 to top surface of 18, fig 3A), wherein the vertical transfer gate (17, fig 3A) disposed on a surface (bottom of the substrate, fig 3A) of the substrate, wherein the vertical transfer gate (17, fig 3A) is disposed in the substrate from a top surface of 20 to top surface of 18, fig 3A) vertically below the transfer gate (16, fig 3A) [0069].(see annotated figure 3A below).
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It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Horikoshi into the structure of Lee to include the vertical transfer gate is configured to transfer the photogenerated charge from the photodiode region to a transfer gate disposed on a surface of the substrate, wherein the vertical transfer gate disposed on a surface of the substrate, wherein the vertical transfer gate is disposed in the substrate vertically below the transfer gate as claimed.
The ordinary artisan would have been motivated to modify Lee based on the teaching of Horikoshi in the above manner for the purpose of to provide a photoelectric conversion element which enables an occupied area to be reduced and conversion efficiency and a dynamic range to be adjusted [0009].
Further, it has been held that rearranging part of an invention involves only routine skill in the art, In re Japikse, 86 USPQ 70.
Re claim 2 Lee in view of Horikoshi teach, the integrated circuit of claim 1, wherein the vertical transfer gate (111b) is centrally symmetric to the bottom surface (10b) of the photodiode region (100) [Lee, 0084]
Re claim 3 Lee in view of Horikoshi teach, the integrated circuit of claim 1, wherein: the photodiode region comprises a first well (100c) and a second well (100b), the first well (100c) is closer to the top surface (top of 102) of the photodiode region (100) than the second well (100b),the first well (100c) has the first doping concentration (concentration of 100a), and the second well (100b) has the second doping concentration (concentration of 100b)[Lee, 0084-0085].
Re claim 4 Lee in view of Horikoshi teach, the integrated circuit of claim 3, wherein: the photodiode region comprises a third well (100a), the third well is closer to the bottom surface (10b) of the photodiode region (100b) than the first well (100c) and the second well (100b), the third well (100a) has a third doping concentration (concentration of 100a), and the third doping concentration is lower than the first doping concentration and the second doping concentration [Lee,0084-0085].
Re claim 5 Lee in view of Horikoshi teaches, the integrated circuit of claim 1, wherein: the integrated circuit is an image sensor that includes a pixel (PR1), and the bottom surface of the photodiode region (10b) is configured to expand to 90% of a unit pixel area of the pixel (PR1) (at least 90% of pixel area see fig 8)[Lee, 0085].
Re claim 6 Lee in view of Horikoshi teaches, the integrated circuit of claim 5, wherein the vertical transfer gate (111b) is centrally symmetric (see fig 8) to the unit pixel area of the pixel (PR1) [0085].
Re claim 7 Lee in view of Horikoshi teaches, the integrated circuit of claim 1, wherein the substrate (1) is a p-type substrate [Lee,0141], and the photodiode region is an n-type region [Lee,0084].
Re claim 8 Lee in view of Horikoshi teaches, the integrated circuit of claim 7, further comprising a p-type well (110, fig 8) [0088] formed between the top surface of the photodiode region (100) and the vertical transfer gate (111b)[0088].
Re claim 9 Lee in view of Horikoshi teaches, he integrated circuit of claim 1, wherein the vertical transfer gate (111b) is further configured to transfer the photogenerated charge from the photodiode region (100) to the transfer gate (111a) located outside of the substrate (1) [Lee.0141].
Claims 10-18 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Horikoshi and Kawai et al (US 20090243019A1).
Re claim 10 Lee teaches, an integrated circuit, comprising:
a photodiode region (100, fig 8) [0086, 0107] disposed in a substrate (1, fig 8) [0141] , wherein:
the photodiode region (100, fig 8) [0107] is configured to accumulate charge photogenerated in the photodiode region in response to incoming light [0075, 0125], the photodiode region (100, fig 8) comprises a top surface (top of 100c), a first well (100c) and a second well (100b), the top surface (top of 100c) of the photodiode region(100) comprises a top surface of the first well (100c), and the first well (100c) has a first doping concentration (concentration of 100c) and a second doping concentration (concentration of 100b) of the second well (100b); and
a vertical transfer gate (111b) in the substrate (1) , wherein: the vertical transfer gate is above the top surface (top of 100c) of the photodiode region (100) and is centrally symmetric to the top surface of the first well (see fig 8), and
Lee does not teach the top surface of the photodiode region comprises a top surface of the first well and a top surface of the second well, the top surface of the first well is surrounded by the top surface of the second well, the second well has a depth that is deeper than a depth of the first well, and the first well has the first doping concentration that is higher than the second doping concentration of the second well.
Kawai does teach the top surface of the photodiode region (21/22, fig 1B) [0027] comprises a top surface of the first well (28, fig 1B) [0027] and a top surface of the second well (27, fig 1B)[0027] the top surface of the first well (28) is surrounded by the top surface of the second well (27), the second well (27) has a depth that is deeper (see fig 1B) than a depth of the first well (28), and the first well (28) has the first doping concentration (3X 1017 cm-3) that is higher than the second doping concentration (1x 10¹⁷ cm-3) of the second well (27).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Kawai into the structure of Lee to include the top surface of the photodiode region comprises a top surface of the first well and a top surface of the second well, the top surface of the first well is surrounded by the top surface of the second well, the second well has a depth that is deeper than a depth of the first well, and the first well has the first doping concentration that is higher than the second doping concentration of the second well as claimed.
The ordinary artisan would have been motivated to modify Lee based on the teaching of Kawai in the above manner for the purpose of increasing the precision of the light sensor [0027].
Lee and Kawai do not teach the vertical transfer gate is configured to transfer the photogenerated charge from the photodiode region to a transfer gate disposed on a surface of the substrate, wherein the vertical transfer gate disposed on a surface of the substrate, wherein the vertical transfer gate is disposed in the substrate vertically below the transfer gate.
Horikoshi teaches the vertical transfer gate (17, that transfers a signal charge from the photoelectric conversion, fig 3A) is configured to transfer the photogenerated charge from the photodiode region (11/12, fig 3A) [0066] to a transfer gate(16, fig3A) [0069] [0189] disposed on a surface of the substrate (from a top surface of 20 to top surface of 18, fig 3A), wherein the vertical transfer gate (16, fig 3A) [0069] disposed on a surface (bottom of the substrate, fig 3A) of the substrate, wherein the vertical transfer gate (17, fig 3A) is disposed in the substrate from a top surface of 20 to top surface of 18, fig 3A) vertically below the transfer gate (16, fig 3A) [0069].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Horikoshi into the structure of Lee and Kawai to include the vertical transfer gate is configured to transfer the photogenerated charge from the photodiode region to a transfer gate disposed on a surface of the substrate, wherein the vertical transfer gate disposed on a surface of the substrate, wherein the vertical transfer gate is disposed in the substrate vertically below the transfer gate as claimed.
The ordinary artisan would have been motivated to modify Lee and Kawai based on the teaching of Horikoshi in the above manner for the purpose of to provide a photoelectric conversion element which enables an occupied area to be reduced and conversion efficiency and a dynamic range to be adjusted [0009].
Further, it has been held that rearranging part of an invention involves only routine skill in the art, In re Japikse, 86 USPQ 70.
Re claim 11 Lee in view of Kawai and Horikoshi teach, the integrated circuit of claim 10, wherein the vertical transfer gate (112b) is centrally symmetric to the top surface of the second well (100b) [Lee, 0107].
Re claim 12 Lee in view Kawai and Horikoshi teach the integrated circuit of claim 10, wherein: the photodiode region (100) comprises a third well (100a) [0027],
Lee does not teach the top surface of the photodiode region comprises a top surface
of the third well, the top surface of the second well is surrounded by the top surface of the third well, the third well has a depth that is deeper than the depth of the second well, and the third well has a third doping concentration that is lower than the second doping concentration.
Kawai does teach, the top surface of the photodiode region (top of 21/22) [Kawai 0027] comprises a top surface of the third well (top of 26), the top surface of the second well (27) is surrounded by the top surface of the third well (26), the third well has a depth (depth of 26) that is deeper than the depth of the second well (depth of 27), and the third well (26) has a third doping concentration (2 x 10¹⁶) that is lower than the second doping concentration (1 X 10¹⁷cm⁻³) [Kawai, 0029].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught Kawai into the structure of
Lee to include the top surface of the photodiode region comprises a top surface of the third well, the top surface of the second well is surrounded by the top surface of the third well, the third well has a depth that is deeper than the depth of the second well, and the third well has a third doping concentration that is lower than the second doping concentration as claimed.
The ordinary artisan would have been motivated to modify Lee based on the teaching of Kawai in the above manner for the purpose of increasing the precision of the light sensor [0027].
Re claim 13 Lee in view of Kawai teach the integrated circuit of claim 12, wherein
the vertical transfer gate( (111b, fig 1B) is centrally symmetric to the top surface of the third well (top of 100a).
Re claim 14 Lee in view of Kawai teach the integrated circuit of claim 12, wherein:
the integrated circuit is an image sensor that includes a pixel, and the top surface of the third well is configured to expand to 90% of a unit pixel area of the pixel.
Re claim 15 Lee in view of Kawai the integrated circuit of claim 14, wherein the
vertical transfer gate (111b, fig 8) [0027] is centrally symmetric to the unit pixel area of the pixel (PR1) [0084].
Re claim 16 Lee in view of Kawai teach, the integrated circuit of claim 10, wherein
the substrate (1) is a p-type substrate [0141], and the photodiode region is an n-type region [0084].
Re claim 17 Lee teaches, the integrated circuit of claim 7, further comprising a p-
type well (110, fig 8) [0088] formed between the top surface of the photodiode region (100) and the vertical transfer gate (111b)[0088].
Re claim 18. Lee in view of Kawai and Horikoshi teaches the integrated circuit of claim 10, wherein the vertical transfer gate (17, fig 3A) [Horikoshi 0069] that transfers a signal charge from the photoelectric conversion, fig 3A) [Horikoshi,0189] is further configured to transfer the photogenerated image charge from the photodiode region (11/12, fig 3A) [ Horikoshi, 0066] to a transfer gate (16, fig 3A) located outside the substrate (16) [Horikoshi 0069].
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRATIKSHA J LOHAKARE whose telephone number is (571)270-1920. The examiner can normally be reached Monday - Friday 7.30 am-4.30 pm.
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/PRATIKSHA JAYANT LOHAKARE/ Examiner, Art Unit 2818
/DUY T NGUYEN/ Primary Examiner, Art Unit 2818 3/3/26