DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/02/2026 has been entered.
Status of the Application
Acknowledgement has been made to the amendment received on 5/5/2026. Claims 1-5,7-14, 16-20 are pending in this application Claims 6 and 15 are cancelled and claims 19-20 are withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, 7 and 9 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Watanabe et al (US20200350358A1).
Re claim 1 Watanabe teaches an integrated circuit (1111, fig 3) [0024], comprising:
a photodiode region (region of PD, fig 3) [0024] disposed in a substrate (1112) [0024], wherein:
the photodiode region (PD, fig 3) [0007, 0015] is configured to accumulate charge photogenerated in the photodiode region in response to incoming light [0015],
the photodiode region (PD) comprises a top surface (Top of PD, near 1121, fig 3) and a bottom surface (region below 1121, fig 3), the top surface being smaller than the bottom surface (see fig 3) [0024],
the photodiode region (PD) comprises at least two doping concentrations (concentrations 1113A and 1113B) [0024], and a first doping concentration (concentration of 1113A, fig 3) [0024] of the two doping concentrations that is closer to the top surface (closer to 1121) [0024] is higher than a second doping concentration (1113B, fig 3) of the two doping concentrations that is closer to the bottom surface (below 1121); and
a vertical transfer gate (bottom of 1116, fig 3) [0025] in the substrate (1112, fig 3),
wherein: the vertical transfer gate (top of 1116, fig 3) (see fig 3)is above the top surface of the photodiode region (see fig 3) and is centrally symmetric to the top surface of the photodiode region [0025], and the vertical transfer gate is configured to transfer the photogenerated charge from the photodiode region to a transfer gate (Top of Tr1, fig 3) [0007, 0015] disposed on a surface of the substrate (1112, fig 3),
wherein the vertical transfer gate (1116, fig 3) is disposed in the substrate vertically below the transfer gate (below the top portion of Tr1, fig 3); and
the integrated circuit (1111, fig 3) [0024] is an image sensor [0024] that includes a pixel (1131, fig 3) [0025], and the vertical transfer gate is centrally symmetric to a unit pixel area of the pixel. (the vertical transfer gate 1116 formed at a position corresponding to the center of a unit pixel and center of the photodiode PD, fig 3) [0025].
Re claim 2 Watanabe teaches the integrated circuit of claim 1, wherein the vertical transfer gate (bottom of 1116, fig 3) is centrally symmetric to the bottom surface of the photodiode region (fig 3) [0025].
Re claim 3 Watanabe teaches the integrated circuit of claim 1, wherein: the photodiode region(PD, fig 3) comprises a first well (1113A, fig 3) [0024] and a second well (1113B, fig 3) the first well (1113A, fig 3) is closer to the top surface of the photodiode region (PD, see fig 3) than the second well (1113B, fig 3) the first well has the first doping concentration (concentration of 1113A), and the second well (1113B) has the second doping concentration (concentration of 1113B).
Re claim 5 Watanabe teaches the integrated circuit of claim 1, wherein the bottom surface (bottom portion of 1121, fig 3) [0024] of the photodiode region (PD, fig 3) is configured to expand to 90% of the unit pixel area of the pixel (at least 90% of the unit pixel area 1131 see fig 3).
Re claim 7 Watanabe teaches the integrated circuit of claim 1, wherein the substrate is a p-type substrate (p-type silicon substrate, fig 3) [0023], and the photodiode region (PD, fig 3) is an n-type region [0024].
Re claim 9 Watanabe teaches the integrated circuit of claim 1, wherein the vertical transfer gate (bottom of 1116, fig 3) is further configured to transfer the photogenerated charge from the photodiode region (PD, fig 3) [0007, 0015] to the transfer gate (Tr1, top of 1116, fig 3) located outside of the substrate (1112, fig 3) .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 8 are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe in view of Lee et al (US20160056198A1).
Re claim 4 Watanabe teaches the integrated circuit of claim 3,
Watanabe do not teach the photodiode region comprises a third well, the third well is closer to the bottom surface of the photodiode region than the first well and the second well, the third well has a third doping concentration, and the third doping concentration is lower than the first doping concentration and the second doping concentration.
Lee teaches the photodiode region comprises a third well (100a), the third well is closer to the bottom surface (10b) of the photodiode region (100b) than the first well (100c) and the second well (100b), the third well (100a) has a third doping concentration (concentration of 100a), and the third doping concentration is lower than the first doping concentration and the second doping concentration [Lee,0084-0085].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Lee into the structure of Watanabe to include the photodiode region comprises a third well, the third well is closer to the bottom surface of the photodiode region than the first well and the second well, the third well has a third doping concentration, and the third doping concentration is lower than the first doping concentration and the second doping concentration as claimed.
The ordinary artisan would have been motivated to modify Watanabe based on the teaching of Lee in the above manner for the purpose of improving charge transfers in the image sensor.
It has been held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced, In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
Re claim 8 Watanabe teaches the integrated circuit of claim 7,
Watanabe do not teach a p-type well formed between the top surface of the photodiode region and the vertical transfer gate.
Lee teaches a p-type well (110, fig 8) [0088] formed between the top surface of the photodiode region (100, fig 8) and the vertical transfer gate (111b, fig 8).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Lee into the structure of to include a p-type well formed between the top surface of the photodiode region and the vertical transfer gate as claimed.
The ordinary artisan would have been motivated to modify Watanabe based on the teaching of Lee in the above manner for the purpose of improving charge transfers in the image sensor.
Claims 10-12, 14, 16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe et al (US20200350358A1) in view of Kawai et al (US20090243019A1).
Re claim 10 Watanabe teaches an integrated circuit (1111, fig 3), comprising:
a photodiode region (PD, fig 3) [0024] disposed in a substrate (1112, fig 3) [0024], wherein:
the photodiode region (PD, fig 3) [0007, 0015-0016] is configured to accumulate charge photogenerated in the photodiode region in response to incoming light [0015-0016],
the photodiode region (PD, fig 3) comprises a top surface (top pf 1121, fig 3), a first well (1113A, fig 3), and a second well (1113B, fig 3) [0024] the top surface of the photodiode region (PD, fig 3) comprises a top surface of the first well (top of 1134A, fig 3) [0024] and a top surface of the second well (top of 1113B, fig 3), the second well has a depth (depth of 1113B, fig 3) that is deeper (see fig 3) than a depth (depth of 1113A) of the first well, and the first well has a first doping concentration (doping concentration of 1113A, fig 3) [0024] that is higher than a second doping concentration of the second well (doping concentration of 113B, fig 3) [0024]; and
a vertical transfer gate (1116, fig 3) in the substrate (fig3), wherein:
the vertical transfer gate (1116, fig 3) [0024-0025] is above the top surface of the photodiode region (PD, fig 3) [0024] and is centrally symmetric to the top surface of the first well (1113A, fig 3), and the vertical transfer gate (1116, fig 3) is configured to transfer the photogenerated charge from the photodiode region (PD, fig 3) to a transfer gate (Tr1 top of 1116, fig 3) [0024-0025] disposed on a surface of the substrate (1112, fig 3), wherein
the vertical transfer gate (bottom of 1116, fig 3)[0024-0025] is disposed in the substrate (1112, fig 3) vertically below the transfer gate (Tr1/top of 1116, fig 3), and
the integrated circuit (1111, fig 3) [0024] is an image sensor (imaging device) that includes a pixel (each pixel, fig 3) [0024], and the vertical transfer gate (Tr1, top of 1116, fig 3) [0024] is centrally symmetric to a unit pixel area of the pixel [0025].
Watanabe does not teach the top surface of the first well is surrounded by the top surface of the second well.
Kawai does teach the top surface of the first well (28, fig 1B) [0027] is surrounded by the top surface of the second well (27, fig 1B) [0027].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Kawai into the structure of Watanabe to include the top surface of the first well is surrounded by the top surface of the second well as claimed.
The ordinary artisan would have been motivated to modify Watanabe based on the teaching of Kawai in the above manner for the purpose of increasing the precision of the light sensor [0027].
Further, it has been held that rearranging part of an invention involves only routine skill in the art, In re Japikse, 86 USPQ 70.
Re claim 11 Watanabe in view of Kawai teaches the integrated circuit of claim 10, wherein the vertical transfer gate (bottom of 1116, fig 3) [Watanabe, 0024] is centrally symmetric to the top surface of the second well (1113B, fig 3) [0024].
Re claim 12 Watanabe in view of Kawai teaches the integrated circuit of claim 10,
Watanabe does not teach the photodiode region comprises a third well, the top surface of the photodiode region comprises a top surface of the third well, the top surface of the second well is surrounded by the top surface of the third well, the third well has a depth that is deeper than the depth of the second well, and the third well has a third doping concentration that is lower than the second doping concentration.
Kawai teaches the photodiode region (21/22, fig1B) [0027] comprises a third well the top surface of the photodiode region (top of 21/22) [Kawai 0027] comprises a top surface of the third well (top of 26), the top surface of the second well (27) is surrounded by the top surface of the third well (26), the third well has a depth (depth of 26) that is deeper than the depth of the second well (depth of 27), and the third well (26) has a third doping concentration (2x 10¹⁶) that is lower than the second doping concentration (1 X 1017cm³) [Kawai, 0029].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Kawai into the structure of Watanabe to include the photodiode region comprises a third well, the top surface of the photodiode region comprises a top surface of the third well, the top surface of the second well is surrounded by the top surface of the third well, the third well has a depth that is deeper than the depth of the second well, and the third well has a third doping concentration that is lower than the second doping concentration as claimed.
The ordinary artisan would have been motivated to modify Watanabe based on the teaching of Kawai in the above manner for the purpose of increasing the precession of the light sensor [0027].
It has been held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced, In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
Re claim 14 Watanabe in view of Kawai teach the integrated circuit of claim 12,
the top surface of the third well (top of 26, fig 1B) [Kawai, 0027] is configured to expand to 90% of the unit pixel area of the pixel (at least 90% of the unit pixel area, fig 1B) [Kawai, 0027].
Re claim 16 Watanabe in view of Kawai teach the integrated circuit of claim 10, wherein the substrate is a p-type substrate (p-type silicon substrate, fig 3) [Watanabe, 0023], and the photodiode region (PD, fig 3) is an n-type region [Watanabe, 0024].
Re claim 18 Watanabe in view of Kawai teach the integrated circuit of claim 10, wherein the vertical transfer gate (Tr1, top of 1116, fig 3) [0024] is further configured to transfer the photogenerated image charge from the photodiode region (PD, fig 3) [0024] to a transfer gate (top of 1116, fig 3) located outside the substrate (1112, fig 3) [0024] .
Claims 13 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe modified by Kawai as applied to claim 10 and further in view of Lee et al (US20160056198A1) .
Re claim 13 Watanabe in view of Kawai teach the integrated circuit of claim 12,
Watanabe and Kawai do not teach the vertical transfer gate is centrally symmetric to the top surface of the third well.
Lee teaches the vertical transfer gate (111b, fig 1B) [0027] is centrally symmetric to the top surface of the third well (top of 100a).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Lee into the structure of Watanabe and Kawai to include the vertical transfer gate is centrally symmetric to the top surface of the third well as claimed.
The ordinary artisan would have been motivated to modify Watanabe and Kawai based on the teaching of Lee in the above manner for the purpose of improving the efficiency of the device.
Re claim 17 Watanabe in view of Kawai the integrated circuit of claim 16
Watanabe do not teach a p-type well formed between the top surface of the photodiode region and the vertical transfer gate.
Lee teaches a p-type well (110, fig 8) [0088] formed between the top surface of the photodiode region (100, fig 8) and the vertical transfer gate (111b, fig 8).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Lee into the structure of to include a p-type well formed between the top surface of the photodiode region and the vertical transfer gate as claimed.
The ordinary artisan would have been motivated to modify Watanabe based on the teaching of Lee in the above manner for the purpose of improving charge transfers in the image sensor.
Response to Arguments
Applicant’s arguments with respect to claims 1-5, 7-14, 16-17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRATIKSHA J LOHAKARE whose telephone number is (571)270-1920. The examiner can normally be reached Monday - Friday 7.30 am-4.30 pm.
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/PRATIKSHA JAYANT LOHAKARE/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 6/29/26
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