Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Amendment filed on 3/20/2065 has been entered. Claims 2 – 5, 10, 21 are amended. Claims 1 – 21 are pending in the present application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1– 21 are rejected under 35 U.S.C. 103 as being unpatentable over Yu ( Pub. No. US 20180122906 A1 ), hereinafter Yu, in view of Yu.
PNG
media_image1.png
871
1429
media_image1.png
Greyscale
Regarding Independent Claim 1 (Previously Presented), Yu teaches an electronic device, comprising:
memory pillars ( Yu, FIG. 86A, 50, 60; FIG. 29A, 50, 60; FIG. 29B, 50, 60; [0192], memory stack structures (50, 60); [0199], memory film 50; [0200], semiconductor channels 60 ) comprising a channel material ( Yu, FIG. 86A, 60; FIG. 29A, 38; FIG. 29B, 60 ; [0200], semiconductor channels 60 ) and extending through both a cell region ( Yu, FIG. 29B, portions above 38L, including 46, 132, 232, 332; [0234], continuous source strap layer 38L; [0219], plurality of electrically conductive layers 46; [0168], first insulating layers 132; [0184], intermediate insulating layers 232; [0185], N-th insulating layers 332 ) and a lateral contact region ( Yu, FIG. 29B, 38L; [0234], continuous source strap layer 38L ), the lateral contact region ( Yu, FIG. 29B, 38L; [0234] ) comprising:
a bottom semiconductive material ( Yu, FIG. 29B, top portion of 112; [0152], source semiconductor layer 112 );
a source contact ( Yu, FIG. 86A, 38; FIG. 29A, 38; FIG. 29B, 38L; [0214], source strap rails 38; [0234], continuous source strap layer 38L ) adjacent to the bottom semiconductive material ( Yu, FIG. 29B, top portion of 112; [0152] ) and in direct contact with the channel material;
sidewalls of the top semiconductive material comprising:
at least one first step ( Yu, FIG. 29B, top portion of 38L; [0234], continuous source strap layer 38L ); and
at least one second step ( Yu, FIG. 29B, bottom portion of 38L; [0234], continuous source strap layer 38L ) ( Yu, FIG. 29B, the bulging portion and the non-bulging portion in 38L, from non-bulging to bulging portion is one step, from bulging portion to non-bulging portion is another step; also there are left side and right side, which doubles the number of steps );
wherein the source contact ( Yu, FIG. 86A, 38; FIG. 29A, 38; FIG. 29B, 38L; [0214], source strap rails 38; [0234], continuous source strap layer 38L ) is in direct contact with the channel material ( Yu, FIG. 86A, 60; FIG. 29B, 60 ; [0200], semiconductor channels 60 ) adjacent to the at least one second step ( Yu, FIG. 29B, bottom portion of 38L; [0234], continuous source strap layer 38L ).
Yu did not explicitly disclose:
A top semiconductive material adjacent to the source contact and not in direct contact with the channel material;
However, Yu disclosed:
A source semiconductor layer 112 and a second sidewall 39S2 adjacent to source strap layer 38L / source strap rails 38, and not in direct contact with the channels 60, and the source semiconductor layer 112 is adjacent to the bulging portion, as shown in FIG. 24D, FIG. 26B, FIG. 32D, FIG. 85, FIG. 86A;
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yu ( FIG. 29B, top portion of 38L, adjacent to the bulging portion; [0234], continuous source strap layer 38L ), to incorporate the teachings of Yu ( A source semiconductor layer 112 and a second sidewall 39S2 adjacent to source strap layer 38L / source strap rails 38, and not in direct contact with the channels 60, and the source semiconductor layer 112 is adjacent to the bulging portion, as shown in FIG. 24D, FIG. 26B, FIG. 32D, FIG. 85, FIG. 86A ), to implement that a top semiconductive material ( i.e. top portion of 38L is replaced by source semiconductor layer 112 and second sidewall 39S2 ) adjacent to the source contact ( i.e. bottom portion of 38L ) and not in direct contact with the channel material. Doing so would provide a specific design for the source contact in direct contact with channel material in semiconductor NAND / Flash memory which has the stepped pillar region / bulging portion, and therefore the performance of source contact can be improved.
Regarding Claim 2 (Currently Amended), Yu teaches the electronic device as claimed in claim 1, on which this claim is dependent, Yu further teaches:
wherein the lateral contact region ( Yu, FIG. 29B, 38L; [0234], continuous source strap layer 38L ) comprises a stepped pillar region ( Yu, FIG. 29B, lower portion of each memory stack structure (50, 60) has a bulging portion in 38L; Abstract, Memory stack structures can be formed with a greater sidewall surface area in the bulging portions to provide a greater contact area with the source strap structure; [0004], lower portion of each memory stack structure has a bulging portion that has a greater lateral dimension than an overlying portion of the respective memory stack structure; at least one source strap structure contacting a respective subset of the semiconductor channels of the memory stack structures at a level of the bulging portion of each memory stack structure ) comprising a first step ( Yu, FIG. 29B, top portion of 38L; [0234], continuous source strap layer 38L ) and a second step ( Yu, FIG. 29B, bottom portion of 38L; [0234], continuous source strap layer 38L ) ( Yu, FIG. 29B, the bulging portion and the non-bulging portion in 38L, from non-bulging to bulging portion is one step, from bulging portion to non-bulging portion is another step; also there are left side and right side, which doubles the number of steps ).
Regarding Claim 3 (Currently Amended), Yu teaches the electronic device as claimed in claim 2, on which this claim is dependent, Yu further teaches:
wherein the second step ( Yu, FIG. 29B, bottom portion of 38L; [0234], continuous source strap layer 38L ) of the stepped pillar region ( Yu, FIG. 29B, lower portion of each memory stack structure (50, 60) has a bulging portion in 38L; [0004], lower portion of each memory stack structure has a bulging portion that has a greater lateral dimension than an overlying portion of the respective memory stack structure ) in the lateral contact region ( Yu, FIG. 29B, 38L; [0234], continuous source strap layer 38L ) exhibits a relatively smaller critical dimension than a critical dimension of the first step ( Yu, FIG. 29B, top portion of 38L; [0234], continuous source strap layer 38L ) of the stepped pillar region ( Yu, FIG. 29B, lower portion of each memory stack structure (50, 60) has a bulging portion in 38L; [0004], lower portion of each memory stack structure has a bulging portion that has a greater lateral dimension than an overlying portion of the respective memory stack structure ).
Regarding Claim 4 (Currently Amended), Yu teaches the electronic device as claimed in claim 2, on which this claim is dependent, Yu further teaches:
wherein the second step ( Yu, FIG. 29B, bottom portion of 38L; [0234], continuous source strap layer 38L ) of the stepped pillar region ( Yu, FIG. 29B, lower portion of each memory stack structure (50, 60) has a bulging portion in 38L; [0004], lower portion of each memory stack structure has a bulging portion that has a greater lateral dimension than an overlying portion of the respective memory stack structure ) in the lateral contact region ( Yu, FIG. 29B, 38L; [0234], continuous source strap layer 38L ) exhibits a relatively smaller critical dimension than a critical dimension of the memory pillars ( Yu, FIG. 86A, 50, 60; FIG. 29A, 50, 60; FIG. 29B, 50, 60; [0192], memory stack structures (50, 60); [0199], memory film 50; [0200], semiconductor channels 60 ) of the cell region ( Yu, FIG. 29B, portions above 38L, including 46, 132, 232, 332; [0234], continuous source strap layer 38L; [0219], plurality of electrically conductive layers 46; [0168], first insulating layers 132; [0184], intermediate insulating layers 232; [0185], N-th insulating layers 332 ) .
Regarding Claim 5 (Currently Amended), Yu teaches the electronic device as claimed in claim 1, on which this claim is dependent, Yu further teaches:
wherein the channel material ( Yu, FIG. 86A, 60; FIG. 29A, 38; FIG. 29B, 60 ; [0200], semiconductor channels 60 ) in the lateral contact region ( Yu, FIG. 29B, 38L; [0234], continuous source strap layer 38L ) substantially fills the second step ( Yu, FIG. 29B, bottom portion of 38L; [0234], continuous source strap layer 38L ) of the stepped pillar region ( Yu, FIG. 29B, lower portion of each memory stack structure (50, 60) has a bulging portion in 38L; [0004], lower portion of each memory stack structure has a bulging portion that has a greater lateral dimension than an overlying portion of the respective memory stack structure ).
Regarding Claim 6 (Original), Yu teaches the electronic device as claimed in claim 1, on which this claim is dependent, Yu further teaches:
further comprising a fill material ( Yu, FIG. 29B, 62; [0201], dielectric core 62 ) adjacent to the channel material ( Yu, FIG. 86A, 60; FIG. 29A, 38; FIG. 29B, 60 ; [0200], semiconductor channels 60 ) in the lateral contact region ( Yu, FIG. 29B, 38L; [0234], continuous source strap layer 38L ) of the memory pillars (Yu, FIG. 86A, 50, 60; FIG. 29A, 50, 60; FIG. 29B, 50, 60; [0192], memory stack structures (50, 60); [0199], memory film 50; [0200], semiconductor channels 60).
Regarding Claim 7 (Original), Yu teaches the electronic device as claimed in claim 6, on which this claim is dependent, Yu further teaches:
wherein a thickness of the fill material ( Yu, FIG. 29B, 62, especially approaching to the bottom end; [0201], dielectric core 62 ) is less than a thickness of the channel material ( Yu, FIG. 86A, 60; FIG. 29A, 38; FIG. 29B, 60 ; [0200], semiconductor channels 60 ) in the lateral contact region ( Yu, FIG. 29B, 38L; [0234], continuous source strap layer 38L ) of the memory pillars ( Yu, FIG. 86A, 50, 60; FIG. 29A, 50, 60; FIG. 29B, 50, 60; [0192], memory stack structures (50, 60); [0199], memory film 50; [0200], semiconductor channels 60 ).
Regarding Claim 8 (Original), Yu teaches the electronic device as claimed in claim 6, on which this claim is dependent, Yu further teaches:
wherein a thickness of the fill material ( Yu, FIG. 29B, 62, especially the bulging portion; [0201], dielectric core 62 ) is greater than a thickness of the channel material ( Yu, FIG. 86A, 60; FIG. 29A, 38; FIG. 29B, 60 ; [0200], semiconductor channels 60 ) in the lateral contact region ( Yu, FIG. 29B, 38L; [0234], continuous source strap layer 38L ) of the memory pillars ( Yu, FIG. 86A, 50, 60; FIG. 29A, 50, 60; FIG. 29B, 50, 60; [0192], memory stack structures (50, 60); [0199], memory film 50; [0200], semiconductor channels 60 ).
Regarding Claim 9 (Original), Yu teaches the electronic device as claimed in claim 6, on which this claim is dependent, Yu further teaches:
wherein a thickness of the channel material ( Yu, FIG. 86A, 60; FIG. 29A, 38; FIG. 29B, 60 ; [0200], semiconductor channels 60; especially the non-bulging portion in 38L ) in direct contact with the source contact ( Yu, FIG. 86A, 38; FIG. 29A, 38; FIG. 29B, 38L; [0214], source strap rails 38; [0234], continuous source strap layer 38L ) is substantially equal to the thickness of the channel material ( Yu, FIG. 86A, 60; FIG. 29A, 38; FIG. 29B, 60 ; [0200], semiconductor channels 60 ) in the cell region ( Yu, FIG. 29B, portions above 38L, including 46, 132, 232, 332; [0234], continuous source strap layer 38L; [0219], plurality of electrically conductive layers 46; [0168], first insulating layers 132; [0184], intermediate insulating layers 232; [0185], N-th insulating layers 332 ).
Regarding Claim 10 (Currently Amended), Yu teaches the electronic device as claimed in claim 2, on which this claim is dependent, Yu further teaches:
wherein the first step ( Yu, FIG. 29B, top portion of 38L; [0234], continuous source strap layer 38L ) of the stepped pillar region ( Yu, FIG. 29B, lower portion of each memory stack structure (50, 60) has a bulging portion in 38L; [0004], lower portion of each memory stack structure has a bulging portion that has a greater lateral dimension than an overlying portion of the respective memory stack structure ) and the second step ( Yu, FIG. 29B, bottom portion of 38L; [0234], continuous source strap layer 38L ) of the stepped pillar region exhibit sloped sidewalls ( Yu, FIG. 29B, the bulging portion and the non-bulging portion in 38L, from non-bulging to bulging portion is one step which has a sloped sidewall, from bulging portion to non-bulging portion is another step which has another sloped sidewall; also there are left side and right side, which doubles the number of steps or sloped side walls ).
Regarding Claim 11 (Previously Presented), Yu teaches the electronic device as claimed in claim 1, on which this claim is dependent, Yu further teaches:
wherein a portion of the source contact ( Yu, FIG. 86A, 38; FIG. 29A, 38; FIG. 29B, 38L; [0214], source strap rails 38; [0234], continuous source strap layer 38L ) proximal to the memory pillars ( Yu, FIG. 86A, 50, 60; FIG. 29A, 50, 60; FIG. 29B, 50, 60; [0192], memory stack structures (50, 60); [0199], memory film 50; [0200], semiconductor channels 60 ) exhibits a greater thickness ( Yu, FIG. 29B, the thickness of source contact ( 38, 38L ) is getting thinner because of the bulging in 38L, ) than a portion of the source contact ( Yu, FIG. 86A, 38; FIG. 29A, 38; FIG. 29B, 38L; [0214], source strap rails 38; [0234], continuous source strap layer 38L ) distal to the memory pillars ( Yu, FIG. 86A, 50, 60; FIG. 29A, 50, 60; FIG. 29B, 50, 60; [0192], memory stack structures (50, 60); [0199], memory film 50; [0200], semiconductor channels 60 ).
Regarding Claim 12 (Original), Yu teaches the electronic device as claimed in claim 1, on which this claim is dependent, Yu further teaches:
wherein the channel material ( Yu, FIG. 86A, 60; FIG. 29A, 38; FIG. 29B, 60 ; [0200], semiconductor channels 60 ) extends continuously along an entire height of the memory pillars ( Yu, FIG. 86A, 50, 60; FIG. 29A, 50, 60; FIG. 29B, 50, 60; [0192], memory stack structures (50, 60); [0199], memory film 50; [0200], semiconductor channels 60 ).
Regarding Claim 13 (Original), Yu teaches the electronic device as claimed in claim 1, on which this claim is dependent, Yu further teaches:
wherein a thickness of the channel material ( Yu, FIG. 86A, 60; FIG. 29A, 38; FIG. 29B, 60 ; [0200], semiconductor channels 60; especially the bulging portion in 38L ) in direct contact with the source contact ( Yu, FIG. 86A, 38; FIG. 29A, 38; FIG. 29B, 38L; [0214], source strap rails 38; [0234], continuous source strap layer 38L ) is greater than a thickness of the channel material ( Yu, FIG. 86A, 60; FIG. 29A, 38; FIG. 29B, 60 ; [0200], semiconductor channels 60 ) in the cell region ( Yu, FIG. 29B, portions above 38L, including 46, 132, 232, 332 ).
Regarding Independent Claim 14 (Previously Presented), Yu teaches an electronic device, comprising:
a bottom semiconductive material ( Yu, FIG. 29B, top portion of 112; [0152], source semiconductor layer 112 );
a source contact ( Yu, FIG. 86A, 38; FIG. 29A, 38; FIG. 29B, 38L; [0214], source strap rails 38; [0234], continuous source strap layer 38L ) adjacent to the bottom semiconductive material ( Yu, FIG. 29B, top portion of 112; [0152], source semiconductor layer 112 );
a top semiconductive material ( Yu, FIG. 29B, top portion of 38L; [0234], continuous source strap layer 38L ) adjacent to the source contact ( Yu, FIG. 86A, 38; FIG. 29A, 38; FIG. 29B, 38L; [0214], source strap rails 38; [0234], continuous source strap layer 38L );
tiers of alternating conductive materials ( Yu, FIG. 29B, 46; [0219], plurality of electrically conductive layers 46 ) and dielectric materials ( Yu, FIG. 29B, 132, 232, 332; [0234]; [0168], first insulating layers 132; [0184], intermediate insulating layers 232; [0185], N-th insulating layers 332 ) adjacent to the top semiconductive material ( Yu, FIG. 29B, top portion of 38L; [0234], continuous source strap layer 38L );
pillars ( Yu, FIG. 86A, 50, 60; FIG. 29A, 50, 60; FIG. 29B, 50, 60; [0192], memory stack structures (50, 60); [0199], memory film 50; [0200], semiconductor channels 60 ) extending through the tiers, the top semiconductive material ( Yu, FIG. 29B, top portion of 38L; [0234], continuous source strap layer 38L ), and the source contact ( Yu, FIG. 86A, 38; FIG. 29A, 38; FIG. 29B, 38L; [0214], source strap rails 38; [0234], continuous source strap layer 38L ) and into the bottom semiconductive material ( Yu, FIG. 29B, top portion of 112; [0152], source semiconductor layer 112 ), the pillars ( Yu, FIG. 86A, 50, 60; FIG. 29A, 50, 60; FIG. 29B, 50, 60; [0192], memory stack structures (50, 60); [0199], memory film 50; [0200], semiconductor channels 60 ) comprising:
a channel material ( Yu, FIG. 86A, 60; FIG. 29A, 38; FIG. 29B, 60 ; [0200], semiconductor channels 60 ), wherein a thickness of the channel material ( Yu, FIG. 86A, 60; FIG. 29A, 38; FIG. 29B, 60 ; [0200], semiconductor channels 60 ) laterally adjacent to the tiers ( conductive materials ( Yu, FIG. 29B, conductive layers 46 ) and dielectric materials ( Yu, FIG. 29B, 132, 232, 332; first insulating layers 132; intermediate insulating layers 232; N-th insulating layers 332 ) ) is less than the thickness of the channel material ( Yu, FIG. 86A, 60; FIG. 29A, 38; FIG. 29B, 60 ; [0200], semiconductor channels 60 ) laterally adjacent to the source contact ( Yu, FIG. 86A, 38; FIG. 29A, 38; FIG. 29B, 38L; [0214], source strap rails 38; [0234], continuous source strap layer 38L ); and
a portion of the source contact (Yu, FIG. 86A, 38; FIG. 29A, 38; FIG. 29B, 38L; [0214]; [0234]) proximal to the pillars exhibiting a greater thickness ( Yu, FIG. 29B, the thickness of source contact ( 38, 38L ) is getting thinner because of the bulging in 38L ) than a portion of the source contact distal to the pillars (Yu, FIG. 86A, 38; FIG. 29A, 38; FIG. 29B, 38L; [0214]; [0234]).
Regarding Claim 15 (Original), Yu teaches the electronic device as claimed in claim 14, on which this claim is dependent, Yu further teaches:
wherein a diameter of a portion ( Yu, FIG. 29B, lower portion of each memory stack structure (50, 60) has a bulging portion in 38L ) of the pillars ( Yu, FIG. 86A, 50, 60; FIG. 29A, 50, 60; FIG. 29B, 50, 60; [0192], memory stack structures (50, 60); [0199], memory film 50; [0200], semiconductor channels 60 ) laterally adjacent to the top semiconductive material ( Yu, FIG. 29B, top portion of 38L; [0234], continuous source strap layer 38L ) is greater than a diameter of a portion ( Yu, FIG. 29B, each memory stack structure (50, 60) has non-bulging portions, especially the non-bulging portions above 38L ) of the pillars ( Yu, FIG. 86A, 50, 60; FIG. 29A, 50, 60; FIG. 29B, 50, 60; [0192], memory stack structures (50, 60); [0199], memory film 50; [0200], semiconductor channels 60 ) laterally adjacent to the tiers of alternating conductive materials ( Yu, FIG. 29B, 46; [0219], plurality of electrically conductive layers 46 ) and dielectric materials ( Yu, FIG. 29B, 132, 232, 332; [0168], first insulating layers 132; [0184], intermediate insulating layers 232; [0185], N-th insulating layers 332 ).
Regarding Claim 16 (Original), Yu teaches the electronic device as claimed in claim 14, on which this claim is dependent, Yu further teaches:
wherein a diameter of a portion ( Yu, FIG. 29B, lower portion of each memory stack structure (50, 60) has non-bulging portions, especially the non-bulging portions in 38L and in 112 ) of the pillars ( Yu, FIG. 86A, 50, 60; FIG. 29A, 50, 60; FIG. 29B, 50, 60; [0192], memory stack structures (50, 60); [0199], memory film 50; [0200], semiconductor channels 60 ) laterally adjacent to the source contact ( Yu, FIG. 86A, 38; FIG. 29A, 38; FIG. 29B, 38L; [0214], source strap rails 38; [0234], continuous source strap layer 38L ) and the bottom semiconductive material ( Yu, FIG. 29B, top portion of 112; [0152], source semiconductor layer 112 ) is less than the diameter of a portion ( Yu, FIG. 29B, lower portion of each memory stack structure (50, 60) has a bulging portion in 38L ) of the pillars ( Yu, FIG. 86A, 50, 60; FIG. 29A, 50, 60; FIG. 29B, 50, 60; [0192], memory stack structures (50, 60); [0199], memory film 50; [0200], semiconductor channels 60 ) laterally adjacent to the top semiconductive material ( Yu, FIG. 29B, top portion of 38L; [0234], continuous source strap layer 38L ).
Regarding Claim 17 (Original), Yu teaches the electronic device as claimed in claim 14, on which this claim is dependent, Yu further teaches:
wherein the channel material ( Yu, FIG. 86A, 60; FIG. 29A, 38; FIG. 29B, 60 ; [0200], semiconductor channels 60 ) comprises a polysilicon material, a III-V compound semiconductive material, a II-VI compound semiconductive material, an organic semiconductive material, GaAs, InP, GaP, GaN, an oxide semiconductive material, or a combination thereof ( Yu, [0200], The semiconductor channel layer includes a semiconductor material that is employed to form semiconductor channels 60. The semiconductor channel layer includes at least one semiconductor material that may include at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel layer includes amorphous silicon or polysilicon ).
Regarding Claim 18 (Original), Yu teaches the electronic device as claimed in claim 14, on which this claim is dependent, Yu further teaches:
wherein the channel material ( Yu, FIG. 86A, 60; FIG. 29A, 38; FIG. 29B, 60 ; [0200], semiconductor channels 60 ) in a cell region exhibits a different dopant concentration ( Yu, FIG. 29B, each memory stack structure (50, 60) has non-bulging portions above 38L (i.e. in the cell region), the semiconductor channels 60 do not directly contact with source strap rails 38 or continuous source strap layer 38L, therefore exhibit a different dopant concentration ) than the channel material ( Yu, FIG. 86A, 60; FIG. 29A, 38; FIG. 29B, 60 ; [0200], semiconductor channels 60 ) in a lateral contact region ( Yu, FIG. 29B, 38L; [0234], continuous source strap layer 38L ) ( Yu, [0153], The dopant concentration of the source semiconductor layer 112 can be in a range from 1.0 × 1019/cm3 to 2.0 × 1021/cm3, although lesser and greater dopant concentrations can also be employed; [0241], The source strap rails 38 are formed directly on the outer sidewalls of the semiconductor channels 60 ).
Regarding Independent Claim 19 (Previously Presented), Yu teaches a method of forming an electronic device, the method comprising:
forming a bottom semiconductive material ( Yu, FIG. 29B, top portion of 112; [0152], source semiconductor layer 112 );
forming a source contact ( Yu, FIG. 86A, 38; FIG. 29A, 38; FIG. 29B, 38L; [0214], source strap rails 38; [0234], continuous source strap layer 38L ) sacrificial material ( Yu, Abstract, sacrificial semiconductor pedestals can be formed in source-level memory openings prior to formation of a vertically alternating stack of insulating layers and sacrificial material layers ) adjacent to the bottom semiconductive material ( Yu, FIG. 29B, top portion of 112; [0152], source semiconductor layer 112 );
forming a top semiconductive material ( Yu, FIG. 29B, top portion of 38L; [0234], continuous source strap layer 38L ) adjacent to the source contact ( Yu, FIG. 86A, 38; FIG. 29A, 38; FIG. 29B, 38L; [0214], source strap rails 38; [0234], continuous source strap layer 38L ) sacrificial material;
removing a portion of the bottom semiconductive material ( Yu, FIG. 29B, top portion of 112; [0152], source semiconductor layer 112 ), a portion of the source contact ( Yu, FIG. 86A, 38; FIG. 29A, 38; FIG. 29B, 38L; [0214], source strap rails 38; [0234], continuous source strap layer 38L ) sacrificial material ( Yu, Abstract, sacrificial semiconductor pedestals can be formed in source-level memory openings prior to formation of a vertically alternating stack of insulating layers and sacrificial material layers ), and a portion of the top semiconductive material ( Yu, FIG. 29B, top portion of 38L; [0234], continuous source strap layer 38L ) to form two or more stepped openings in the top semiconductive material ( Yu, FIG. 29B, the bulging portion and the non-bulging portion in 38L, from non-bulging to bulging portion is one step, from bulging portion to non-bulging portion is another step; also there are left side and right side, which doubles the number of step openings );
forming a sacrificial structure ( Yu, Abstract, formation of … sacrificial material layers ) in the stepped openings ( Yu, FIG. 29B, the bulging portion and the non-bulging portion in 38L );
forming tiers ( Yu, FIG. 29B, 46, 132, 232, 332; [0219], plurality of electrically conductive layers 46; [0168], first insulating layers 132; [0184], intermediate insulating layers 232; [0185], N-th insulating layers 332 ) adjacent to the top semiconductive material ( Yu, FIG. 29B, top portion of 38L; [0234], continuous source strap layer 38L ) and the sacrificial structure ( Yu, Abstract, formation of … sacrificial material layers );
forming pillar openings ( Yu, [0178], first-tier memory openings 149 ) through the tiers ( Yu, FIG. 29B, 46, 132, 232, 332; [0219], plurality of electrically conductive layers 46; [0168], first insulating layers 132; [0184], intermediate insulating layers 232; [0185], N-th insulating layers 332 );
removing the sacrificial structure ( Yu, Abstract, formation of … sacrificial material layers ) from the stepped openings ( Yu, FIG. 29B, the bulging portion and the non-bulging portion in 38L ) to form a stepped feature region ( Yu, Abstract, Memory openings can include bulging portions formed by removal of the sacrificial semiconductor pedestals );
forming cell films ( Yu, FIG. 29B, 50, 60; [0199], memory film 50; [0200], semiconductor channels 60 ) in the pillar openings ( Yu, [0178], first-tier memory openings 149 ) and the stepped feature region( Yu, Abstract, Memory openings can include bulging portions formed by removal of the sacrificial semiconductor pedestals ), the cell films ( Yu, FIG. 29B, 50, 60; [0199], memory film 50; [0200], semiconductor channels 60 ) comprising a channel material ( Yu, FIG. 86A, 60; FIG. 29A, 38; FIG. 29B, 60 ; [0200], semiconductor channels 60 );
removing a portion of the channel material ( Yu, FIG. 86A, 60; FIG. 29A, 38; FIG. 29B, 60 ; [0200], semiconductor channels 60 ) in the pillar openings ( Yu, [0178], first-tier memory openings 149 );
selectively removing the source contact ( Yu, FIG. 86A, 38; FIG. 29A, 38; [0214], source strap rails 38 ) sacrificial material to form a source contact opening ( Yu, [0209], Source cavities 119 ); and
forming a source contact ( Yu, FIG. 86A, 38; FIG. 29A, 38; [0214], source strap rails 38 ) in the source contact opening ( Yu, [0209], Source cavities 119 ) extending laterally and contacting the channel material ( Yu, FIG. 86A, 60; FIG. 29A, 38; FIG. 29B, 60 ; [0200], semiconductor channels 60 ).
Regarding Claim 20 (Original), Yu teaches the method as claimed in claim 19, on which this claim is dependent, Yu further teaches:
further comprising forming a fill material ( Yu, FIG. 29B, 62; [0201], dielectric core 62 ) adjacent to the channel material ( Yu, FIG. 86A, 60; FIG. 29A, 38; FIG. 29B, 60 ; [0200], semiconductor channels 60 ) in the stepped feature region ( Yu, Abstract, Memory openings can include bulging portions formed by removal of the sacrificial semiconductor pedestals ).
Regarding Claim 21 (Currently Amended), Yu teaches the method as claimed in claim 19, on which this claim is dependent, Yu further teaches:
wherein removing a portion of the bottom semiconductive material ( Yu, FIG. 29B, top portion of 112; [0152], source semiconductor layer 112 ), a portion of the source contact ( Yu, FIG. 86A, 38; FIG. 29A, 38; FIG. 29B, 38L; [0214], source strap rails 38; [0234], continuous source strap layer 38L ) sacrificial material ( Yu, Abstract, sacrificial semiconductor pedestals can be formed in source-level memory openings prior to formation of a vertically alternating stack of insulating layers and sacrificial material layers ), and a portion of the top semiconductive material ( Yu, FIG. 29B, top portion of 38L; [0234], continuous source strap layer 38L ) to form stepped openings ( Yu, FIG. 29B, the bulging portion and the non-bulging portion in 38L ) comprises etching a slot ( Yu, FIG. 27B, 39; [0230], source-level memory openings 39 ) in the top semiconductive material ( Yu, FIG. 29B, top portion of 38L; [0234], continuous source strap layer 38L ), forming a spacer ( Yu, FIG. 27B, 115; [0232], second dielectric liner 115 ) adjacent to the slot, etching an additional slot ( Yu, FIG. 28, 39, wider and deeper than 39 in FIG. 27B; [0230], source-level memory openings 39 ) through the spacer ( Yu, FIG. 28, 115; [0232], second dielectric liner 115 ) and through the source contact ( Yu, FIG. 86A, 38; FIG. 29A, 38; FIG. 29B, 38L; [0214], source strap rails 38; [0234], continuous source strap layer 38L ) sacrificial material ( Yu, Abstract, sacrificial semiconductor pedestals can be formed in source-level memory openings prior to formation of a vertically alternating stack of insulating layers and sacrificial material layers ) and the bottom semiconductive material ( Yu, FIG. 29B, top portion of 112; [0152], source semiconductor layer 112 ), and removing the remaining portion of the spacer ( Yu, FIG. 27B, FIG. 28; the portion of 115 which contacts 39 in FIG. 27B is removed in FIG. 28; [0232], second dielectric liner 115 ).
Response to Arguments
Applicant’s argument for claim 1 (currently amended): page 8, line 5, cited “ The Office Action dated January 7, 2026, does not identify a "top semiconductive material" of Yu, instead arguing that a person of ordinary skill in the art would modify other structures of Yu to make obvious the recited "top semiconductive material." ”.
Examiner’s response: First, “ top semiconductive material ” is mapped by “ continuous source strap layer 38L ” of Yu, please refer to the Claim Rejections - 35 USC § 103 for claim 1 in this office action, cited
“ sidewalls of the top semiconductive material comprising:
at least one first step ( Yu, FIG. 29B, top portion of 38L; [0234], continuous source strap layer 38L ); and
at least one second step ( Yu, FIG. 29B, bottom portion of 38L; [0234], continuous source strap layer 38L ) ( Yu, FIG. 29B, the bulging portion and the non-bulging portion in 38L, from non-bulging to bulging portion is one step, from bulging portion to non-bulging portion is another step; also there are left side and right side, which doubles the number of steps ); ”.
Second, a person of ordinary skill in the art would modify the teachings in Yu to make obvious for " A top semiconductive material adjacent to the source contact and not in direct contact with the channel material ", not " top semiconductive material ", please refer to the Claim Rejections - 35 USC § 103 for claim 1 in this office action, cited
“ Yu did not explicitly disclose:
A top semiconductive material adjacent to the source contact and not in direct contact with the channel material;
However, Yu disclosed:
A source semiconductor layer 112 and a second sidewall 39S2 adjacent to source strap layer 38L / source strap rails 38, and not in direct contact with the channels 60, and the source semiconductor layer 112 is adjacent to the bulging portion, as shown in FIG. 24D, FIG. 26B, FIG. 32D, FIG. 85, FIG. 86A;
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yu ( FIG. 29B, top portion of 38L, adjacent to the bulging portion; [0234], continuous source strap layer 38L ), to incorporate the teachings of Yu ( A source semiconductor layer 112 and a second sidewall 39S2 adjacent to source strap layer 38L / source strap rails 38, and not in direct contact with the channels 60, and the source semiconductor layer 112 is adjacent to the bulging portion, as shown in FIG. 24D, FIG. 26B, FIG. 32D, FIG. 85, FIG. 86A ), to implement that a top semiconductive material ( i.e. top portion of 38L is replaced by source semiconductor layer 112 and second sidewall 39S2 ) adjacent to the source contact ( i.e. bottom portion of 38L ) and not in direct contact with the channel material. Doing so would provide a specific design for the source contact in direct contact with channel material in semiconductor NAND / Flash memory which has the stepped pillar region / bulging portion, and therefore the performance of source contact can be improved. ”.
Applicant’s argument for claim 1 (currently amended): page 9, line 11 from bottom, cited “ In other words, the Office asserts that a person of ordinary skill in the art, having the disclosure of Yu and nothing else (there is no other basis for the replacement cited), would elect to modify the "continuous source strap layer 38L" such that a top portion of the "continuous source strap layer 38L" would be converted to a "top semiconductive material." ” … page 10, line 12, cited “ Further, there is nothing in Yu that indicates that a conversion of a portion of the "continuous source strap layer 38L" is even possible. Absent a motivation to make the proposed modification to Yu along with a reasonable expectation that such modification is possible, a person of ordinary skill in the art would not make the modification proposed by the Office. ”.
Examiner’s response: the basis or motivation for obvious is explained in the last paragraph in claim 1, as cited above. More specifically, source strap layer 38L and source semiconductor layer 112 are both source region, therefore, to duplicate / rearrange / combine the structures of 38L and 112 and to make variation structures for source region would be obvious.
Applicant’s argument for claim 5 (currently amended): page 11, line 4 from bottom, cited “ it also shows a good majority of that portion of the pillar structure filled with "dielectric cores 62" which are not "channel material." Thus, those portions of Yu in the alleged "second step of the stepped pillar region" are filled with both "semiconductor channel 60" and "dielectric cores 62" in such a manner that Yu fails to teach or suggest "wherein the channel material...substantially fills the second step of the stepped pillar region" as recited in claim 5. ”.
Examiner’s response: First, portion of the pillar structure filled with "dielectric cores 62" which are not "channel material" in Yui FIG. 29B is a well-known and necessary structure for NAND / Flash memory, just like the pillar structure filled with "dielectric cores 150" which are not "channel material" in specification FIG. 1A; if "dielectric cores 62" would make Yu fails to teach or suggest "wherein the channel material...substantially fills the second step of the stepped pillar region", then "dielectric cores 62" would make the applicant fails to teach or suggest "wherein the channel material...substantially fills the second step of the stepped pillar region" as well. Second, "dielectric cores 62" does not make Yu fail to teach or suggest "wherein the channel material...substantially fills the second step of the stepped pillar region", because the limitation is “ substantially fills ”, which does not exclude the existence of "dielectric cores 62".
Applicant’s argument for claim 10 (currently amended): page 12, line 8, cited “ Nowhere in Yu is there any description, illustrations, teaching, or reference to "sloped sidewalls" in the pillar region. ”.
Examiner’s response: please refer to the Claim Rejections - 35 USC § 103 for claim 10 in this office action, cited “ sloped sidewalls ( Yu, FIG. 29B, the bulging portion and the non-bulging portion in 38L, from non-bulging to bulging portion is one step which has a sloped sidewall, from bulging portion to non-bulging portion is another step which has another sloped sidewall; also there are left side and right side, which doubles the number of steps or sloped side walls ). ”.
Applicant’s argument for claim 13 (original): page 12, line 6 from bottom, cited “ Claim 13 depends from claim 1 and also recites, in part, "wherein a thickness of the channel material in direct contact with the source contact is greater than a thickness of the channel material in the cell region." Yu does not teach or suggest such recitations and therefore fails to make obvious claim 13. ”.
Examiner’s response: please refer to the Claim Rejections - 35 USC § 103 for claim 13 in this office action, cited “ wherein a thickness of the channel material ( Yu, FIG. 86A, 60; FIG. 29A, 38; FIG. 29B, 60 ; [0200], semiconductor channels 60; especially the bulging portion in 38L ) in direct contact with the source contact ( Yu, FIG. 86A, 38; FIG. 29A, 38; FIG. 29B, 38L; [0214], source strap rails 38; [0234], continuous source strap layer 38L ) is greater than a thickness of the channel material ( Yu, FIG. 86A, 60; FIG. 29A, 38; FIG. 29B, 60 ; [0200], semiconductor channels 60 ) in the cell region ( Yu, FIG. 29B, portions above 38L, including 46, 132, 232, 332 ). ”; in other words, claim 13 is mapped by Yu because of the bulging portion in 38L.
Applicant’s argument for claim 14 (Previously Presented): page 13, line 7 from bottom, cited “ Absent further teaching, we do not know what the thickness is adjacent to the "tiers" or the "source contact." In addition, the drawings lend no further support to the rejection. Absent a disclosure by Yu specifically stating that a thickness of the "channel material laterally adjacent to the tiers is less than the thickness...laterally adjacent to the source contact," the rejection of claim 14 under 35 U.S.C. § 103 is not supported. ”.
Examiner’s response: please refer to the Claim Rejections - 35 USC § 103 for claim 14 in this office action, cited “ … wherein a thickness of the channel material ( Yu, FIG. 86A, 60; FIG. 29A, 38; FIG. 29B, 60 ; [0200], semiconductor channels 60 ) laterally adjacent to the tiers ( conductive materials ( Yu, FIG. 29B, conductive layers 46 ) and dielectric materials ( Yu, FIG. 29B, 132, 232, 332; first insulating layers 132; intermediate insulating layers 232; N-th insulating layers 332 ) ) is less than the thickness of the channel material ( Yu, FIG. 86A, 60; FIG. 29A, 38; FIG. 29B, 60 ; [0200], semiconductor channels 60 ) laterally adjacent to the source contact ( Yu, FIG. 86A, 38; FIG. 29A, 38; FIG. 29B, 38L; [0214], source strap rails 38; [0234], continuous source strap layer 38L ); … ”; in other words, claim 14 is mapped by Yu because of the bulging portion in 38L.
Applicant’s argument for claim 19 (Previously Presented): page 14, line 4 from bottom, cited “ Independent claim 19 recites "a method of forming an electronic device," including, in part, "removing...a portion of the top semiconductive material to form two or more stepped openings in the top semiconductive material." Yu at least fails to teach or suggest this element in the recited method. ”.
Examiner’s response: please refer to the Claim Rejections - 35 USC § 103 for claim 19 in this office action, cited “ removing … a portion of the top semiconductive material ( Yu, FIG. 29B, top portion of 38L; [0234], continuous source strap layer 38L ) to form two or more stepped openings in the top semiconductive material ( Yu, FIG. 29B, the bulging portion and the non-bulging portion in 38L, from non-bulging to bulging portion is one step, from bulging portion to non-bulging portion is another step; also there are left side and right side, which doubles the number of step openings ); …”; in other words, claim 19 is mapped by Yu because of the bulging portion and the non-bulging portion in 38L.
Applicant’s argument for claim 21 (Currently Amended): page 15, line 7 from bottom, cited “ Yu does not disclose a process including "etching a slot in the top semiconductive material, forming a spacer adjacent to the slot, etching an additional slot through the spacer" as recited in amended claim 21. ”.
Examiner’s response: please refer to the Claim Rejections - 35 USC § 103 for claim 21 in this office action, cited “ … etching a slot ( Yu, FIG. 27B, 39; [0230], source-level memory openings 39 ) in the top semiconductive material ( Yu, FIG. 29B, top portion of 38L; [0234], continuous source strap layer 38L ), forming a spacer ( Yu, FIG. 27B, 115; [0232], second dielectric liner 115 ) adjacent to the slot, etching an additional slot ( Yu, FIG. 28, 39, wider and deeper than 39 in FIG. 27B; [0230], source-level memory openings 39 ) through the spacer ( Yu, FIG. 28, 115; [0232], second dielectric liner 115 ) … ”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
Prosecution Insights