Prosecution Insights
Last updated: October 26, 2026
Application No. 17/898,107

METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS

Non-Final OA §102§103
Filed
Aug 29, 2022
Examiner
TRAN, TONY
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Micron Technology Inc.
OA Round
5 (Non-Final)
70%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 70% — above average
70%
Career Allowance Rate
621 granted / 884 resolved
+2.2% vs TC avg
Strong +33% interview lift
Without
With
+33.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
50 currently pending
Career history
937
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
60.5%
+20.5% vs TC avg
§102
33.3%
-6.7% vs TC avg
§112
3.7%
-36.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 884 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/22/2026 has been entered. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1 and 5-8 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by MATSUNO (Pub. No.: US 2023/0275026). PNG media_image1.png 694 1170 media_image1.png Greyscale Re claim 1, MATSUNO, FIG. 17B [as shown above] teaches a microelectronic device, comprising: a stack structure comprising vertically alternating conductive structures (46) and insulative structures (32) arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulative structures; a staircase structure (134/146/144, ¶ [0139]) having steps comprising edges of at least some of the tiers of the stack structure, the stack structure comprising sidewalls horizontally bounding the staircase structure and extending upward from the steps of the staircase structure; a liner material (134) on the steps of the staircase structure and the sidewalls of the stack structure, the liner material comprising horizontally extending portions on the steps of the staircase structure and vertically extending portions on the sidewalls of the stack structure; an etch stop structure [ESL] extending continuously in a first horizontal direction [FHD] and having a smaller width than the steps in a second horizontal direction [SHD] orthogonal to the first horizontal direction; and conductive contact structures (85/86, FIG. 19A, [0163]) vertically extending through the etch stop structure [ESL] and the liner material (134) and to the conductive structures (46, FIG. 19A) of the stack structure, the conductive contact structures (85/86) in direct contact with the etch stop structure [ESL]. Re claim 5, MATSUNO, FIG. 19A teaches the microelectronic device of claim 1, wherein the each conductive contact structure (85/86) is substantially horizontally surrounded by the etch stop structure (144). Re claim 6, MATSUNO, FIG. 19A teaches the microelectronic device of claim 1, wherein the etch stop structure (144) comprises a strip of material spanning multiple steps of the staircase structure in the first horizontal direction. Re claim 7, MATSUNO, FIG. 12C [as shown below] teaches the microelectronic device of claim 1, wherein the etch stop structure (144) is spaced apart from the vertically extending portions of the liner material (134) in the second horizontal direction by at least some distance [SHD]. Re claim 8, MATSUNO, FIG. 19A teaches the microelectronic device of claim 1, wherein the liner material comprises a dielectric oxide material (134, [0085]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2-4 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over MATSUNO in view of Haratipour (Pub. No.: US 2024/0373644). Re claim 2-3, MATSUNO teaches all the limitation of claim 1. MATSUNO fails to teach the limitation of claims 2-3. Haratipour teaches wherein the etch stop structure comprises a doped nitride material; and wherein the doped nitride material comprises a carbon-doped nitride material (310/314/318, FIG. 3, [0103]). It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of preventing the electron migration as taught by Haratipour, [0103]. Re claim 4, in the combination, Haratipour teaches the microelectronic device of claim 1, wherein the etch stop structure comprises a substantially undoped dielectric material, the substantially undoped dielectric material comprising a dopant-free nitride material (silicon nitride, [0103]). Re claim 9, in the combination, Haratipour teaches wherein only upper regions of the etch stop structure (outermost layer 144, FIG. 17B) is doped with a chemical species. Response to Arguments Applicant's arguments filed 07/22/2026 have been fully considered but they are not persuasive because it had some level of resist along the edge when etching down to form the opening 75C as shown above. Furthermore, it is subjected to a new ground of rejection because the etch stop layer is the lower 144 as shown in FIG. 17B above. For the above reasons, it is believed that the rejections should be sustained. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TONY TRAN/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Show 6 earlier events
Jan 22, 2026
Response after Non-Final Action
Feb 17, 2026
Non-Final Rejection mailed — §102, §103
Mar 13, 2026
Response Filed
Apr 20, 2026
Final Rejection mailed — §102, §103
Jun 12, 2026
Response after Non-Final Action
Jul 22, 2026
Request for Continued Examination
Jul 24, 2026
Response after Non-Final Action
Oct 16, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
70%
Grant Probability
99%
With Interview (+33.3%)
2y 9m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 884 resolved cases by this examiner. Grant probability derived from career allowance rate.

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