DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed 05/31/2026 has been entered. Claims 1-20 remain pending in the application.
Claim Objections
Claims 1-20 are objected to because of the following informalities:
Claim 1 recites the limitations “output circuits” in line 9 and “exponents” in line 10, but would have better consistent with other claim elements and clarity if recited as “a plurality of output circuits” and “a plurality of exponents”. Claims 2-13 inherit the same deficiency by reasons of dependence and all other instances would necessitate the change to “the plurality of output circuits” and “the plurality of exponents”;
Claim 14 recites the limitations “output circuits” in line 12 and “exponents” in line 13, but would have better consistent with other claim elements and clarity if recited as “a plurality of output circuits” and “a plurality of exponents”. Claims 15-17 inherit the same deficiency by reasons of dependence and all other instances would necessitate the change to “the plurality of output circuits” and “the plurality of exponents”;
Claim 18 recites the limitations “output circuits” in line 7 and “exponents” in line 8, but would have better consistent with other claim elements and clarity if recited as “a plurality of output circuits” and “a plurality of exponents”. Claims 19-20 inherit the same deficiency by reasons of dependence and all other instances would necessitate the change to “the plurality of output circuits” and “the plurality of exponents”.
Appropriate correction is required.
Claim Construction
Regarding claim 1, the preamble is given patentable weight. Claims 7, 11, and 13 contains the limitation “the device” in the body, which is referring to the limitations as recited in the preamble of claim 1. A skilled person in the art reading the claims would consider the claim in view of the body and preamble, and identify them limited to the technological environment of a device as recited in claim 1. The body of the claim depends on the preamble for completeness, and gives life, meaning, and vitality to this claim. Therefore, the preamble of claim 1 should be afforded patentable weight.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding claim 1, under the Alice Framework Step 1 analysis, the claim falls within the four statutory categories of patentable subject matter: an apparatus.
Under the Alice Framework Step 2A Prong 1 analysis, claim 1 recites Mathematical Concepts and/or Mental Processes. The claim recites Mathematical Calculations, which is specifically identified as an exemplar in the Mathematical Concepts grouping of abstract ideas, and/or recites Evaluations, which is specifically identified as an exemplar in the Mental Processes grouping of abstract ideas:
“A device, comprising: a plurality of integer multiplier circuits;
a multiplexer circuit configured to provide portions of mantissas of a set of first data elements having a floating-point data type and portions of mantissas of a set of second data elements having the floating-point data type to respective integer multiplier circuits of the plurality of integer multiplier circuits, wherein each integer multiplier circuit is configured to multiply a respective portion of the mantissa of a first data element by a respective portion of the mantissa of a second data element to generate a partial product; and
output circuits configured to generate an output data element based on the partial products generated by the plurality of integer multiplier circuits and exponents of the set of first data elements and of the set of second data elements,
wherein the multiplexer circuit is further configured to bypass providing least-significant portions of the mantissas of the set of first data elements to integer multiplier circuits of the plurality of integer multiplier circuits for multiplication with least-significant portions of the mantissas of the set of second data elements.”
See specification ([0026], [0041-0042]) describing to provide. See specification ([0025-0026], [0041-0042]) describing to multiply. See specification ([0031], [0035], [0059], [0065]) describing to generate. See specification ([0045], [0055], [0059], [0071]) describing to bypass. The steps of “to provide”, “to multiply”, “to generate”, and “to bypass” are processes that under the broadest reasonable interpretation, cover performance of the limitations in the mind. That is, other than reciting “a device”, “a plurality of integer multiplier circuits”, “a multiplexer circuit”, and “output circuits”, nothing in the claim element precludes the steps from practically being performed in the human mind. For example, but for the “a device”, “a plurality of integer multiplier circuits”, “a multiplexer circuit”, and “output circuits” language, the claim encompasses manually providing portions of the data for multiplication and generating output data value based on that result, of which would be possible with aid of pen and paper, as shown in at least Fig. 3, 4, and 5A-B and described in the above paragraphs. For these reasons, the claim recites Mathematical Concepts and/or Mental Processes.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: a device, a plurality of integer multiplier circuits, a multiplexer circuit, and output circuits. The device, the plurality of integer multiplier circuits, the multiplexer circuit, and output circuits are recited at a high level of generality, and are examples of generic computing elements, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). Further, it is recited at a high-level of generality such that it amounts to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea or merely reciting the words "apply it" (or an equivalent) with the judicial exception. (See MPEP2106.05(f): Mere Instructions to Apply an Exception). Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B Analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 Analysis, the claim recites limitations described above as recited at a high level of generality merely results in "apply it" on a computer (or an equivalent) with the judicial exception. Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 1 is ineligible.
Claims 2 and 4 merely further limit the mathematical concepts and/or mental processes. Claims 2 and 4 do not recite any new additional elements that would necessitate analysis under Alice Framework Step 2A Prong 2 and Alice Framework Step 2B Analysis.
Under the Alice Framework Step 2A Prong 1 analysis, claim 3 recites Mathematical Concepts and/or Mental Processes. The claim recites Mathematical Calculations, which is specifically identified as an exemplar in the Mathematical Concepts grouping of abstract ideas, and/or recites Evaluations, which is specifically identified as an exemplar in the Mental Processes grouping of abstract ideas:
“wherein the plurality of integer multiplier circuits comprises:
a first set of integer multiplier circuits having a first bit size; and
a second set of integer multiplier circuits having a second bit size different from the first bit size.”
See specification ([0012], [0026], [0030], [0060-0061]) describing a first bit size and second bit size. The steps of “having a first bit size” and “having a second bit size different from the first bit size” are processes that under the broadest reasonable interpretation, cover performance of the limitations in the mind. That is, other than reciting “the plurality of integer multiplier circuits”, “a first set of integer multiplier circuits”, and “a second set of integer multiplier circuits”, nothing in the claim element precludes the steps from practically being performed in the human mind. For example, but for the “the plurality of integer multiplier circuits”, “a first set of integer multiplier circuits”, and “a second set of integer multiplier circuits” language, the claim encompasses manually assessing a first bit size and a second bit size different from the first, of which would be possible with aid of pen and paper, as shown in at least Fig. 4, and 5A-B and described in the above paragraphs. For these reasons, the claim recites Mathematical Concepts and/or Mental Processes.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: the plurality of integer multiplier circuits, a first set of integer multiplier circuits, and a second set of integer multiplier circuits. The plurality of integer multiplier circuits, a first set of integer multiplier circuits, and a second set of integer multiplier circuits are recited at a high level of generality, and are examples of generic computing elements, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). Further, it is recited at a high-level of generality such that it amounts to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea or merely reciting the words "apply it" (or an equivalent) with the judicial exception. (See MPEP2106.05(f): Mere Instructions to Apply an Exception). Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B Analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 Analysis, the claim recites limitations described above as recited at a high level of generality merely results in "apply it" on a computer (or an equivalent) with the judicial exception. Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 3 is ineligible.
Under the Alice Framework Step 2A Prong 1 analysis, claim 5 recites Mathematical Concepts and/or Mental Processes. The claim recites Mathematical Calculations, which is specifically identified as an exemplar in the Mathematical Concepts grouping of abstract ideas, and/or recites Evaluations, which is specifically identified as an exemplar in the Mental Processes grouping of abstract ideas:
“wherein the bit size of the first set of integer multiplier circuits is eleven bits and the bit size of the second set of integer multiplier circuits is eight bits.”
See specification ([0026], [0042-0044], [0053-0054], [0060-0061]) describing a first bit size is eleven bits and second bit size is eight bits. The steps of “the bit size is eleven bits” and “the bit size is eight bits” are processes that under the broadest reasonable interpretation, cover performance of the limitations in the mind. That is, other than reciting “the first set of integer multiplier circuits” and “the second set of integer multiplier circuits”, nothing in the claim element precludes the steps from practically being performed in the human mind. For example, but for the “the first set of integer multiplier circuits” and “the second set of integer multiplier circuits” language, the claim encompasses manually assessing the first bit size as 11 bits and the second bit size as 8 bits, of which would be possible with aid of pen and paper, as shown in at least Fig. 4, and 5A-B and described in the above paragraphs. For these reasons, the claim recites Mathematical Concepts and/or Mental Processes.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: the first set of integer multiplier circuits and the second set of integer multiplier circuits. The first set of integer multiplier circuits and the second set of integer multiplier circuits are recited at a high level of generality, and are examples of generic computing elements, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). Further, it is recited at a high-level of generality such that it amounts to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea or merely reciting the words "apply it" (or an equivalent) with the judicial exception. (See MPEP2106.05(f): Mere Instructions to Apply an Exception). Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B Analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 Analysis, the claim recites limitations described above as recited at a high level of generality merely results in "apply it" on a computer (or an equivalent) with the judicial exception. Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 5 is ineligible.
Under the Alice Framework Step 2A Prong 1 analysis, claim 6 recites Mathematical Concepts and/or Mental Processes. The claim recites Mathematical Calculations, which is specifically identified as an exemplar in the Mathematical Concepts grouping of abstract ideas, and/or recites Evaluations, which is specifically identified as an exemplar in the Mental Processes grouping of abstract ideas:
“wherein the output circuits comprise:
a first shift circuit configured to shift bits of the partial products based on the exponents of the set of first data elements and of the set of second data elements;
a first integer adder circuit configured to add the shifted partial products to generate a sum; and
a composition circuit configured to generate the output data element based on the sum generated by the first integer adder circuit.”
See specification ([0047]) describing to shift. See specification ([0048]) describing to add. See specification ([0051]) describing to generate. The steps of “to shift”, “to add” and “to generate” are processes that under the broadest reasonable interpretation, cover performance of the limitations in the mind. That is, other than reciting “the output circuits”, “a first shift circuit”, “a first integer adder circuit”, and “a composition circuit”, nothing in the claim element precludes the steps from practically being performed in the human mind. For example, but for the “the output circuits”, “a first shift circuit”, “a first integer adder circuit”, and “a composition circuit” language, the claim encompasses manually shifting the partial products, adding, and then outputting the result, of which would be possible with aid of pen and paper, as shown in at least Fig. 4, and 5A-B and described in the above paragraphs. For these reasons, the claim recites Mathematical Concepts and/or Mental Processes.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: the output circuits, the first shift circuit, the first integer adder circuit, and the composition circuit. The output circuits, the first shift circuit, the first integer adder circuit, and the composition circuit are recited at a high level of generality, and are examples of generic computing elements, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). Further, it is recited at a high-level of generality such that it amounts to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea or merely reciting the words "apply it" (or an equivalent) with the judicial exception. (See MPEP2106.05(f): Mere Instructions to Apply an Exception). Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B Analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 Analysis, the claim recites limitations described above as recited at a high level of generality merely results in "apply it" on a computer (or an equivalent) with the judicial exception. Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 6 is ineligible.
Under the Alice Framework Step 2A Prong 1 analysis, claim 7 recites Mathematical Concepts and/or Mental Processes. The claim recites Mathematical Calculations, which is specifically identified as an exemplar in the Mathematical Concepts grouping of abstract ideas, and/or recites Evaluations, which is specifically identified as an exemplar in the Mental Processes grouping of abstract ideas:
“wherein the set of first data elements are paired with the set of second data elements, respectively, to form a plurality of data-element pairs,
wherein the device further comprises an exponent circuit configured to:
add the exponents of the first data element and the second data element for each data-element pair to generate a respective exponent sum;
determine a maximum exponent sum from the respective exponent sums;
for each data-element pair, determine a difference between the maximum exponent sum and the respective exponent sum,
wherein the first shift circuit is configured to shift the bits of the partial products based on the respective differences between the maximum exponent sum and the respective exponent sums, and
wherein the output data element is generated based on the maximum exponent sum.”
See specification ([0063]) describing to form. See specification ([0027]) describing to add. See specification ([0027]) describing to determine. See specification ([0048]) describing to shift. See specification ([0051]) describing is generated. The steps of “to form”, “to add”, “to determine”, “to shift”, and “is generated” are processes that under the broadest reasonable interpretation, cover performance of the limitations in the mind. That is, other than reciting “the device”, “an exponent circuit”, and “the first shift circuit”, nothing in the claim element precludes the steps from practically being performed in the human mind. For example, but for the “the device”, “an exponent circuit”, and “the first shift circuit” language, the claim encompasses manually pairing, adding exponent from the pairs, determining the largest exponent, determining the differences between the largest exponent and a respective exponent, shifting based on the difference, and then outputting the result, of which would be possible with aid of pen and paper, as shown in at least Fig. 4, and 5A-B and described in the above paragraphs. For these reasons, the claim recites Mathematical Concepts and/or Mental Processes.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: the device, the exponent circuit, and the first shift circuit. The exponent circuit and the first shift circuit are recited at a high level of generality, and are examples of generic computing elements, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). Further, it is recited at a high-level of generality such that it amounts to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea or merely reciting the words "apply it" (or an equivalent) with the judicial exception. (See MPEP2106.05(f): Mere Instructions to Apply an Exception). Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B Analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 Analysis, the claim recites limitations described above as recited at a high level of generality merely results in "apply it" on a computer (or an equivalent) with the judicial exception. Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 7 is ineligible.
Under the Alice Framework Step 2A Prong 1 analysis, claim 8 recites Mathematical Concepts and/or Mental Processes. The claim recites Mathematical Calculations, which is specifically identified as an exemplar in the Mathematical Concepts grouping of abstract ideas, and/or recites Evaluations, which is specifically identified as an exemplar in the Mental Processes grouping of abstract ideas:
“a sign circuit configured to determine an output sign for each data-element pair based on sign bits of the respective first data elements and second data elements,
wherein the output circuits further comprise a conversion circuit configured to generate two's complements of the shifted partial products based on the respective output signs prior to being added by the first integer adder circuit.”
See specification ([0025], [0064]) describing to determine. See specification ([0049]) describing to generate. The steps of “to determine” and “to generate” are processes that under the broadest reasonable interpretation, cover performance of the limitations in the mind. That is, other than reciting “a sign circuit”, “the output circuits”, “a conversion circuit”, and “the first integer adder circuit”, nothing in the claim element precludes the steps from practically being performed in the human mind. For example, but for the “a sign circuit”, “the output circuits”, “a conversion circuit”, and “the first integer adder circuit” language, the claim encompasses manually determining an output sign, generating two’s complements, and then adding, of which would be possible with aid of pen and paper, as shown in at least Fig. 4, and 5A-B and described in the above paragraphs. For these reasons, the claim recites Mathematical Concepts and/or Mental Processes.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: the sign circuit, the outputs circuits, the conversion circuit, and the first integer adder circuit. The sign circuit, the outputs circuits, the conversion circuit, and the first integer adder circuit are recited at a high level of generality, and are examples of generic computing elements, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). Further, it is recited at a high-level of generality such that it amounts to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea or merely reciting the words "apply it" (or an equivalent) with the judicial exception. (See MPEP2106.05(f): Mere Instructions to Apply an Exception). Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B Analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 Analysis, the claim recites limitations described above as recited at a high level of generality merely results in "apply it" on a computer (or an equivalent) with the judicial exception. Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 8 is ineligible.
Under the Alice Framework Step 2A Prong 1 analysis, claim 9 recites Mathematical Concepts and/or Mental Processes. The claim recites Mathematical Calculations, which is specifically identified as an exemplar in the Mathematical Concepts grouping of abstract ideas, and/or recites Evaluations, which is specifically identified as an exemplar in the Mental Processes grouping of abstract ideas:
“the composition circuit is further configured to:
convert the sum generated by the first integer adder circuit from two's complement to signed-magnitude format; and
round the converted sum to a predetermined bit length,
wherein a sign bit of the output data element is based on the converted sum, an exponent of the output data element is based on the determined maximum exponent sum, and a mantissa of the output data element is based on the rounded sum.”
See specification ([0034-0035]) describing to convert. See specification ([0036]) describing to round. See specification ([0035-0037]) describing a sign bit, exponent, and mantissa. The steps of “to convert”, “to round”, and “sign bit, exponent, and mantissa” are processes that under the broadest reasonable interpretation, cover performance of the limitations in the mind. That is, other than reciting “the composition circuit” and “the first integer adder circuit”, nothing in the claim element precludes the steps from practically being performed in the human mind. For example, but for the “the composition circuit” and “the first integer adder circuit” language, the claim encompasses manually converting to signed-magnitude, rounding, and basing the sign bit based on the converted sum, exponent based on the largest exponent sum, and mantissa based on the rounded sum, of which would be possible with aid of pen and paper, as shown in at least Fig. 4, and 5A-B and described in the above paragraphs. For these reasons, the claim recites Mathematical Concepts and/or Mental Processes.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: the composition circuit and the first integer adder circuit. The composition circuit and the first integer adder circuit are recited at a high level of generality, and are examples of generic computing elements, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). Further, it is recited at a high-level of generality such that it amounts to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea or merely reciting the words "apply it" (or an equivalent) with the judicial exception. (See MPEP2106.05(f): Mere Instructions to Apply an Exception). Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B Analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 Analysis, the claim recites limitations described above as recited at a high level of generality merely results in "apply it" on a computer (or an equivalent) with the judicial exception. Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 9 is ineligible.
Under the Alice Framework Step 2A Prong 1 analysis, claim 10 recites Mathematical Concepts and/or Mental Processes. The claim recites Mathematical Calculations, which is specifically identified as an exemplar in the Mathematical Concepts grouping of abstract ideas, and/or recites Evaluations, which is specifically identified as an exemplar in the Mental Processes grouping of abstract ideas:
“the composition circuit is further configured to:
normalize the rounded sum; and
adjust the maximum exponent sum based on the normalization,
wherein the exponent of the output data element is based on the adjusted maximum exponent sum and the mantissa of the output data element is based on the normalized sum.”
See specification ([0036]) describing to normalize. See specification ([0037], [0066]) describing to adjust. See specification ([0027], [0037]) describing the exponent. The steps of “to normalize”, “to adjust”, and “exponent” are processes that under the broadest reasonable interpretation, cover performance of the limitations in the mind. That is, other than reciting “the composition circuit”, nothing in the claim element precludes the steps from practically being performed in the human mind. For example, but for the “the composition circuit” language, the claim encompasses manually normalizing, adjusting based on the normalization, and basing the exponent on the adjusted and normalized values, of which would be possible with aid of pen and paper, as shown in at least Fig. 4, and 5A-B and described in the above paragraphs. For these reasons, the claim recites Mathematical Concepts and/or Mental Processes.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: the composition circuit and the first integer adder circuit. The composition circuit and the first integer adder circuit are recited at a high level of generality, and are examples of generic computing elements, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). Further, it is recited at a high-level of generality such that it amounts to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea or merely reciting the words "apply it" (or an equivalent) with the judicial exception. (See MPEP2106.05(f): Mere Instructions to Apply an Exception). Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B Analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 Analysis, the claim recites limitations described above as recited at a high level of generality merely results in "apply it" on a computer (or an equivalent) with the judicial exception. Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 10 is ineligible.
Under the Alice Framework Step 2A Prong 1 analysis, claim 11 recites Mathematical Concepts and/or Mental Processes. The claim recites Mathematical Calculations, which is specifically identified as an exemplar in the Mathematical Concepts grouping of abstract ideas, and/or recites Evaluations, which is specifically identified as an exemplar in the Mental Processes grouping of abstract ideas:
“the multiplexer circuit is further configured to:
provide different combinations of the portions of the mantissas of the set of first data elements and of the set of second data elements to the plurality of integer multiplier circuits during different respective cycles of the device.”
See specification ([0022], [0051]) describing to provide. The step of “to provide” is a process that under the broadest reasonable interpretation, cover performance of the limitations in the mind. That is, other than reciting “the multiplexer circuit”, “the plurality of integer multiplier circuits”, and “different respective cycles of the device”, nothing in the claim element precludes the steps from practically being performed in the human mind. For example, but for the “the multiplexer circuit”, “the plurality of integer multiplier circuits”, and “different respective cycles of the device” language, the claim encompasses manually providing the different combinations, of which would be possible with aid of pen and paper, as shown in at least Fig. 4, and 5A-B and described in the above paragraphs. For these reasons, the claim recites Mathematical Concepts and/or Mental Processes.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: the multiplexer circuit, the plurality of integer multiplier circuits, and different respective cycles of the device. The multiplexer circuit and plurality of integer multiplier circuit are recited at a high level of generality, and are examples of generic computing elements, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). Further, it is recited at a high-level of generality such that it amounts to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea or merely reciting the words "apply it" (or an equivalent) with the judicial exception. (See MPEP2106.05(f): Mere Instructions to Apply an Exception). The “different respective cycles of the device” limitation is an example of insignificant extra-solution activity, mere data gathering (see MPEP 2106.05(g): Insignificant Extra-Solution Activity). Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B Analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 Analysis, the claim recites limitations described above as recited at a high level of generality merely results in "apply it" on a computer (or an equivalent) with the judicial exception. The limitation described above as an insignificant extra-solution activity are also well-understood, routine, or conventional (for ‘cycles’: see Patterson, David A., and John L. Hennessy. Computer Organization and Design: The Hardware/Software Interface (5th Edition). Morgan Kaufmann, 2013. (hereinafter “Patterson”), p. 33-38). Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 11 is ineligible.
Under the Alice Framework Step 2A Prong 1 analysis, claim 12 recites Mathematical Concepts and/or Mental Processes. The claim recites Mathematical Calculations, which is specifically identified as an exemplar in the Mathematical Concepts grouping of abstract ideas, and/or recites Evaluations, which is specifically identified as an exemplar in the Mental Processes grouping of abstract ideas:
“a second shift circuit configured to shift bits of the partial products generated by the different respective integer multiplier circuits based on a bit position of the portion of the mantissa of the first data element multiplied to generate the respective partial products; and
a second integer adder circuit configured to add the shifted partial products corresponding to each of the first data elements to generate respective partial sums,
wherein the first shift circuit is configured to shift the bits of the partial sums based on the determined difference between the maximum exponent sum and the respective exponent sum of the corresponding data-element pair,
wherein the conversion circuit is configured to generate two's complements of the shifted partial sums, and
wherein the first integer adder circuit is configured to add the shifted partial sums to generate the sum.”
See specification ([0047]) describing to shift. See specification ([0048]) describing to add. See specification ([0048]) describing to shift. See specification ([0049]) describing to generate. See specification ([0049]) describing to add. The steps of “to shift”, “to add”, “to shift”, “to generate”, and “to add” are processes that under the broadest reasonable interpretation, cover performance of the limitations in the mind. That is, other than reciting “a second shift circuit”, “a second integer adder”, “the first shift circuit”, “the conversion circuit”, and “the first integer adder circuit”, nothing in the claim element precludes the steps from practically being performed in the human mind. For example, but for the “a second shift circuit”, “a second integer adder”, “the first shift circuit”, “the conversion circuit”, and “the first integer adder circuit” language, the claim encompasses manually shifting bits, adding the shifted bits, shifting based on the differences of the exponents, converting to two’s complement, and adding to generate the sum, of which would be possible with aid of pen and paper, as shown in at least Fig. 4, and 5A-B and described in the above paragraphs. For these reasons, the claim recites Mathematical Concepts and/or Mental Processes.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: the second shift circuit, the second integer adder, the first shift circuit, the conversion circuit, and the first integer adder circuit. The second shift circuit, the second integer adder, the first shift circuit, the conversion circuit, and the first integer adder circuit are recited at a high level of generality, and are examples of generic computing elements, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). Further, it is recited at a high-level of generality such that it amounts to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea or merely reciting the words "apply it" (or an equivalent) with the judicial exception. (See MPEP2106.05(f): Mere Instructions to Apply an Exception). Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B Analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 Analysis, the claim recites limitations described above as recited at a high level of generality merely results in "apply it" on a computer (or an equivalent) with the judicial exception. Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 12 is ineligible.
Under the Alice Framework Step 2A Prong 1 analysis, claim 13 recites Mathematical Concepts and/or Mental Processes. The claim recites Mathematical Calculations, which is specifically identified as an exemplar in the Mathematical Concepts grouping of abstract ideas, and/or recites Evaluations, which is specifically identified as an exemplar in the Mental Processes grouping of abstract ideas:
“the output circuits further comprise:
a third shift circuit configured to shift bits of the sum generated by the first integer adder circuit based on a cycle count of the device,
wherein the composition circuit generates the output data element based on the shifted sum.”
See specification ([0022], [0051]) describing to shift. See specification ([0022], [0051]) describing generates. The steps of “to shift” and “generates” are processes that under the broadest reasonable interpretation, cover performance of the limitations in the mind. That is, other than reciting “the output circuits”, “a third shift circuit”, “the first integer adder circuit”, “based on a cycle count of the device”, and “the composition circuit”, nothing in the claim element precludes the steps from practically being performed in the human mind. For example, but for the “the output circuits”, “a third shift circuit”, “the first integer adder circuit”, “based on a cycle count of the device”, and “the composition circuit”, language, the claim encompasses manually shifting the sum and then output the value based on the shifted value, of which would be possible with aid of pen and paper, as shown in at least Fig. 4, and 5A-B and described in the above paragraphs. For these reasons, the claim recites Mathematical Concepts and/or Mental Processes.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: the output circuits, a third shift circuit, the first integer adder circuit, based on a cycle count of the device, and the composition circuit. The output circuits, a third shift circuit, the first integer adder circuit, and the composition circuit are recited at a high level of generality, and are examples of generic computing elements, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). Further, it is recited at a high-level of generality such that it amounts to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea or merely reciting the words "apply it" (or an equivalent) with the judicial exception. (See MPEP2106.05(f): Mere Instructions to Apply an Exception). The “based on a cycle count of the device” limitation is an example of insignificant extra-solution activity, mere data gathering (see MPEP 2106.05(g): Insignificant Extra-Solution Activity). Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B Analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 Analysis, the claim recites limitations described above as recited at a high level of generality merely results in "apply it" on a computer (or an equivalent) with the judicial exception. The limitation described above as an insignificant extra-solution activity are also well-understood, routine, or conventional (for ‘cycle count’: see Patterson, p. 34-37). Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 13 is ineligible.
Claim 14 is directed to a device that performs similar limitations to claim 1. The claim 1 analysis similarly applies to claim 14. Additionally, claim 14 recites the following: each integer multiplier circuit is provided a different pair of portions of mantissa, wherein the pairs of portions of the mantissas do not include a pair comprising a least-significant portion of a mantissa of the set of first data elements and a least-significant portion of a mantissa of the set of second data elements.
Under the Alice Framework Step 1 analysis, the claim falls within the four statutory categories of patentable subject matter: an apparatus.
Under the Alice Framework Step 2A Prong 1 analysis, claim 14 recites Mathematical Concepts and/or Mental Processes. The claim recites Mathematical Calculations, which is specifically identified as an exemplar in the Mathematical Concepts grouping of abstract ideas, and/or recites Evaluations, which is specifically identified as an exemplar in the Mental Processes grouping of abstract ideas:
“each integer multiplier circuit is provided a different pair of portions of mantissa, wherein the pairs of portions of the mantissas do not include a pair comprising a least-significant portion of a mantissa of the set of first data elements and a least-significant portion of a mantissa of the set of second data elements.”
See specification ([0045], [0055], [0068]) describing to provide. The step of “to provide” is a process that under the broadest reasonable interpretation, cover performance of the limitations in the mind. That is, other than reciting “integer multiplier circuit”, nothing in the claim element precludes the steps from practically being performed in the human mind. For example, but for the “ the integer multiplier circuits” language, the claim encompasses manually providing portions of the data by excluding specific portions, of which would be possible with aid of pen and paper, as shown in at least Fig. 4, and 5A-B and described in the above paragraphs. For these reasons, the claim recites Mathematical Concepts and/or Mental Processes.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: integer multiplier circuits. The integer multiplier circuits are recited at a high level of generality, and are examples of generic computing elements, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). Further, it is recited at a high-level of generality such that it amounts to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea or merely reciting the words "apply it" (or an equivalent) with the judicial exception. (See MPEP2106.05(f): Mere Instructions to Apply an Exception). Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B Analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 Analysis, the claim recites limitations described above as recited at a high level of generality merely results in "apply it" on a computer (or an equivalent) with the judicial exception. Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 14 is ineligible.
Claims 15-17 recites similar limitations to those of claims 2-5. The claims 2, 3, 4-5 analysis similarly applies to claims 15, 16, 17, respectively. Claims 15-17 are similarly rejected.
Claim 18 is directed to a device that performs similar limitations to claim 1. The claim 1 analysis similarly applies to claim 18. Additionally, claim 18 recites the following: a controller circuit; an accumulator circuit; and a plurality of multiplication and accumulation (MAC) cells, wherein each of the plurality of MAC cells comprises: input circuits configured to receive; and output circuits provide the output data element to the accumulator circuit, wherein the accumulator circuit is configured to accumulate the output data elements generated by the plurality of MAC cells to generate an output tensor.
Under the Alice Framework Step 1 analysis, the claim falls within the four statutory categories of patentable subject matter: an apparatus.
Under the Alice Framework Step 2A Prong 1 analysis, claim 18 recites Mathematical Concepts and/or Mental Processes. The claim recites Mathematical Calculations, which is specifically identified as an exemplar in the Mathematical Concepts grouping of abstract ideas, and/or recites Evaluations, which is specifically identified as an exemplar in the Mental Processes grouping of abstract ideas:
“a controller circuit; an accumulator circuit; and a plurality of multiplication and accumulation (MAC) cells, wherein each of the plurality of MAC cells comprises: input circuits configured to receive; and output circuits provide the output data element to the accumulator circuit, wherein the accumulator circuit is configured to accumulate the output data elements generated by the plurality of MAC cells to generate an output tensor.”
See specification ([0022], [0039-0041], [0071]) describing to accumulate. The step of “to accumulate” is a process that under the broadest reasonable interpretation, cover performance of the limitations in the mind. That is, other than reciting “a controller circuit”, “an accumulation circuit”, “a plurality of multiplication and accumulation (MAC) cells”, “input circuits configured to receive”, and “output circuits provide the output data element”, nothing in the claim element precludes the steps from practically being performed in the human mind. For example, but for the “a controller circuit”, “an accumulation circuit”, “a plurality of multiplication and accumulation (MAC) cells”, “input circuits configured to receive”, and “output circuits provide the output data element” language, the claim encompasses manually accumulating the output data elements to generate an output tensor, of which would be possible with aid of pen and paper, as shown in at least Fig. 4, and 5A-B and described in the above paragraphs. For these reasons, the claim recites Mathematical Concepts and/or Mental Processes.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: a controller circuit, an accumulation circuit, a plurality of multiplication and accumulation (MAC) cells, input circuits configured to receive, and output circuits provide the output data element. The controller circuit, the accumulation circuit, the plurality of multiplication and accumulation (MAC) cells, input circuits, and output circuits are recited at a high level of generality, and are examples of generic computing elements, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). Further, it is recited at a high-level of generality such that it amounts to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea or merely reciting the words "apply it" (or an equivalent) with the judicial exception. (See MPEP2106.05(f): Mere Instructions to Apply an Exception). The receiving and providing the output data limitations are examples of insignificant extra-solution activity, mere data gathering (see MPEP 2106.05(g): Insignificant Extra-Solution Activity). Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B Analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 Analysis, the claim recites limitations described above as recited at a high level of generality merely results in "apply it" on a computer (or an equivalent) with the judicial exception. The limitation described above as an insignificant extra-solution activity are also well-understood, routine, or conventional (for ‘receiving’ and ‘providing’: see MPEP 2106.05(d)(II): Storing and retrieving information in memory). Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 18 is ineligible.
Claims 19-20 recites similar limitations to those of claims 2, 4-5. The claims 2, 4-5 analysis similarly applies to claims 19 and 20, respectively. Claims 19-20 are similarly rejected.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 6-8, 14-15, 18-19 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US 20210263993 A1 Urbanski et al. (hereinafter “Urbanski”).
Regarding claim 1, Urbanski teaches a device (Fig. 13A-C “1300” [0124]), comprising:
a plurality of integer multiplier circuits (Fig. 13A-B “1334” and other unnumbered multipliers [0132]);
a multiplexer circuit (Fig. 13A-B “1330, 1332” and other unnumbered muxes [0132]) configured to provide portions of mantissas of a set of first data elements having a floating-point data type (Fig. 13A-B “1308” mant. A[0]:A[n] of vector A [0127]) and portions of mantissas of a set of second data elements having the floating-point data type (Fig. 13A-B “1324” mant. B[0]:B[n] of vector B [0127, 0132]) to respective integer multiplier circuits of the plurality of integer multiplier circuits (Fig. 13A-B “1334” multipliers corresponding to “1308” mant. A[0] and “1324” mant. B[0] [0129]), wherein each integer multiplier circuit is configured to multiply a respective portion of the mantissa of a first data element by a respective portion of the mantissa of a second data element ([0131-0132]) to generate a partial product (Fig. 13A-B outputs from “1334” and other unnumbered multipliers [0132] products from each multipliers); and
output circuits (Fig. 13A-C the circuitry following multiplier, and before accumulator “1336, 1342, 1346, 1353, 1351, 1355A, 1357” [0132, 0135, 0138]) configured to generate an output data element (Fig. 13C “1359” [0135]) based on the partial products generated by the plurality of integer multiplier circuits (Fig. 13A-B outputs from “1334” and other unnumbered multipliers [0132] products from each multipliers) and exponents of the set of first data elements (Fig. 13A-B “1314” [0127]) and of the set of second data elements (Fig. 13A-B “1316” [0132]),
wherein the multiplexer circuit is further configured to bypass providing least-significant portions of the mantissas of the set of first data elements (Fig. 13A-B mant. A[n] [0127-0129]) to integer multiplier circuits of the plurality of integer multiplier circuits for multiplication (Fig. 13A-B “1334” and other unnumbered multipliers [0132]) with least-significant portions of the mantissas of the set of second data elements (Fig. 13A-B mant. B[n] [0127-0129]).
Regarding claim 2, the teachings addressed in the claim 1 analysis and rejection
are incorporated, and Urbanski teaches wherein:
a mantissa bit size of the floating-point data type is twenty-four bits ([0124] using the logic given for the 32-bit example (N=32), (N=24) since N can be any value between 0 to N and given the example is 32 is inclusive of N=11 [0129]), and
wherein the portions of the mantissas provided to the plurality of integer multiplier circuits (see claim 1 mapping) comprise the least-significant portions each including eight bits from eight least-significant bit positions of the respective mantissas ([0124] 16-23 element positions input to 1301C), middle portions each including eight bits from eight middle-bit positions of the respective mantissas ([0124] 8-15 element positions input to 1301B), and most-significant portions each including eight bits from eight most-significant bit positions of the respective mantissas ([0124] 0-7 element positions input to 1301A).
Regarding claim 6, the teachings addressed in the claim 1 analysis and rejection
are incorporated, and Urbanski teaches wherein:
the output circuits (see claim 1 mapping) comprise:
a first shift circuit (Fig. 13A-B “1336” [0132-0133]) configured to shift bits of the partial products based on the exponents of the set of first data elements and of the set of second data elements ([0132-0133] shifted based on max exponent “1341” based on exponents “1314” [0127] and “1316” [0132]);
a first integer adder circuit (Fig. 13A-B “1346” [0138]) configured to add the shifted partial products to generate a sum (Fig. 13A-B “1347A-Z” [0138] [0143] single product); and
a composition circuit (Fig. 13C “1303” [0143, 0146]) configured to generate the output data element (Fig. 13C “1359” [0135]) based on the sum generated by the first integer adder circuit ([0143, 0146]).
Regarding claim 7, the teachings addressed in the claim 6 analysis and rejection
are incorporated, and Urbanski teaches wherein:
the set of first data elements are paired with the set of second data elements, respectively, to form a plurality of data-element pairs ([0132]),
wherein the device further comprises an exponent circuit (Fig. 13A-C “1338, 1340, 1353, 1363” [0132], [0135]) configured to:
add the exponents of the first data element and the second data element for each data-element pair to generate a respective exponent sum (Fig. 13A-B “1338” [0132]);
determine a maximum exponent sum from the respective exponent sums (Fig. 13A-B “1341” output from “1340” [0132]); and for each data-element pair, determine a difference between the maximum exponent sum and the respective exponent sum (Fig. 13A-B “1340” [0132], [0134], [0141] comparator circuit),
wherein the first shift circuit is configured to shift the bits of the partial products based on the respective differences between the maximum exponent sum and the respective exponent sums (Fig. 13A-B “1341” to shift registers “1336” [0132]), and wherein the output data element (Fig. 13C “1359” [0135]) is generated based on the maximum exponent sum (Fig. 13A-B “1341” [0132], “1353” [0135]; Fig. 13C “1363” [0135]).
Regarding claim 8, the teachings addressed in the claim 7 analysis and rejection
are incorporated, and Urbanski teaches further comprising:
a sign circuit (Fig. 13A-B “1344” [0134]) configured to determine an output sign (Fig. 13A-B output from “1344” [0134]) for each data-element pair based on sign bits of the respective first data elements (Fig. 13A-B “1326” [0134]) and second data elements (Fig. 13A-B “1328” [0134]),
wherein the output circuits further comprise a conversion circuit (Fig. 13A-B “1342” [0142]) configured to generate two's complements of the shifted partial products based on the respective output signs ([0132]) prior to being added by the first integer adder circuit (Fig. 13A-B “1342” before “1346” [0138]).
Claim 14 recites similar limitations to claim 1. The claim 1 analysis similarly applies, and additionally in claim 14, Urbanski teaches: each integer multiplier circuit is provided a different pair of portions of mantissa (Fig. 13A-B “1308, 1324” mant. A[0] and mant. B[0] [0141]), wherein the pairs of portions of the mantissas do not include a pair comprising a least-significant portion of a mantissa of the set of first data elements (Fig. 13A-B pair “1308, 1324” does not include mant. A[n] [0141]) and a least-significant portion of a mantissa of the set of second data elements (Fig. 13A-B pair “1308, 1324” does not include mant. B[n] [0141]).
Claim 15 recites similar limitations to claim 2. The claim 2 analysis similarly applies, and claim 15 is similarly rejected.
Claim 18 recites similar limitations to claim 1. The claim 1 analysis similarly applies, and additionally in claim 18, Urbanski teaches: a controller circuit (Fig. 13A-B “1306” [0129]); an accumulator circuit (Fig. 13C “1310” [0144]); and a plurality of multiplication and accumulation (MAC) cells (Fig. 13A-C “1301A-1301Z, 1303, 1310” [0129]; Fig. 16 “1604” [0194]), wherein each of the plurality of MAC cells comprises: input circuits configured to receive (Fig. 13A-B “1301A-1301Z” [0124]); and output circuits (Fig. 13A-C the circuitry following multiplier, and before accumulator “1336, 1342, 1346, 1353, 1351, 1355A, 1357” [0132, 0135, 0138) provide the output data element (Fig. 13C “1359” [0135]) to the accumulator circuit (Fig. 13C “1359” to “1310” [0135]), wherein the accumulator circuit is configured to accumulate the output data elements generated by the plurality of MAC cells (Fig. 13 C “1310” [0144-0145]) to generate an output tensor ([0044], [0127], [0139-0141] Flexpoint).
Claim 19 recites similar limitations to claim 2. The claim 2 analysis similarly applies, and claim 19 is similarly rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-5, 16-17, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Urbanski as applied to claims 1, 14, 18 above, and further in view of US 20180157961 A1 Henry et al. (hereinafter “Henry”).
Regarding claim 3, the teachings addressed in the claim 1 analysis and rejection
are incorporated, and Urbanski discloses wherein:
the plurality of integer multiplier circuits (see claim 1 mapping).
Although Urbanski discloses the plurality of integer multiplier circuits, they appear to be silent to disclosing a first set of integer multiplier circuits having a first bit size; and a second set of integer multiplier circuits having a second bit size different from the first bit size.
Henry discloses a first set of integer multiplier circuits having a first bit size (Fig. 18 “242A” [0178] 16 bits); and
a second set of integer multiplier circuits having a second bit size different from the first bit size (Fig. 18 “242B” [0178] 8 bits).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Urbanski’s accelerator circuitry with Henry’s integer multiplier circuitry and sizing because they are in the claimed invention’s same field of endeavor of multiply-accumulate architecture ([abstract]). Modifying with Henry’s integer multiplier circuitry and sizing purport improvements via its flexibility for the programmer ([0200]), and therefore improves the efficiency of calculations by modeling the amount of precision needed by the particular application ([0200]). It would have been obvious to one of ordinary skill in the art to configure Urbanski’s accelerator circuitry with Henry’s integer multiplier circuitry and sizing as doing so would have been beneficial.
Regarding claim 4, the teachings addressed in the claim 3 analysis and rejection
are incorporated, and Urbanski discloses wherein:
a mantissa bit size of the floating-point data type is eleven bits ([0124] using the logic given for the 32-bit example (N=32), (N=11) since N can be any value between 0 to N and given the example is 32 is inclusive of N=11 [0129]), and
wherein the portions of the mantissas provided to the plurality of integer multiplier circuits (see claim 1 mapping) comprises the least-significant portions each including three bits from three least- significant bit positions of the respective mantissas ([0124] 8-15 element positions input to 1301B where only 8, 9, and 10 are utilized given N=11), most-significant portions each including eight bits from eight most-significant bit positions of the respective mantissas ([0124] 0-7 element positions input to 1301A), and complete portions comprising all eleven bits of the respective mantissas ([0124], [0129] N=11).
Regarding claim 5, the teachings addressed in the claim 4 analysis and rejection
are incorporated. Urbanski is silent with disclosing the bit size of the first set of integer multiplier circuits is eleven bits and the bit size of the second set of integer multiplier circuits is eight bits.
Henry discloses the bit size of the first set of integer multiplier circuits is eleven bits (Fig. 18 “242A” [0178] 16 bits, which is at least 11 bits and effectively is 11 when 5 bits are not utilized in multiplication) and the bit size of the second set of integer multiplier circuits is eight bits (Fig. 18 “242B” [0178] 8 bits).
The motivation to modify provided with respect to claim 3 similarly applies.
Claims 16-17 recite similar limitations to claims 3-5. The claims 3 and 4-5 analysis similarly applies to claims 16 and 17 respectively, and claims 16-17 are similarly rejected.
Claim 20 recites similar limitations to claims 4-5. The claims 4-5 analysis similarly applies to claim 20 respectively, and claim 20 is similarly rejected.
Claims 9-13 are rejected under 35 U.S.C. 103 as being unpatentable over Urbanski as applied to claims 1, 14, 18 above, and further in view of US 20200026494 A1 Langhammer et al. (hereinafter “Langhammer”) in view of Patterson.
Regarding claim 9, the teachings addressed in the claim 8 analysis and rejection
are incorporated, and Urbanski discloses wherein:
the composition circuit is configured (see claim 6 mapping), the sum generated by the first integer adder circuit from two's complement (see claim 6 mapping), and the output data element is based on the determined maximum exponent sum (see claim 7 mapping).
Urbanski appears to be silent with disclosing:
convert the sum generated by the first integer adder circuit from two's complement to signed-magnitude format; and round the converted sum to a predetermined bit length, wherein a sign bit of the output data element is based on the converted sum, an exponent, and a mantissa of the output data element is based on the rounded sum.
Langhammer discloses:
convert the sum generated by the first integer adder circuit from two's complement to signed-magnitude format (Fig. 7A “718” [0062], [0065]); and
round the converted sum to a predetermined bit length (Fig. 7A “724” [0062], [0065-0066]), wherein a sign bit (Fig. 7A output of “728” [0062], [0066]) of the output data element is based on the converted sum (Fig. 7A final floating-point containing “Ss” in relation to “Ms” of which was converted in “718” [0061]), an exponent (Fig. 7A output of “726” [0062], [0066]), and a mantissa (Fig. 7A output of “724” [0062], [0065-0066]) of the output data element is based on the rounded sum (Fig. 7A “724” [0065-0066]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Urbanski’s accelerator circuitry with Langhammer’s converting, rounding, and sign/exponent/mantissa features because they are in the claimed invention’s same field of endeavor of multiply-accumulate architecture ([0038]). Modifying with Langhammer’s converting, rounding, and sign/exponent/mantissa features would have yielded predictable functionality as the features are derived from the classical implementation and architecture of adders, thus making them known techniques in the art ([0004], [0061, 0068]). Further, converting (see Patterson, p. 75, 199-200) and rounding (see Patterson, p. 205) are common operations utilized in floating-point adders, and floating-point formats are known in the art (see Patterson, p. 197-198). It would have been obvious to one of ordinary skill in the art to configure Urbanski’s accelerator circuitry with Langhammer’s features as they are well known in the art corresponding with adder architectures, doing so would have been yielded predictable functionality of performing the converting and rounding features and basing in floating point format (sign, exponent, mantissa).
Regarding claim 10, the teachings addressed in the claim 9 analysis and rejection
are incorporated, and Urbanski discloses wherein:
the composition circuit (see claim 6 mapping), the maximum exponent sum (see claim 7 mapping), and the output data element (see claim 1 mapping).
Urbanski appears to be silent with disclosing:
normalize the rounded sum; and
adjust the maximum exponent sum based on the normalization,
wherein the exponent of the output data element is based on the adjusted maximum exponent sum and the mantissa of the output data element is based on the normalized sum.
Langhammer discloses: normalize the rounded sum (Fig. 7A “722” [0062, 0065]); and
adjust the maximum exponent sum based on the normalization (Fig. 7A “726” receives output from “724” post normalization and rounding [0066]),
wherein the exponent of the output data element is based on the adjusted maximum exponent sum (Fig. 7A “726” receives output from “724” post normalization and rounding and further outputs “Es” [0066]) and the mantissa of the output data element is based on the normalized sum (Fig. 7A “724” receives output from “722” and further outputs “Ms” [0065-0066]).
Langhammer discloses normalization before rounding, however, it would have been obvious to modify the order of these operations and thus functionality of the values processed it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. Further, Langhammer discloses configuring the circuitry in such a way would be recognized by one skilled in the art ([0024], [0155]).
The motivation to modify provided with respect to claim 9 similarly applies.
Regarding claim 11, the teachings addressed in the claim 10 analysis and rejection are incorporated, and Urbanski discloses wherein:
the multiplexer circuit (see claim 1 mapping) is further configured to:
provide different combinations of the portions of the mantissas of the set of first data elements and of the set of second data elements ([0124]) to the plurality of integer multiplier circuits (Fig. 13A-B “1334” and other unnumbered multipliers [0132]) of the device (see claim 1 mapping).
Urbanski appears to be silent with disclosing during different respective cycles.
Langhammer discloses during different respective cycles ([0042], [0050]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Urbanski’s accelerator circuitry with Langhammer’s cycle features because they are in the claimed invention’s same field of endeavor of multiply-accumulate architecture ([0038]). Modifying with Langhammer’s cycle features would have yielded predictable functionality as the features are derived from clock-based architecture ([0042], [0050]). Further, clock-based architectures are commonly utilized, are known in the art, and are used to assess performance of devices and algorithms (see Patterson, p. 33, 36). It would have been obvious to one of ordinary skill in the art to configure Urbanski’s accelerator circuitry with Langhammer’s cycles features as they are well known in the art corresponding with clock-based architectures, doing so would have been yielded predictable functionality of performing based on clock cycles.
Regarding claim 12, the teachings addressed in the claim 11 analysis and rejection are incorporated, and Urbanski discloses further comprising:
a second shift circuit (Fig. 13C “1355A-Z” [0135]) configured to shift bits of the partial products generated by the different respective integer multiplier circuits (Fig. 13A-B “1334” and other unnumbered multipliers [0132]) based on a bit position of the portion of the mantissa of the first data element multiplied to generate the respective partial products ([0138], [0143]); and
a second integer adder circuit (Fig. 13C “1357” [0135]) configured to add the shifted partial products corresponding to each of the first data elements to generate respective partial sums (Fig. 13C first outputs from top row of adders in “1357” [0138], [0143]),
wherein the first shift circuit (Fig. 13A-B “1336” [0132-0133]) is configured to shift the bits of the partial sums based on the determined difference between the maximum exponent sum and the respective exponent sum of the corresponding data-element pair (Fig. 13A-B “1341” to shift registers “1336” [0132]),
wherein the conversion circuit (Fig. 13A-B “1342” [0142]) is configured to generate two's complements of the shifted partial sums ([0132]), and
wherein the first integer adder circuit (Fig. 13A-B “1346” [0138]) is configured to add the shifted partial sums to generate the sum (Fig. 13A-B “1347A-Z” [0138] [0143] single product).
Regarding claim 13, the teachings addressed in the claim 12 analysis and rejection are incorporated, and Urbanski discloses wherein:
the output circuits (see claim 1 mapping) further comprise:
a third shift circuit (Fig. 13C “1366” [0145]) configured to shift bits ([0146]) of the sum generated by the first integer adder circuit (Fig. 13A-B “1346” [0138]) based on the device (see claim 1 mapping), wherein the composition circuit (see claim 6 mapping) generates the output data element (Fig. 13C “1359” [0135]) based on the shifted sum (Fig. 13C “1359” shifted with accumulated value “1358” output [0145-0146]).
Urbanski appears to be silent with disclosing a cycle count.
Langhammer disclose a cycle count (Fig. 5A “Cycle” #1-23 [0042], [0050]).
The motivation to combine provided with respect to claim 11 similarly applies.
Response to Arguments
Claim Objections. The objections to the claims are maintained.
35 USC 101. Applicant asserts in substance the following:
Applicant asserts that, claims 1-20 recite hardware, and every feature at issue under the Office's§ 101 analysis recites a hardware circuit - literally a specific, concrete implementation. Hardware is not an abstract idea. Moreover, such circuits are not "generic computing elements," unlike a" general purpose computer" or a "storage medium" that the courts have recognized as not transforming an abstract idea.
Instead, the positively recited multiplexer circuit, integer multiplier circuits, and output circuits, which are arranged in a specific interconnection in which the multiplexer is "configured to bypass providing least-significant portions of the mantissas ... for multiplication with least significant portions of the mantissas," define a particular hardware accelerator architecture. They do not define a mathematical relationship, formula, or calculation (see Remarks p. 13 ⁋2-3).
Examiner respectfully disagrees. Aside from generally reciting a multiplexer circuit, multiplier circuits, and output circuits, no other explicit recitation of input/output connections or further structural limitations of the circuits is given. Moreover, no such interpretation of the claims is given due to a 112(f) invocation. The circuits are instead recited by what they do, the functionality they perform, rather than by what they are, as such functionality does not by nature incorporate corresponding structural components or the particular hardware accelerator architecture as argued.
Applicant asserts that, the Office Action's "pen and paper" framing illustrates the analytical mistake underlying the rejections. The Office Action writes that "but for the 'a device,' 'a plurality of integer multiplier circuits,' 'a multiplexer circuit,' and 'output circuits' language, the claim encompasses manually providing portions of the data for multiplication and generating [an] output data value." The premise of this sentence, "but for [the entire recited apparatus]," effectively disregards the text of every element of the claim. Removing the device, the multiplier circuits, the multiplexer circuit, and the output circuits from claim 1 leaves no claim at all. Any patent claim could be considered an abstract idea if all of the hardware implementation details were removed from the analysis of the claim (see Remarks p. 13 ⁋4).
Examiner respectfully disagrees. The statement of the analysis was made in such a manner to highlight the distinctions between the limitations of the claim analyzed as part of the abstract idea from the limitations of the claim to be analyzed as part of the additional elements.
Applicant asserts that, the Mayo/Alice inquiry asks whether the claim as a whole recites only a judicial exception, not whether a hypothetic claim stripped of all implementation hardware recites only a judicial exception. Under controlling Federal Circuit authority, claims directed to a specific machine implementation are not directed to the abstraction the machine performs. See, e.g., McRO, Inc. v. Bandai Namco Games Am. Inc., 837 F.3d 1299, 1314-16 (Fed. Cir. 2016) (claims to specific implementation not directed to the underlying abstract idea even where the implementation performs mathematical operations) (see Remarks p. 13 ⁋5 - p. 14 ⁋1).
Examiner respectfully disagrees. The claims have been interpreted as a whole as indicated by the statement “Taken alone or in combination, they fail to integrate the judicial exception into a practical application.” found on page 6 of the Non-Final Office Action filed 03/19/2026.
Applicant asserts that, even assuming, arguendo, that claim 1 did recite an abstract idea (which, as noted above, it is not), claim 1 would integrate that exception into a practical application and therefore be patentable under Step 2A Prong 2 of the Alice framework. The recited multiplexer circuit is not a generic routing element; it is "configured to bypass providing least-significant portions of the mantissas of the set of first data elements to integer multiplier circuits ... for multiplication with least-significant portions of the mantissas of the set of second data elements." This is a particular architectural feature (the multiplexer's bypass configuration) of the recited hardware implementation, which eliminates the least-significant partial product from the partial-product collection. That architectural feature provides a specific, concrete improvement to floating-point accelerator design that provides a reduced multiplier count and circuit area. The Office Action does not address this architectural choice; it asserts that this hardware architecture is simply a collection of "generic computing elements," which is improper, as noted above, and ignores the actual language of the claims (see Remarks p. 14 ⁋2).
Examiner respectfully disagrees. As evidenced in Applicant’s argument, the recited multiplexer circuit is claimed by its functionality rather than specific structural limitations as Applicant has interpreted in the argument. In light of the specification, the “bypass” limitation is described with respect to the abstract idea, the mathematical concepts and/or mental processes ([0045], [0055], [0059], [0071]).
No additional elements and/or combination of additional elements are claimed that result in the purported improvement beyond the mathematical concepts and/or mental processes.
With respect to a purported improvement derived from “eliminating the least-significant partial product” it is the abstract idea, the manner of applying the mathematical relationships and/or mental processes to perform the bypassing that yields the purported improvements. See specification ([0045], [0055], [0059], [0071]).
See MPEP 2106.05(a)(I). “Examples that the courts have indicated may not be sufficient to show an improvement in computer-functionality”.
See MPEP 2106.05(a)(II). “It is important to keep in mind that an improvement in the abstract idea itself (e.g. a recited fundamental economic concept) is not an improvement in technology.”
See also MPEP 2106.05. An inventive concept "cannot be furnished by the unpatentable law of nature (or natural phenomenon or abstract idea) itself."
Applicant asserts that, the Office Action's Step 2B analysis is similarly deficient. The Office Action includes no factual finding under Berkheimer v. HP Inc., 881 F.3d 1360, 1369 (Fed. Cir. 2018), that the ordered combination of a bypass-configured multiplexer, a plurality of integer multipliers, and output circuits producing an output data element from partial products and exponents was well understood, routine, and conventional (WURC). An unsupported assertion that the recited components are "generic computing elements" does not discharge the Berkheimer burden. Further, as noted below, the Office Action's argument that the claims are anticipated or unpatentable is defective on multiple grounds, and the inability of the Office to construct an effective argument under§§ 102 or 103 further detracts from any allegation that any pending claim is WURC (see Remarks p. 14 ⁋3).
Examiner respectfully disagrees. No additional elements in claim 1 with respect to the multiplexer circuit, integer multiplier circuits, and output circuits have been analyzed as insignificant extra-solution activities, and therefore have not necessitated a re-evaluation to find if that or those elements were unconventional or otherwise more than well-understood, routine, or conventional activity.
35 USC 102. Applicant asserts the following in substance:
Applicant asserts that, claim 1 recites a different architecture. The claimed multiplexer circuit is "configured to provide portions of mantissas of a set of first data elements ... and portions of mantissas of a set of second data elements ... to respective integer multiplier circuits of the plurality of integer multiplier circuits, wherein each integer multiplier circuit is configured to multiply a respective portion of the mantissa of a first data element by a respective portion of the mantissa of a second data element to generate a partial product." Each integer multiplier circuit is configured to multiply a respective portion of the mantissa - singular - of a first data element by a respective portion of the mantissa of a second data element. Each data element has the mantissa, and the recited "portion" is a sub-part of that single mantissa. The claimed architecture distributes portions of a single data element's mantissa across multiple multipliers, each multiplier producing a partial product from a pair of mantissa portions (see Remarks p. 16 ⁋3 – p. 17 ⁋1).
Urbanski's mantissa A[0] is the complete mantissa of vector A's element [0], not a portion of any mantissa. Urbanski has no architectural step that partitions a mantissa into portions, distributes the portions across multiple multipliers, or produces a partial product from a pair of mantissa portions. The Office Action's mapping treats each Urbanski vector-element pair as a "first data element/ second data element" pair, which leaves each Urbanski multiplier multiplying complete mantissas - not portions – and accordingly leaves the "portion of the mantissa of a [first/ second] data element" feature unmapped (see Remarks p. 17 ⁋2).
Examiner respectfully disagrees. Urbanski discloses a set of first data elements of which contain portions of mantissas of said set (Fig. 13A-B "1308" mant. A[0]:A[n] of vector A [0127]) and a set of second data elements of which contain portions of mantissas of said set (Fig. 13A-B "1324" mant. B[0]:B[n] of vector B [0127, 0132]).
The language “a respective portion of the mantissa of a first data element” and “a respective portion of the mantissa of a second data element” is interpreted to refer back to the portions of mantissas of a set of first data elements and the portions of mantissas second data elements as “the mantissa” solely was not previously recited beforehand. Thus, it is interpreted as such to maintain antecedent basis for the claim language and the claims given their plain meaning (or the broadest reasonable interpretation of the claim). There is nothing recited in the claim to explicitly preclude that respective mantissa portions are derived from a singular mantissa, rather the claim merely recites the respective portions of the mantissas are derived from the provided portions of mantissas of the set of first data elements and second data elements. Moreover, claim 1 does not recite “partition a mantissa into portions” and thus Applicant is arguing unclaimed features. Therefore, Urbanski discloses the limitations as claimed.
Applicant asserts that, the Office Action's "bypass" argument fails on the same ground. The Office Action maps the bypass feature to Urbanski's "fig. 13a-b mant. a[n] [0127-0129]." Urbanski's "mant. a[n]" is the complete mantissa of the Nth element of vector A, not a least-significant portion of any mantissa. Because Urbanski does not partition mantissas, Urbanski has no least-significant mantissa portion that the multiplexer could be "configured to bypass providing" for multiplication with a least-significant mantissa portion of a second data element. The architectural antecedent that the bypass feature presupposes is absent from Urbanski (see Remarks p. 17 ⁋3).
Examiner respectfully disagrees. As stated in response to Argument 1 above, “partitioning of mantissas” is not claimed. The language “portions of mantissas” does not by nature lend itself to be interpreted inferentially that partitioning or some other subdividing functionality was performed.
Urbanski discloses the multiplexer circuit is configured to bypass providing least-significant portions of the mantissas of the set of first data elements (Fig. 13A-B mant. A[n] [0127-0129]). Examiner’s response to Argument 1 is incorporated for the points directed to the interpretation of provide portions of mantissas of a set of first data elements, portions of mantissas of a set of second data elements, respective portion of the mantissa of a first data element, and respective portion of the mantissa of a second data element. Thus, “providing least-significant portions of the mantissas” in the context of the “portions of the mantissas” as mapped in claim 1 corresponds to the portions of the mantissas data elements in its entirety, rather than to a singular “mantissa” as argued as no singular mantissa has been claimed. Therefore, Urbanski discloses the multiplexer circuit is configured to bypass the leftmost portions of the mantissas as recited in the claims.
Applicant asserts that, Urbanski also expressly addresses the figure-labeling artifact that the Office Action treats as a "bypass," directly contradicting the Office's interpretation of that artifact. Urbanski' s specification states: "A reference number for the other inputs (e.g., for elements 1 through N) are not drawn in this figure so as not [to] obfuscate the data flow/lines." Urbanski, [0128]. Urbanski has dedicated processing components for every element position from 0 through N - the figure simply omits reference numbers for the intermediate positions to avoid clutter. There is no element position in Urbanski's architecture for which multiplication is bypassed; Urbanski multiplies every corresponding pair of vector elements (see Remarks p. 17 ⁋4).
Examiner respectfully disagrees. Claim 1 recites wherein “the multiplexer circuit is configured to bypass providing least-significant portions of the mantissas of the set of first data elements”. Urbanski discloses the bypass providing least-significant portions of the mantissas of the set of first data elements (Fig. 13A-B mant. A[n] [0127-0129]). Urbanski discloses in [0127-0129] bypassing of the least-significant portions (mant. A[n]) by the multiplexers (Fig. 13A-B "1330, 1332" and other unnumbered muxes [0132]).
Moreover, aside from the multiplexer circuit is configured to bypass, it is not recited “element position for which multiplication is bypassed” as Applicant argues, and thus, based on the BRI of the claim it is interpreted that the multiplexer circuit performs bypass to provide least-significant portions of the mantissas.
Applicant asserts that, Dependent claims 2, 15, and 19 recite a 24-bit mantissa partitioned into three 8-bit portions (least-significant, middle, and most-significant). Urbanski neither discloses nor suggests this feature. The Office Action alleges that it does, arguing, "using the logic given for the 32-bit example (n=32), (n=24) since n can be any value between 0 to n and given the example is 32 is inclusive of n=11."
This argument conflates two different parameters in Urbanski. Urbanski's "N" is the number of elements in each input vector, not the bit width of a mantissa. Urbanski, [0127] ("the vectors ... have a same number of elements equal to N+l. N may be any positive integer ... "). Urbanski's statement that N "may be any positive integer" applies to vector length only and does not establish that Urbanski discloses a mantissa partitioned into 8-bit portions of any width. Urbanski does not partition mantissas at all, and accordingly does not disclose a 24-bit mantissa partitioned into three 8-bit portions (nor an 11-bit mantissa partitioned as recited in claim 4) (see Remarks p. 18 ⁋4-5).
Examiner respectfully disagrees. The logic used to interpret claim 1 and stated in response to argument 1 is similarly applied. Thus, “a mantissa bit size” in the context of the “portions of the mantissas” as mapped in claim 1 corresponds to the portions of the mantissas data elements in its entirety, rather than to a singular “mantissa” as argued as no singular mantissa has been claimed. Moreover, Urbanski gives an example of N=32 ([0124]) to illustrate the element positions capabilities and effectively teaches a greater example than what is claimed merely due to the claim reciting a value less than what is disclosed.
Applicant asserts that, even if Urbanski's "any positive integer" generality could be read on a mantissa bit width (which it cannot, for at least the reasons above) a generic statement that a reference's parameter "may be any value" does not anticipate a specific claimed value with the requisite specificity. MPEP § 2131.03; see also Atofina v. Great Lakes Chem. Corp., 441 F.3d 991, 999 (Fed. Cir. 2006) (a broad disclosed range does not anticipate a narrower claimed range falling within it). The Office Action's "n=24 since n can be any value" is an unsupported obviousness argument masquerading as§ 102 rejection; it cannot establish either anticipation or unpatentability under§ 103 (see Remarks p. 19 ⁋1).
Examiner respectfully disagrees. Urbanski discloses a range of values N=12 as a example in [0124] of which anticipates the claim language. Reference to MPEP 2131.03 is not persuasive as the section details applying prior art to claimed ranges, of which is not recited in the claims, rather than solely ranges present in the prior art teachings.
Applicant asserts that, anticipation under§ 102 requires not merely that each claimed element be found in the reference, but that the elements be "arranged or combined in the same way as recited in the claim." Net Money/Nat 1369 (Fed. Cir. 2008); accord MPEP § 2131. The Office Action attempts to tie together Urbanski's shift register 1336, integer adder 1346, and realign circuit 1303 - three components that, in Urbanski, are not arranged as the claim recites. Claim 6 requires a composition circuit that generates the output data element based on the sum generated by the first integer adder circuit; Urbanski's realign circuit 1303 operates downstream of and across the outputs of multiple sum-of-products circuits, not from the sum of one adder. The elements the Office Action assembles from Urbanski are not "arranged as in the claim" for purposes of § 102 (see Remarks p. 19 ⁋4).
Examiner respectfully disagrees. Claim 6 describes the arrangement of the first shift circuit, first integer adder circuit, and composition circuit by manner of their respective functionality. For example, the first shift circuit shifts partial products, of which is then added by the first integer adder circuit to generate a sum, where finally the composition circuit generates an output based on the sum. Claim 6 does not recite specific input/output connections as Applicant appears to interpret it based on the arguments Applicant asserts, or recite particular restrictions for connections.
Applicant asserts that, Urbanski's realign circuit 1303 does not generate an output data element based on the sum produced by one adder circuit. Rather, the realign circuit 1303 receives outputs from multiple sum-of-products circuits 1301A through 1301Z and combines them via a second set of adders 1357 to produce a single resultant for the accumulator. Urbanski, [0143]. Urbanski's realign circuit 1303 is an inter-sum-of-products combiner that aggregates outputs from many sum-of-products circuits to feed the accumulator 1310. Urbanski, [0146]. The recited composition circuit, by contrast, generates the output data element based on the sum - singular - generated by the first integer adder circuit – likewise singular - of claim 6. Urbanski's 1303 does not generate output based on the sum from one adder; it operates downstream of and across multiple adder outputs (see Remarks p. 20 ⁋1).
Examiner respectfully disagrees. A first integer adder circuit (Fig. 13A-B “1346” [0138]) is used in the generation of the output data element. Applicant makes the argument that more adders utilized, somehow does not disclose, a singular adder as argued. This argument is unpersuasive as Applicant is not arguing whether it is an adder circuit or if adding is being performed, but rather the quantities of which under the BRI of the claim is still disclosed.
35 USC 103. Applicant asserts the following in substance:
1. Applicant asserts that, Henry contains no such teaching. Henry discloses two - and only two – multiplier sizes [0178]. Henry does not disclose an 11-bit multiplier or any multiplier of intermediate width.
Nor does Henry describe operation of the 16-bit multiplier 242A with five bits unused. To the contrary, Henry teaches that when the neural processing unit (NPU) is in a narrow configuration in which 8-bit data words are processed by the 16-bit wide multiplier, the operand selection logic 1898 first sign-extends or zero-pads the 8-bit words to the full 16-bit width before providing them to the wide multiplier[0179]. The wide multiplier always operates on 16-bit operands; what changes between Henry's wide and narrow configurations is the source of those 16-bit operands, not the bit size of the multiplier circuit itself.
The bit size of a multiplier circuit is a structural property of the circuit, not a runtime utilization pattern. A 16-bit multiplier in which some upper input bits happen to be sign-extension bits or zero-padding bits remains a 16-bit multiplier circuit. Henry's wide multiplier 242A is a 16-bit multiplier; it is not, structurally, an 11-bit multiplier. The Office Action's "effectively 11 when 5 bits are not utilized" reasoning finds no support in Henry's disclosure; nor would a POSITA believe such a runtime modification could be made with a reasonable expectation of success (see Remarks p. 21).
Examiner respectfully disagrees. Henry discloses the limitation as interpreted by the BRI of the claim as the multipliers are described as having a bit size (see claim 3 for which claim 6 depends on), rather than an explicit recitation (e.g. 16-bit multiplier circuit). This language does not merely limit the structural capabilities of the multiplier itself. Further, in light of the instant application’s specification, paragraph [00125] describes the bit size of a multiplier circuit “may refer to the maximum number of bits that may be used to represent the two values being multiplied”. Therefore, embodiments in which operand sizing does factor into account unlike what Applicant asserted. See Henry, [0200].
2. Applicant asserts that, the claimed sequence is accordingly: convert, then round, then normalize.
At every block in Langhammer that performs both normalization and rounding, normalization is performed first and rounding follows. Langhammer therefore does not teach the claimed sequence of converting and rounding the converted sum first and normalizing the rounded sum thereafter.
The order of normalization and rounding in floating-point arithmetic is therefore not a functionally inconsequential rearrangement of parts. It produces a different mode of operation and different numerical results. Japikse does not support a rejection in which the asserted rearrangement changes the operation <u>*and</u> the result of the asserted combination. Langhammer's normalize-then-round disclosure does not teach the claimed round-then normalize sequence, and the asserted Japikse* rationale fails to bridge the gap (see Remarks p. 22-24).
Examiner respectfully disagrees. Although the instant claims do no recite structural components that corresponding to the claimed functionality, Langhammer does disclose structural components corresponding to the claimed functionality. The Japikse rationale as cited in the motivation, in combination with the explicit disclosure in Langhammer ([0155]) describing the methods or processes described are merely illustrative and various modifications may be implemented by those skilled in the art, support the findings that Langhammer discloses the claimed limitations. Making the modification would have been obvious to one of ordinary skill in the art before the effective filing date as mere rearranging parts involves only routine skill in the art in addition to Langhammer’s disclosure of making modifications to the processes and methods ([0024], [0155]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MARKUS ANTHONY VILLANUEVA/Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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