Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3, 5, 6 and 8-10 rejected under 35 U.S.C. 103 as being unpatentable over Ma (U.S. Patent Pub. No. 2020/0083225) of record, in view of Kanamori (U.S. Patent Pub. No. 2014/0085961) of record, in view of Tanzawa (U.S. Patent Pub. No. 2014/0078827).
Regarding Claim 1
FIG. 1F of Ma discloses a microelectronic device, comprising: vertical stacks of memory cells, each vertical stack of memory cells comprising: a vertical stack of access devices (160); a vertical stack of capacitors (170) horizontally neighboring the vertical stack of access devices; and a conductive pillar structure (148) in electrical communication with the vertical stack of access devices.
Ma is silent with respect to “low first global digit lines vertically above and neighboring the vertical stacks of memory cells; high first global digit lines vertically spaced from the vertical stacks of memory cells a greater distance than the low first global digit lines; and low second global digit lines and high second global digit lines respectively horizontally interleaved with the low first global digit lines and the high first global digit lines in a horizontal direction, the low second global digit lines and high second global digit lines being electrically isolated from the low first global digit lines and the high first global digit lines; and wherein each of the low first global digit lines and each of the high first global digit lines is individually in electrical communication with four of the conductive pillar structures” and “each one of the low second global digit lines (108) and the high second global digit lines individually horizontally neighbors one or more of at least one of the low first global digit lines and at least one of the high first global digit lines; and wherein each one of the low second global digit lines has a longitudinal axis that is axially aligned with a longitudinal axis of one of the low first global digit lines and each one of the high second global digit lines has a longitudinal axis that is axially aligned with a longitudinal axis of one of the high first global digit line”.
FIG. 8 of Kanamori discloses a similar microelectronic device, comprising low first global digit lines (HWL1) vertically above and neighboring the vertical stacks of memory cells (FIG. 4); high first global digit lines (HWL2) vertically spaced from the vertical stacks of memory cells a greater distance than the low first global digit lines; and low second global digit lines (HWL1) and high second global digit lines (HWL2) respectively horizontally interleaved with the low first global digit lines and the high first global digit lines in a horizontal direction, the low second global digit lines and high second global digit lines being electrically isolated from the low first global digit lines and the high first global digit lines (FIG. 4 and [0062, 0087]), and wherein each of the low first global digit lines and each of the high first global digit lines is individually in electrical communication with four of the conductive pillar structures (FIG. 19), wherein each one of the low second global digit lines (108) and the high second global digit lines individually horizontally neighbors one or more of at least one of the low first global digit lines and at least one of the high first global digit lines; and wherein each one of the low second global digit lines has a longitudinal axis that is axially aligned with a longitudinal axis of one of the low first global digit lines and each one of the high second global digit lines has a longitudinal axis that is axially aligned with a longitudinal axis of one of the high first global digit line.
Moreover, the configuration of the claimed “each of the low first global digit lines and each of the high first global digit lines is individually in electrical communication with four of the conductive pillar structures” is a matter of choice, which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant. In re Dailey 149 USPQ 47, 50 (CCPA 1966). See also Glue Co. v. Upton 97 US 3,24 (USSC 1878). MPEP 2144.04.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Ma, as taught by Kanamori. The ordinary artisan would have been motivated to modify Ma in the above manner for purpose of 3D memory device with improved integration and reliability ([0004] of Kanamori).
Ma as modified by Kanamori is silent with respect to “each one of the low second global digit lines (108) and the high second global digit lines individually horizontally neighbors one or more of at least one of the low first global digit lines and at least one of the high first global digit lines; and wherein each one of the low second global digit lines has a longitudinal axis that is axially aligned with a longitudinal axis of one of the low first global digit lines and each one of the high second global digit lines has a longitudinal axis that is axially aligned with a longitudinal axis of one of the high first global digit line”.
FIG. 8 of Tanzawa discloses a similar microelectronic device, wherein each one of the low second global digit lines (774/775) and the high second global digit lines (left 370-373) individually horizontally neighbors one or more of at least one of the low first global digit lines (374/375) and at least one of the high first global digit lines (right 370-373); and wherein each one of the low second global digit lines has a longitudinal axis that is axially aligned with a longitudinal axis of one of the low first global digit lines and each one of the high second global digit lines has a longitudinal axis that is axially aligned with a longitudinal axis of one of the high first global digit line.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Ma, as taught by Tanzawa. The ordinary artisan would have been motivated to modify Ma in the above manner for purpose of improving memory operations and reducing undesired coupling capacitance ([0191] of Tanzawa).
Regarding Claim 3
With respect to “a vertical distance between the low first global digit lines and the high first global digit lines is within a range of from about 100 nm to about 200 nm”, said distance is related to the integration density and parasitic capacitances. Therefore, said distance is considered to be a result effective variable. The claim to a specific distance therefore constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05).
Regarding Claim 5
With respect to “a distance between the conductive pillar structures in the horizontal direction is within a range of from about 50 nm to about 150 nm”, said distance is related to the integration density and parasitic capacitances. Therefore, said distance is considered to be a result effective variable. The claim to a specific distance therefore constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05).
Regarding Claim 6
With respect to “a vertical distance between an uppermost surface of the conductive pillar structures of the vertical stacks of memory cells and the high first global digit lines is about two times a vertical distance between the uppermost surface of the conductive pillar structures and the low first global digit lines”, said distance is related to the integration density and parasitic capacitances. Therefore, said distance is considered to be a result effective variable. The claim to a specific distance therefore constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05).
Regarding Claim 8
With respect to “the low first global digit lines, the high first global digit lines, the low second global digit lines, and the high second global digit lines individually have a dimension in the horizontal direction within a range of from about 20 nm to about 50 nm”, said distance is related to the integration density and conductance. Therefore, said distance is considered to be a result effective variable. The claim to a specific distance therefore constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05).
Regarding Claim 9
With respect to “a distance between one of the low first global digit lines and one of the low second global digit lines horizontally neighboring the one of the low first global digit lines in the horizontal direction is within a range of from about 80 nm to about 120 nm”, said distance is related to the integration density and parasitic capacitances. Therefore, said distance is considered to be a result effective variable. The claim to a specific distance therefore constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05).
Regarding Claim 10
FIG. 7 of Kanamori discloses a stack structure comprising vertically spaced conductive structures (VWL), at least some of the vertically spaced conductive structures are individually in electrical communication with a memory cell of the vertical stack of memory cells and comprise a gate of an access device of the vertical stack of access devices.
Claims 12-16 rejected under 35 U.S.C. 103 as being unpatentable over Ma, in view of Kanamori, in view of Lee (U.S. Patent No. 7,184,290).
Regarding Claim 12
FIG. 1F of Ma discloses a memory device, comprising: vertical stacks of dynamic random access memory (DRAM) cells, each of the DRAM cells comprising a storage device (170) horizontally neighboring an access device (160); conductive pillar structures (148) vertically extending along the vertical stacks of DRAM cells, each of the conductive pillar structures in electrical communication with access devices of one of the vertical stacks of DRAM cells.
Ma is silent with respect to “global digit lines horizontally spaced from one another in a horizontal direction”; “at least two of the global digit lines horizontally neighboring one another spaced a different vertical distance from the vertical stacks of DRAM cells than one another and are electrically isolated from each other”; “global digit lines vertically above and spaced from the vertical stacks of DRAM cells” and “multiple multiplexers, each of the multiplexers intervening between one of the global digit lines and an individual conductive pillar structure of the conductive pillar structures vertically extending along the vertical stacks of DRAM cells”.
FIG. 8 of Kanamori discloses a similar microelectronic device, comprising global digit lines (HWL) horizontally spaced from one another in a horizontal direction; at least two (HWL1 and HWL2) of the global digit lines horizontally neighboring one another spaced a different vertical distance from the vertical stacks of DRAM cells than one another and are electrically isolated from each other (FIG. 4 and [0062, 0087]); and global digit lines vertically above and spaced from the vertical stacks of DRAM cells.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Ma, as taught by Kanamori. The ordinary artisan would have been motivated to modify Ma in the above manner for purpose of 3D memory device with improved integration and reliability ([0004] of Kanamori).
Ma as modified by Kanamori is silent with respect “multiple multiplexers, each of the multiplexers intervening between one of the global digit lines and an individual conductive pillar structure of the conductive pillar structures vertically extending along the vertical stacks of DRAM cells”.
FIG. 3 of Lee discloses a similar microelectronic device, wherein each of the multiplexers (MUX) intervening between one of the global digit lines and an individual conductive pillar structure of the conductive pillar structures vertically extending along the vertical stacks of DRAM cells (Col. 7, Lines 12-48).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Ma, as taught by Lee. The ordinary artisan would have been motivated to modify Ma in the above manner for purpose of providing a DRAM device having a reduced bit line capacitance and reduced area (Col. 2, Lines 24-26 of Lee).
Regarding Claim 13
FIG. 8 of Kanamori discloses every other one of the global digit lines is located a same vertical distance from the vertical stacks of DRAM cells.
Regarding Claim 14
FIG. 1 of Ma discloses conductive structures horizontally extending in the horizontal direction and individually in electrical communication with the DRAM cells of the vertical stacks of DRAM cells.
Regarding Claim 15
FIG. 8 of Kanamori discloses one half of the global digit lines are located a first vertical distance from the vertical stacks of DRAM cells and an additional one half of the global digit lines are located a second, greater vertical distance from the vertical stacks of DRAM cells.
Regarding Claim 16
FIG. 8 of Kanamori discloses each of the global digit lines is in electrical communication with multiple conductive pillar structures.
Claim 4 rejected under 35 U.S.C. 103 as being unpatentable over Ma, Kanamori and Tanzawa, in view of Kuo (U.S. Patent Pub. No. 2010/0012916) of record.
Regarding Claim 4
Ma as modified by Kanamori and Tanzawa discloses Claim 1.
Ma as modified by Kanamori and Tanzawa is silent with respect to “the low second global digit lines and the high second global digit lines are respectively in electrical communication with second global digit line contact structures having a larger vertical dimension than first global digit line contact structures in electrical communication with the low first global digit lines and the high first global digit lines”.
FIG. 11 of Kuo discloses a similar microelectronic device, wherein the second global digit lines are in electrical communication with second global digit line contact structures (73) having a larger vertical dimension than first global digit line contact structures in electrical communication with the first global digit lines.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Ma, as taught by Kuo, such that the low second global digit lines and the high second global digit lines are respectively in electrical communication with second global digit line contact structures having a larger vertical dimension than first global digit line contact structures in electrical communication with the low first global digit lines and the high first global digit lines, because the claimed configuration was a matter of choice, which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration was significant. In re Dailey 149 USPQ 47, 50 (CCPA 1966). See also Glue Co. v. Upton 97 US 3,24 (USSC 1878). MPEP 2144.04. The ordinary artisan would have been motivated to modify Ma in the above manner for purpose of improving integration level ([0037] of Kuo).
Claim 7 rejected under 35 U.S.C. 103 as being unpatentable over Ma, Kanamori and Tanzawa, in view of Suzuki (U.S. Patent Pub. No. 2011/0002159) of record.
Regarding Claim 7
Ma as modified by Kanamori and Tanzawa discloses Claim 1.
Ma as modified by Kanamori and Tanzawa is silent with respect to “the first global digit lines and the second global digit lines are individually in electrical communication with a sense amplifier”.
FIG. 11 of Suzuki discloses a similar microelectronic device, wherein the first global digit lines and the second global digit lines are individually in electrical communication with a sense amplifier (SA).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Ma, as taught by Suzuki. The ordinary artisan would have been motivated to modify Ma in the above manner for purpose of achieving low noise ([0003] of Suzuki).
Claims 7 and 18 rejected under 35 U.S.C. 103 as being unpatentable over Ma, Kanamori and Tanzawa, in view of Hilbert (U.S. Patent No. 6,377,504) of record.
Regarding Claim 7
Ma as modified by Kanamori and Tanzawa discloses Claim 1.
Ma as modified by Kanamori and Tanzawa is silent with respect to “the low first global digit lines, the high first global digit lines the low second global digit lines, and the high second global digit lines are individually in electrical communication with a sense amplifier”.
FIG. 2 of Hilbert discloses a similar microelectronic device, wherein the low first global digit lines, the high first global digit lines the low second global digit lines, and the high second global digit lines are individually in electrical communication with a sense amplifier (FIG. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Ma, as taught by Hilbert. The ordinary artisan would have been motivated to modify Ma in the above manner for purpose of reading the contents of the storage cells (Abstract of Hilbert).
Regarding Claim 18
FIG. 3 of Hilbert discloses global digit line contacts (301/302), each of the global digit line contacts individually in electrical communication with a multiplexer and one of the global digit lines.
Claim 12 rejected under 35 U.S.C. 103 as being unpatentable over Ma, in view of Kanamori, in view of Derner (U.S. Patent Pub. No. 2020/0328220) of record.
Regarding Claim 12
FIG. 1F of Ma discloses a memory device, comprising: vertical stacks of dynamic random access memory (DRAM) cells, each of the DRAM cells comprising a storage device (170) horizontally neighboring an access device (160); conductive pillar structures (148) vertically extending along the vertical stacks of DRAM cells, each of the conductive pillar structures in electrical communication with access devices of one of the vertical stacks of DRAM cells.
Ma is silent with respect to “global digit lines horizontally spaced from one another in a horizontal direction”; “at least two of the global digit lines horizontally neighboring one another spaced a different vertical distance from the vertical stacks of DRAM cells than one another and are electrically isolated from each other”; “global digit lines vertically above and spaced from the vertical stacks of DRAM cells” and “multiple multiplexers, each of the multiplexers intervening between one of the global digit lines and an individual conductive pillar structure of the conductive pillar structures vertically extending along the vertical stacks of DRAM cells”.
FIG. 8 of Kanamori discloses a similar microelectronic device, comprising global digit lines (HWL) horizontally spaced from one another in a horizontal direction; at least two (HWL1 and HWL2) of the global digit lines horizontally neighboring one another spaced a different vertical distance from the vertical stacks of DRAM cells than one another and are electrically isolated from each other (FIG. 4 and [0062, 0087]); and global digit lines vertically above and spaced from the vertical stacks of DRAM cells.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Ma, as taught by Kanamori. The ordinary artisan would have been motivated to modify Ma in the above manner for purpose of 3D memory device with improved integration and reliability ([0004] of Kanamori).
Ma as modified by Kanamori is silent with respect “multiple multiplexers, each of the multiplexers intervening between one of the global digit lines and an individual conductive pillar structure of the conductive pillar structures vertically extending along the vertical stacks of DRAM cells”.
FIG. 4 of Derner discloses a similar microelectronic device, wherein each of the multiplexers (MUX) intervening between one of the global digit lines (72) and an individual conductive pillar structure (38) of the conductive pillar structures vertically extending along the vertical stacks of DRAM cells.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Ma, as taught by Derner. The ordinary artisan would have been motivated to modify Ma in the above manner for developing integrated memory having strong signal, good durability over a large number of read/write cycles, fast access rates, and protection against cell-to-cell disturb mechanisms ([0002] of Derner).
Claim 24 rejected under 35 U.S.C. 103 as being unpatentable over Cloud (U.S. Patent No. 6,297,989) of record, in view of Kim (U.S. Patent Pub. No. 2020/0279601) of record, in view of Derner (U.S. Patent Pub. No. 2020/0328220) of record
Regarding Claim 24
FIG. 1 of Cloud discloses an electronic system, comprising: an input device (140); an output device (150); a processor device (120) operably coupled to the input device and the output device; and a memory device operably coupled to the processor device and comprising: vertical stacks of access devices; vertical stacks of capacitor structures horizontally neighboring the vertical stacks of access devices; conductive pillar structures individually vertically extending proximate to and in electrical communication with one of the vertical stacks of access devices; multiplexers (130); first global digit lines in electrical communication with some of the multiplexers; and second global digit lines in electrical communication with others of the multiplexers (FIG. 5 and Col. 9, Lines 11-31: multiplexers coupling to bit lines and control lines coupling to stacked capacitors).
Cloud is silent with respect to the memory device “comprising: vertical stacks of access devices; vertical stacks of capacitor structures horizontally neighboring the vertical stacks of access devices; conductive pillar structures individually vertically extending proximate to and in electrical communication with one of the vertical stacks of access devices”; “multiplexers vertically overlying the vertical stacks of capacitor structures”; “low first global digit lines vertically overlying the multiplexers, the low first global digit lines in electrical communication with some of the multiplexers; and high first global digit lines vertically spaced above the low first global digit lines and in electrical communication with others of the multiplexers”.
FIG. 2 of Kim discloses a similar microelectronic device, comprising vertical stacks of access devices (T); vertical stacks of capacitor structures (C) horizontally neighboring the vertical stacks of access devices; conductive pillar structures (BL) individually vertically extending proximate to and in electrical communication with one of the vertical stacks of access devices.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Cloud, as taught by Kim. The ordinary artisan would have been motivated to modify Cloud in the above manner for purpose of decreasing parasitic capacitance for minimized memory cell ([0004] of Kim).
Cloud as modified by Kim is silent with respect to “multiplexers vertically overlying the vertical stacks of capacitor structures”; “low first global digit lines vertically overlying the multiplexers, the low first global digit lines in electrical communication with some of the multiplexers; and high first global digit lines vertically spaced above the low first global digit lines and in electrical communication with others of the multiplexers”.
FIG. 4 of Derner discloses a similar microelectronic device, comprising multiplexers (MUX) vertically overlying the vertical stacks of capacitor structures (120); low first global digit lines (70) vertically overlying the multiplexers, and in electrical communication with the multiplexers; and high first global digit lines (72) vertically spaced above the low first global digit lines and in electrical communication with others of the multiplexers (FIG. 5).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Cloud, as taught by Derner such that low first global digit lines vertically overlying the multiplexers, the low first global digit lines in electrical communication with some of the multiplexers; and high first global digit lines vertically spaced above the low first global digit lines and in electrical communication with others of the multiplexers. The ordinary artisan would have been motivated to modify Cloud in the above manner for purpose of developing integrated memory having strong signal, good durability over a large number of read/write cycles, fast access rates, and protection against cell-to-cell disturb mechanisms ([0002] of Derner).
Claims 25-29 rejected under 35 U.S.C. 103 as being unpatentable over Cloud, Kim and Derner, in view of Park (U.S. Patent Pub. No. 2022/0044725) of record
Regarding Claim 25
Cloud as modified by Kim and Derner discloses Claim 24.
Cloud as modified by Kim and Derner is silent with respect to “each of the low first global digit lines is horizontally spaced from a horizontally neighboring one of the high first global digit line”.
FIG. 9 of Park discloses a similar microelectronic device, wherein each of the low first global digit lines (WL5) is horizontally spaced from a horizontally neighboring one (WL6) of the high first global digit line.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Cloud, as taught by Park. The ordinary artisan would have been motivated to modify Cloud in the above manner for purpose of increasing the integration density of the two-dimensional semiconductor device ([0004] of Park).
Regarding Claim 26
FIG. 9 of Park discloses the low first global digit lines and the high first global digit lines are in electrical communication with first global digit line contact structures having a smaller vertical dimension than second global digit line contact structures in electrical communication with second global digit lines.
Regarding Claim 27
FIG. 1 of Cloud discloses the multiplexers individually comprise a first electrode material in electrical communication with a second electrode material.
Regarding Claim 28
Modified Cloud discloses sense amplifiers vertically overlying the low first global digit lines and the high first global digit lines and low second global digit lines and high second global digit lines, the sense amplifiers in electrical communication with the low first global digit lines and the high first global digit lines and with the low second global digit lines and the high second global digit lines.
Regarding Claim 29
FIG. 9 of Park discloses the high first global digit lines are vertically closer to the sense amplifiers than the low first global digit lines.
Pertinent Art
Pertinent art includes US 20090097309, 20090289251, Penumatcha (U.S. Patent Pub. No. 20200105774), Park (U.S. Patent Pub. No. 2014/0198552), Chang (U.S. Patent Pub. No. 2021/0247962), Xue (U.S. Patent Pub. No. 2022/0223197), Shim (U.S. Patent Pub. No. 2017/0373084), Eom (U.S. Patent Pub. No. 2019/0147918), Liu (U.S. Patent Pub. No. 2020/0091164), Hishida (U.S. Patent Pub. No. 2021/0375923), Hwang (U.S. Patent Pub. No. 2013/0279233).
Response to Arguments
Applicant’s arguments with respect to Claims 1 and 12 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection. In response to applicant’s argument with respect to Cloud, the typo is corrected. Applicant’s arguments with respect to Derner is not persuasive. The MUX of Derner horizontally extends to connect MUX DRIVER (not a circle as labeled by the Applicant) and vertically overlaps the capacitor structures. For clarity, FIG. 4 is used.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897
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