Prosecution Insights
Last updated: April 19, 2026
Application No. 17/898,536

SEMICONDUCTOR DEVICE

Final Rejection §102§103
Filed
Aug 30, 2022
Examiner
KLEIN, JORDAN M
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Toshiba Electronic Devices & Storage Corporation
OA Round
2 (Final)
85%
Grant Probability
Favorable
3-4
OA Rounds
2y 7m
To Grant
94%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
451 granted / 528 resolved
+17.4% vs TC avg
Moderate +8% lift
Without
With
+8.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
21 currently pending
Career history
549
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
48.8%
+8.8% vs TC avg
§102
33.2%
-6.8% vs TC avg
§112
13.6%
-26.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 528 resolved cases

Office Action

§102 §103
DETAILED ACTION This Office Action is in response to the applicant's amendment filed June 20th, 2025. In virtue of this communication, claims 1, 4, 7, and 10 are currently presented in the instant application. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 4, 7, and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kalfus et al. (US 4,935,803; hereinafter Kalfus). With respect to claim 1, Kalfus teaches a semiconductor device in at least Figs. 6 and 7 with Figs. 3-5 teaching overlapping subject matter comprising: a lead frame 12 (see Figs. 6, 7, column 3, line 65 - column 4, line 23, column 4, line 37-43, and column 6, line 36-42); a semiconductor chip 16 mounted on the lead frame 12 (see Figs. 6, 7, column 2, line 11-15, column 3, line 65 - column 4, line 23, column 4, line 37-61, column 6, line 36-42); a clip member 80 connected to an electrode 22 of the semiconductor chip 16 via a conductive adhesive agent 78 (see Figs. 6, 7, column 4, line 5-9, and column 6, line 21 - column 7, line 3; bonding material 78 is solder); and a non-conductive surface protection film 18 provided on a connection face of the electrode 22, the surface protection film 18 including an inner edge IE facing the clip member 80, the inner edge IE defining an outer peripheral edge of a connection surface of the electrode 22 (see Figs. 6, 7, column 4, lines 5-23, 37-43, column 5, line 25-42, and column 6, line 59 - column 7, line 3; also see Fig. 7 annotated below), wherein at least part of an outer peripheral edge OPE of a connection face (where 80 contacts 78) of the clip member 80 is located at a position more inside than an outermost peripheral edge OMPE of the clip member 80 in plan view (see Figs. 6, 7, and column 6, line 43 - column 7, line 3; also see Fig. 7 annotated below; note increased separation between lower surface of 80 and the upper surface of 18), and within a range of the connection face (where 80 contacts 78) of the electrode 22, the outermost peripheral edge OMPE of the clip member 80 is located at a distance of a first clearance L from the inner edge IE of the surface protection film 18 (see Figs. 6, 7, column 5, line 25-42, and column 6, line 21 - column 7, line 3; also see Fig. 7 annotated below), and the at least part of the outer peripheral edge OPE of the connection face (where 80 contacts 78) of the clip member 80 is located at a distance of a second clearance L1 from the inner edge IE of the surface protection film 18, the second clearance L1 being larger than the first clearance L (see Figs. 6, 7, column 5, line 25-42, and column 6, line 21 - column 7, line 3; also see Fig. 7 annotated below). PNG media_image1.png 395 856 media_image1.png Greyscale With respect to claim 4, Kalfus teaches the semiconductor device according to claim 1, wherein a cross-sectional shape corresponding to the at least part of the outer peripheral edge OPE of the connection face (where 80 contacts 78) of the clip member 80 includes a recess at an end corresponding to the outer peripheral edge (see Figs. 6, 7, and column 6, line 43 - column 7, line 3; note increased separation between lower surface of 80 and the upper surface of 18 and 22. Also note Fig. 8 of instant application). With respect to claim 10, Kalfus teaches the semiconductor device according to claim 4, wherein the recess has a shape in which the cross-sectional shape of the clip member 80 is cut out in a polygonal shape (see Figs. 6, 7, and column 6, line 43 - column 7, line 3; note increased separation between lower surface of 80 and the upper surface of 18 and 22. Also note Fig. 8 of instant application). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kalfus et al. (US 4,935,803; hereinafter Kalfus) in view of Sato et al. (US 2018/0174998 A1; hereinafter Sato). With respect to claim 7, Kalfus discloses the semiconductor device according to claim 4. Kalfus does not disclose wherein the recess has a shape in which the cross-sectional shape of the clip member is cut out in a fan shape. Sato disclose a semiconductor device in at least Figs. 1-4 wherein a recess 26c has a shape in which the cross-sectional shape of a clip member 26 is cut out in a fan shape (see Figs. 1-4 and paragraphs 33). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the recess of Kalfus would have a shape in which the cross-sectional shape of the clip member is cut out in a fan shape as taught by Sato because by such a configuration excess solder is collected in the concave portion 26c, thereby making it possible to prevent solder overflow (see Sato: paragraph 33). Response to Arguments Applicant's arguments filed June 20th, 2025 have been fully considered but they are not persuasive. The applicant argues that “in Kalfus, there is no teaching or suggestion regarding the claimed ‘first clearance’ and also the claimed ‘the second clearance being larger than the first clearance.’ Thus, Kalfus does not (and cannot) disclose or suggest all of the claimed features.” The examiner respectfully disagrees. As outlined in the rejection above and shown in annotated Fig. 7 above, Kalfus teaches that the outermost peripheral edge OMPE of the clip member 80 is located at a distance of a first clearance L from the inner edge IE of the surface protection film 18, and the at least part of the outer peripheral edge OPE of the connection face (where 80 contacts 78) of the clip member 80 is located at a distance of a second clearance L1 from the inner edge IE of the surface protection film 18, the second clearance L1 being larger than the first clearance L (see Figs. 6, 7, column 5, line 25-42, and column 6, line 21 - column 7, line 3; also see Fig. 7 annotated above). Therefore, the claims remain rejected. It is noted that the claim does not require the outermost peripheral edge of the clip member to be located between the outer peripheral edge of the connection face of the clip member and the inner edge of the surface protection film. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Inquiry Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORDAN M KLEIN whose telephone number is (571)270-7544. The examiner can normally be reached 9:00 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /J.M.K/Examiner, Art Unit 2893 /SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Aug 30, 2022
Application Filed
Mar 12, 2025
Non-Final Rejection — §102, §103
Jun 20, 2025
Response Filed
Sep 30, 2025
Final Rejection — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
85%
Grant Probability
94%
With Interview (+8.2%)
2y 7m
Median Time to Grant
Moderate
PTA Risk
Based on 528 resolved cases by this examiner. Grant probability derived from career allow rate.

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