DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 8-13, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho (2011/0057300, newly cited, hereinafter, Cho ‘300) in view of Cho et al. (US 2018/0068934, hereinafter, Cho ‘934.)
In regard to claims 1 and 9, in figs. 1A-1F, for example, Cho ‘300 discloses a method of making a semiconductor package, comprising:
etching a conductive member to form a leadframe 118;
etching the leadframe to form a cavity, fig. 1E;
attaching a semiconductor component Q1 to the leadframe inside the cavity; and
attaching the semiconductor die 170 (para [0021]) to the leadframe on a side of the leadframe opposite the cavity.
Cho ‘300 mentions the semiconductor device could be any electronic device, but fails to mention a passive device. Nonetheless, passive devices also considered to be part of semiconductor device, for example, capacitor, resistor, etc. And it could be replaced with a device as disclosed by Cho’300. For example, Cho ‘934, in fig. 2, discloses an analogous package 50 including an etched lead frame 54B, and opening and a passive component, capacitor, 56 formed in the recess. The arrangement allows stack structure and thus reduce the volume of the package. This is known in the art.
Thus, it would be obvious to one of ordinary skill in the art at the time of the application was filed to replace the two devices as taught in order to provide stability and allow stack structure and thus reduce the volume of the package.
Furthermore, the combination inherently provides a leadframe that is already being cut/etched from a conductive material in order to provide a leadframe before etching to form a cavity. See Cho ‘300’s figS. 1A-1F.
Regarding claims 2 and 10, wherein a height of the passive component is less than a depth of the cavity. See Cho’300’s fig. 1F.
Regarding claims 3 and 11, the step of etching the leadframe to form the cavity includes etching the leadframe to a depth of approximately 50-75% of the total thickness of the frame. Cho’300’s fig. 1F.
Regarding claims 4 and 12, the above combination further comprising etching a recess in the cavity to electrically isolate terminals of the passive component. Cho’300’s fig. 1F.
Regarding claim 5 and 13, Cho’s 300 further comprising filling the recess with a pre- mold compound. Cho’300’s fig. 1F.
Regarding claims 8 and 16, the passive component is a capacitor. See Cho ‘934’s fig. 2.
Claim(s) 6-7 and 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho ‘300 and Cho ‘934 as applied to claim 1 above, and further in view of TSAI et al. (US 2016/0172281, newly cited, hereinafter, Tsai.)
In regard to claims 6 and 14, the above combination discloses all of the claimed limitations, except, further comprising molding that covers portions of the semiconductor die, the lead frame, the cavity, and the passive component with a mold compound.
Tsai, in fig. 7, for example, discloses an analogous semiconductor package 100 (para [0033], an etched leadframe 110 (para [0037]), a semiconductor 120 formed in the cavity/recessed 118, and a molding material 130 covering portions of the semiconductor die, the lead frame, the cavity, and the passive component with a mold compound (para [0034].) The molding provides structural stability and protection. This is known to one of ordinary skill in the art.
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the application was filed to cover the elements as taught in order to provides structural stability and protection.
Regarding claims 7 and 15, wherein a bottom surface of the passive component is not covered with mold compound. See Cho ‘300’s fig. 1F.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho ‘300 and Cho ‘034as applied to claim 9 above, and further in view of Lee et al. (US 2009/0004774, previously cited, hereinafter, Lee.)
In regard to claim 17, the combination of Akram and Phillips discloses all of the claimed limitations as mentioned above, except further shows the device are formed on the same side of the leadframe (this is another embodiment/species of the invention.) However, the arrangement is known in the art since it provides another way to facilitate the connection the fits the design within the package. For instance, Lee, in figs. 4 and 16, discloses an analogous device including a leadframe 100 (para [0032]), a semiconductor device 104, passive device/capacitors 110 on the leadframe. The devices are disposed on the same side of the leadframe.
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the application was filed to form the devices as taught in order to take the advantage.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Nonetheless, it should be helpful to address the Applicant’s arguments to clarify certain claimed limitations where the previously cited prior art indeed disclosed. Applicant argues, in the remarks’ page 5, that the PCB as disclosed by Akram is not a conductive member. Akram discloses an identical process, for example, the steps of forming the recess in a substrate, PCB, and a semiconductor is formed in the recess. The argument that the substrate PCB is not a conductive member is not accurate. Even though the substrate, PCB may not be made of metal, but it possesses an ability or property to be functioning as a thermal conductive substrate; thus, satisfies the claimed limitation. Nowhere in the claims, 1 and 9, that the conductive member is an electrically conductive member. Otherwise, Akram does teach the method of forming the package as a whole. Thus, simply argue for the conductive limitation does not expedite the process of the prosecution, which has already prolonged. The newly cited references are incorporated herein to show the process of forming the package as currently claimed is well known and the materials of the substrate indeed provide conductive feature, electrically conductive.
Note: The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN W HA whose telephone number is (571)272-1707. The examiner can normally be reached M-T: 8:00AM-6:00PM.
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/NATHAN W HA/Primary Examiner, Art Unit 2814