DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
At the following locations, indicated by the notation [claim(s), line(s)], please make the following changes to provide better clarity, proper grammar, or proper antecedent basis:
[2, 1] change “a interlayer” to “an interlayer”.
[11, 1] change “a interlayer” to “an interlayer”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 5, 13-15, 17, 18, and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al. (US 2023/0343839) (hereafter Kim839).
Regarding claim 1, Kim839 discloses a semiconductor device, comprising:
a semiconductor base 105 (Fig. 1, paragraph 0033) having a first width (horizontal length of 105 in Fig. 1);
a semiconductor device TR2 (Fig. 1, paragraph 0036) over the semiconductor base 105 (Fig. 1), having a second width (horizontal length of TR2 in Fig. 1) that is greater than the first width (horizontal length of 105 in Fig. 1);
a power rail 150 (Fig. 1, paragraph 0036) beneath the semiconductor base 105 (Fig. 1); and
a conductive contact (140, V2, and V1 in Fig. 1) that extends from a top of the semiconductor device TR2 (Fig. 1) to the power rail 150 (Fig. 1).
Regarding claim 2, Kim839 further discloses the semiconductor device of claim 1, further comprising a interlayer dielectric (115 and L1 in Fig. 1, paragraphs 0033 and 0043), around the semiconductor base 105 (Fig. 1) and the semiconductor device TR2 (Fig. 1), that includes a portion of interlayer dielectric (115 and L1 in Fig. 1) between the semiconductor base 105 (Fig. 1) and the conductive contact (140, V2, and V1 in Fig. 1).
Regarding claim 5, Kim839 further discloses the semiconductor device of claim 1, wherein the semiconductor device TR2 (Fig. 1) overhangs two sidewalls of the semiconductor base 105 (Fig. 1).
Regarding claim 13, Kim839 discloses a method of forming a semiconductor device, comprising:
etching (see paragraph 0050, wherein “sacrificial layers SL and channel layers CL may be epitaxially grown from the substrate 105, and patterned through, for example, photolithography and etching (dry and/or wet etching), to obtain a plurality of nanosheet stacks N1-N4 “) a stack (N2 in Fig. 2A, paragraph 0050) of alternating semiconductor layers (SL and CL in Fig. 2A, paragraph 0050) over a semiconductor base 105 (Fig. 2A, paragraph 0050);
forming a protective layer 116 (Fig. 2B, paragraph 0053) on a sidewall of the stack (N2 in Fig. 2B);
etching back (see Fig. 2K and paragraph 0093, wherein “At least a portion of the substrate 105 may be patterned through, for example, photolithography and etching (dry and/or wet etching)”) a sidewall of the semiconductor base 105 (Fig. 2J) to reduce a width of the semiconductor base 105 (Fig. 2K) relative to a width of the stack (N2 in Fig. 2E);
forming a device (TR2 in Fig. 2F, paragraph 0071) from the stack (N2 in Fig. 2E); and
forming a contact (140, V2 and V1 in Fig. 1) that penetrates from above the device (TR2 in Fig. 1) to below the semiconductor base 105 (Fig. 1).
Regarding claim 14, Kim839 further discloses the method of claim 13, wherein forming the protective layer 116 (Fig. 2B, paragraph 0053) includes depositing a protective material 116 (Fig. 2B) on two sidewalls of the stack (N2 in Fig. 2B).
Regarding claim 15, Kim839 further discloses the method of claim 13, wherein etching back (see Fig. 2K and paragraph 0093, wherein “At least a portion of the substrate 105 may be patterned through, for example, photolithography and etching (dry and/or wet etching)”) the sidewall of the semiconductor base 105 (Fig. 2K) includes an isotropic etch (“wet etching” in paragraph 0093) that etches back two sidewalls of the semiconductor base 105 (Fig. 2K).
Regarding claim 17, Kim839 further discloses the method of claim 13, further comprising forming a power rail 150 (Fig. 1, paragraph 0036) in electrical contact with the contact (140, V2, and V1 in Fig. 1).
Regarding claim 18, Kim839 further discloses the method of claim 13, further comprising depositing a dielectric spacer (L3 in Fig. 2K, paragraph 0093) in a gap left by etching back the sidewall of the semiconductor base 105 (Fig. 2J).
Regarding claim 20, Kim839 further discloses the method of claim 1, further comprising: depositing a sacrificial material 115 (Fig. 2A, paragraph 0033) to a height of the semiconductor base 105 (Fig. 2A), before forming the protective layer 116 (Fig. 2B); and removing (see Fig. 2C and paragraph 0056) the sacrificial material 105 (Fig. 2B) after forming the protective layer 116 (Fig. 2B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 16, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim839 as applied to claims 1, 13, and 18 above, and further in view of Chung et al. (US 2021/0375861) (hereafter Chung).
Regarding claim 3, Kim839 further discloses the semiconductor device of claim 1, further comprising: an interlayer dielectric (L1 and L3 in Fig. 1, paragraph 0043) around the semiconductor device TR2 (Fig. 1) and the semiconductor base 105 (Fig. 1).
Kim839 does not disclose a dielectric spacer between the semiconductor base and the conductive contact, the dielectric spacer comprising a different material from the interlayer dielectric.
Chung discloses a dielectric spacer 34 (Fig. 27B, paragraph 0045) between the semiconductor base 50 (Fig. 27B, paragraph 0059) and the conductive contact (112 and 36 in Fig. 27B, paragraph 0079), the dielectric spacer 34 (Fig. 27B, paragraph 0045, wherein “silicon nitride”) comprising a different material from the interlayer dielectric (paragraph 0016, wherein “silicon oxide, such as a high-density plasma (HDP) oxide or the like”; and paragraph 0066, wherein “phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim839 to form a dielectric spacer between the semiconductor base and the conductive contact, the dielectric spacer comprising a different material from the interlayer dielectric, as taught by Chung, since the dielectric spacer/first liners 34 (Chung, Fig. 27B, paragraph 0045) may act as isolation features between subsequently formed conductive contact/backside vias and the semiconductor base/substrate 50 (Chung, Fig. 27B, paragraph 0045).
Regarding claim 16, Kim839 discloses the method of claim 13, however Kim839 does not disclose etching a via, prior to forming the contact, that passes through a portion of a source/drain structure of the device.
Chung discloses etching a via 108 (Fig. 22B, paragraph 0075), prior to forming the contact 112 (Fig. 23B, paragraph 0077), that passes through a portion of a source/drain structure 92 (Fig. 22B, paragraph 0075) of the device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim839 to include etching a via, prior to forming the contact, that passes through a portion of a source/drain structure of the device, as taught by Chung, since exposing (Chung, paragraph 0077) the side surfaces as well as the top surfaces of the epitaxial source/drain regions 92 (Chung, Fig. 22B, paragraph 0077) may increase the contact area between the epitaxial source/drain regions and subsequently formed source/drain contacts.
Regarding claim 19, Kim839 further discloses the method of claim 18, further comprising depositing an interlayer dielectric (L2 in Fig. 2J, paragraph 0089), after forming the device (TR2 in Fig. 2F, paragraph 0071).
Kim839 does not disclose depositing an interlayer dielectric from a different material from the dielectric spacer.
Chung discloses depositing an interlayer dielectric 106 (Fig. 27B, paragraph 0080, wherein “PSG, BSG, BPSG, USG, or the like”) from a different material from the dielectric spacer 52 (Fig. 27B, paragraph 0016, wherein “silicon oxide, such as a high-density plasma (HDP) oxide or the like”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim839 to include depositing an interlayer dielectric from a different material from the dielectric spacer, as taught by Chung, since applicant has not disclosed that the claimed material is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical, which are criteria that have been held to be necessary for material limitations to be prima facie unobvious. The claimed material is considered to be a "preferred" or "optimum" material out of a plurality of well known materials that a person of ordinary skill in the art at the time the invention was made would have found obvious to provide to the invention of the cited prior art reference, using routine experimentation and optimization of the invention. In re Leshin, 125 USPQ 416 (CCPA 1960).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kim839 as applied to claim 1 above, and further in view of Lin et al. (US 2022/0406774) (hereafter Lin).
Regarding claim 4, Kim839 discloses the semiconductor device of claim 1, however Kim839 does not disclose the semiconductor base has a sidewall that is vertically aligned with a sidewall of the semiconductor device.
Lin discloses the semiconductor base (portion of 24 between 68 in Fig. 30C) has a sidewall that is vertically aligned with a sidewall (sidewall of 92 between 81 in Fig. 30C) of the semiconductor device (“NMOS transistors” in paragraph 0038).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim839 to form the semiconductor base has a sidewall that is vertically aligned with a sidewall of the semiconductor device, as taught by Lin, since the first spacers 81 (Lin, Fig. 18A, paragraph 0059) and the second spacers 83 (Lin, Fig. 18A, paragraph 0059) act to self-aligned subsequently formed source drain regions, as well as to protect sidewalls of the fins 66 (Lin, Fig. 18A, paragraph 0059) and/or nanostructure 55 (Lin, Fig. 18A, paragraph 0059) during subsequent processing.
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Kim839 as applied to claim 1 above, and further in view of Kim et al. (US 2022/0028895) (hereafter Kim895).
Regarding claim 6, Kim839 discloses the semiconductor device of claim 1, however Kim839 does not disclose the conductive contact makes electrical contact with a sidewall of the semiconductor device.
Kim895 discloses the conductive contact (CP1, VC, and 150 in Fig. 1B) makes electrical contact with a sidewall (sidewall of 130 in Fig. 1B) of the semiconductor device (“integrated circuit device” in paragraph 0015).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim839 to form the conductive contact makes electrical contact with a sidewall of the semiconductor device, as taught by Kim895, since the electric power (Kim895, paragraph 0038) provided through the external connection terminal may be supplied to the source/drain regions 130 (Kim895, Fig. 1B, paragraph 0038) via the rear wiring structure 180 (Kim895, Fig. 1B, paragraph 0038), the power delivery structure 160 (Kim895, Fig. 1B, paragraph 0038), the buried rail 150 (Kim895, Fig. 1B, paragraph 0038), and the first conductive plug CP1 (Kim895, Fig. 1B, paragraph 0038). In addition, since an integrated circuit device (Kim895, paragraph 0004) that is highly integrated has to have a lot of wiring layers arranged within a small area while stably ensuring insulation distances among the wiring layers.
Regarding claim 7, Kim839 in view of Kim895 discloses the semiconductor device of claim 6, however Kim839 does not disclose the conductive contact makes direct electrical contact with a source/drain structure of the semiconductor device.
Kim895 discloses the conductive contact (CP1, VC, and 150 in Fig. 1B) makes direct electrical contact with a source/drain structure 130 (Fig. 1B, paragraph 0027) of the semiconductor device 1 (Fig. 1B, paragraph 0016).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim839 to form the conductive contact makes direct electrical contact with a source/drain structure of the semiconductor device, as taught by Kim895, since the electric power (Kim895, paragraph 0038) provided through the external connection terminal may be supplied to the source/drain regions 130 (Kim895, Fig. 1B, paragraph 0038) via the rear wiring structure 180 (Kim895, Fig. 1B, paragraph 0038), the power delivery structure 160 (Kim895, Fig. 1B, paragraph 0038), the buried rail 150 (Kim895, Fig. 1B, paragraph 0038), and the first conductive plug CP1 (Kim895, Fig. 1B, paragraph 0038). In addition, since an integrated circuit device (Kim895, paragraph 0004) that is highly integrated has to have a lot of wiring layers arranged within a small area while stably ensuring insulation distances among the wiring layers.
Claims 8-11 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2023/0343839) (hereafter Kim839), in view of Lin et al. (US 2022/0406774) (hereafter Lin).
Regarding claim 8, Kim839 discloses a semiconductor device, comprising:
a pair of adjacent semiconductor bases (second 105 and third 105 from the left corner of Fig. 1, paragraph 0033), each having a first width (horizontal length of 105 in Fig. 1);
a pair of adjacent semiconductor devices (TR2 and TR3 in Fig. 1, paragraph 0036), each positioned over a respective base of the pair of adjacent semiconductor bases (second 105 and third 105 from the left corner of Fig. 1) and each having a second width (horizontal length of TR2 and horizontal length of TR3 in Fig. 1) that is greater than the first width (horizontal length of 105 in Fig. 1);
a power rail 150 (Fig. 1, paragraph 0036) beneath the pair of adject semiconductor bases (second 105 and third 105 from the left corner of Fig. 1); and
a conductive contact (140, V2, and V1 in Fig. 1) that extends from a top of one of the pair of adjacent semiconductor devices (TR2 and TR3 in Fig. 1) to the power rail 150 (Fig. 1).
Kim839 does not disclose the pair of adjacent semiconductor devices each have a sidewall that is vertically aligned with a sidewall of the respective base.
Lin discloses the pair of adjacent semiconductor devices each have a sidewall (sidewall of 92 between 81 in Fig. 30C) that is vertically aligned with a sidewall of the respective base (portion of 24 between 68 in Fig. 30C).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim839 to form the pair of adjacent semiconductor devices each have a sidewall that is vertically aligned with a sidewall of the respective base, as taught by Lin, since the first spacers 81 (Lin, Fig. 18A, paragraph 0059) and the second spacers 83 (Lin, Fig. 18A, paragraph 0059) act to self-aligned subsequently formed source drain regions, as well as to protect sidewalls of the fins 66 (Lin, Fig. 18A, paragraph 0059) and/or nanostructure 55 (Lin, Fig. 18A, paragraph 0059) during subsequent processing.
Regarding claim 9, Kim839 further discloses the semiconductor device of claim 8, wherein the conductive contact (140, V2, and V1 in Fig. 1) is between the semiconductor devices (TR2 and TR3 in Fig. 1).
Regarding claim 10, Kim839 in view of Lin discloses the semiconductor device of claim 8, however Kim839 does not disclose the aligned sidewalls of the respective semiconductor bases are on opposite sides of the respective semiconductor devices.
Lin discloses the aligned sidewalls of the respective semiconductor bases (portion of 24 between 68 in Fig. 30C) are on opposite sides of the respective semiconductor devices (“NMOS transistor” and “PMOS transistor” in paragraph 0038).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim839 to form the aligned sidewalls of the respective semiconductor bases are on opposite sides of the respective semiconductor devices, as taught by Lin, since the first spacers 81 (Lin, Fig. 18A, paragraph 0059) and the second spacers 83 (Lin, Fig. 18A, paragraph 0059) act to self-aligned subsequently formed source drain regions, as well as to protect sidewalls of the fins 66 (Lin, Fig. 18A, paragraph 0059) and/or nanostructure 55 (Lin, Fig. 18A, paragraph 0059) during subsequent processing.
Regarding claim 11, Kim839 further discloses the semiconductor device of claim 8, further comprising a interlayer dielectric (115 and L1 in Fig. 1, paragraphs 0033 and 0043), around the semiconductor base (second 105 and third 105 from the left corner of Fig. 1) and the semiconductor device (TR2 and TR3 in Fig. 1), that includes a portion of interlayer dielectric (115 and L1 in Fig. 1) between the semiconductor base (second 105 and third 105 from the left corner of Fig. 1) and the conductive contact (140, V2, and V1 in Fig. 1).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kim839 in view of Lin as applied to claim 8 above, and further in view of Chung et al. (US 2021/0375861) (hereafter Chung).
Regarding claim 12, Kim839 further discloses the semiconductor device of claim 8, further comprising: an interlayer dielectric (L1 and L3 in Fig. 1, paragraph 0043) around the semiconductor device TR2 (Fig. 1) and the semiconductor base 105 (Fig. 1).
Kim839 and Lin do not disclose a dielectric spacer between the semiconductor base and the conductive contact, the dielectric spacer comprising a different material from the interlayer dielectric.
Chung discloses a dielectric spacer 34 (Fig. 27B, paragraph 0045) between the semiconductor base 50 (Fig. 27B, paragraph 0059) and the conductive contact (112 and 36 in Fig. 27B, paragraph 0079), the dielectric spacer 34 (Fig. 27B, paragraph 0045, wherein “silicon nitride”) comprising a different material from the interlayer dielectric (paragraph 0016, wherein “silicon oxide, such as a high-density plasma (HDP) oxide or the like”; and paragraph 0066, wherein “phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim839 in view of Lin to form a dielectric spacer between the semiconductor base and the conductive contact, the dielectric spacer comprising a different material from the interlayer dielectric, as taught by Chung, since the dielectric spacer/first liners 34 (Chung, Fig. 27B, paragraph 0045) may act as isolation features between subsequently formed conductive contact/backside vias and the semiconductor base/substrate 50 (Chung, Fig. 27B, paragraph 0045).
Conclusion
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813