DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/18/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 4-7, 9, and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Jung (U.S. PG Pub No US2022/0344463A1) (of record) in view of Chang (U.S. PG Pub No US2022/0052157A1) (of record) and Guler (U.S. PG Pub No US2020/0098878A1).
Regarding claim 1, Jung teaches a semiconductor structure [0032, 0112] (refer to fig. 12, annotated fig. 15B below) comprising:
a first dielectric isolation pillar (ST6) fig. 15B [0117] having a first (left) side and a second (right) side opposite the first (left) side (refer to annotated fig. 15B below), the first dielectric isolation pillar being disposed between a pair of p-type field effect transistors (pFETs) (P1-P2) [0033, 0117-0118] (refer to annotated fig. 15B below), the pair of pFETs including adjacent pFET nanosheet stacks (P1-P2 include nanosheet channel stacks) [0116];
a second dielectric isolation pillar (ST4) fig. 15B [0117] disposed between a pair of n-type field effect transistors (nFETs) (N1-N2) [0033, 0117-0118] (refer to annotated fig. 15B below), the pair of nFETs including adjacent nFET nanosheet stacks (N1-N2 include nanosheet channel stacks) [0116];
a first source/drain (S/D) epitaxial region (S/D structure in R1) fig. 12 [0034] having (including) a first contact (CA4) fig. 15B [0116] electrically connected to a backside power delivery network (BSPDN) (comprising M14) fig. 15B [0089, 0098], the first contact (CA4) being disposed on (located in relative proximity to) the first (left) side of the first dielectric isolation pillar (ST6) (refer to annotated fig. 15B below);
a second source/drain epitaxial region (S/D structure in R3) fig. 12 [0034]; and
wherein the first dielectric isolation pillar (ST6) directly contacts sidewalls of the adjacent pFET nanosheet stacks (as shown in annotated fig. 15B below, distal nanosheets directly contact ST’s; further, [0057] of Jung suggests direct contact with insulating layer constituting ST’s and nanosheets of stack), and wherein the second dielectric isolation pillar (ST4) directly contacts sidewalls of the adjacent nFET nanosheet stacks (as shown in annotated fig. 15B below, distal nanosheets directly contact ST’s; further, [0057] of Jung suggests direct contact with insulating layer constituting ST’s and nanosheets of stack) (for the purposes of Examination, fig. 15B has been considered from the orientation shown in annotated fig. 15B below),
[AltContent: arrow][AltContent: textbox (Nanosheets in direct contact with respective ST’s )][AltContent: arrow][AltContent: arrow][AltContent: arrow]
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Annotated fig. 15B of Jung
However, Jung does not explicitly disclose a second S/D epitaxial region (S/D structure in R3) having a second contact electrically connected to back-end-of-line (BEOL) components disposed below the BSPDN (comprising M14), the second contact being disposed on the second (right) side of the first dielectric isolation pillar (ST6), wherein the first dielectric isolation pillar (ST6) and the second dielectric isolation pillar (ST4) have a same uniform width (variable width throughout).
Chang teaches a semiconductor structure (100) fig. 1B [0023] comprising a second S/D epitaxial region (110C) fig. 1B [0023, 0027] having (including) a second contact (comprising 130-II) annotated fig. 1B below [0028] electrically connected to back-end-of-line (134-II) annotated fig. 1B below [0023, 0031] components disposed below the BSPDN (comprising 130-I) annotated fig. 1B below [0028] (134 connected to power supply components [0031]), the second contact (130-II) being disposed on (located in relative proximity to) the second (right) side (‘on’/ near to right side of 114-P representing first dielectric pillar of Jung) annotated fig. 1B below [0021] of the first dielectric isolation pillar (114-P) (for the purposes of Examination, fig. 1B has been considered from the orientation shown in annotated fig. 15B below).
[AltContent: textbox (129-I)][AltContent: arrow][AltContent: arrow][AltContent: textbox (114-P)][AltContent: arrow][AltContent: textbox (130-I)][AltContent: arrow][AltContent: textbox (134-II)][AltContent: arrow][AltContent: textbox (130-II)]
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Reoriented fig. 1B of Chang
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor structure of Jung such that each source/drain structure is provided with a plurality of contacts [0017-0019, 0021-0023] in order to enhance the scaling down of the device [0002] by enhancing the integration density of contact structures [0017] while reducing contact resistance [0017-0018] and enhancing power delivery to individual S/D structures [0031], as taught by Chang.
However, Jung in view of Chang does not explicitly disclose wherein the first dielectric isolation pillar (ST6) and the second dielectric isolation pillar (ST4) (between respective nanosheet stacks) have a same uniform width (variable width throughout).
Guler teaches a semiconductor structure (1000) fig. 10A [0093] wherein the first dielectric isolation pillar (left 1020) fig. 10A [0095] and the second dielectric isolation pillar (right 1020) (positioned between respective nanostructure stacks left/right 1007 [0095]; pillars in direct contact with sidewalls of nanostructures in Jung’s structure) have a same uniform width (each identical 1020 have “a width” which is the same throughout the rectangular 1020 [0095]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the geometry of the isolation pillars separating the nanostructures of the FETs in Jung in view of Chang to be reshaped to have a same, uniform width throughout [0093-0095] in order to enhance the uniformity of transistor cell layout [0031, 0036] so as to increase the integration density of scaled-down transistor components [0001-0004, 0036] without compromising performance [0002, 0038], as taught by Guler.
Regarding claim 4, Jung in view of Chang and Guler teaches the semiconductor structure [0032, 0112] of claim 1. Jung also teaches wherein a dielectric gate cut pillar (ST5) fig. 15B [0117] separates the pair of pFETs (P1-P2) [0033, 0117-0118] from the pair of nFETs (N1-N2) [0033, 0117-0118] (see annotated fig. 15B above).
Regarding claim 5, Jung in view of Chang and Guler teaches the semiconductor structure [0032, 0112] of claim 4. Jung also teaches wherein the dielectric gate cut pillar (ST5) fig. 15B [0117] is vertically aligned with a shallow trench isolation (STI) region (STI region comprising space filled by ST5) fig. 15B [0117] (surfaces of dielectric ST5 considered as identical to surfaces of STI region).
Regarding claim 6, Jung in view of Chang and Guler teaches the semiconductor structure [0032, 0112] of claim 4. Jung also teaches wherein the dielectric gate cut pillar (ST5) fig. 15B [0117] is parallel to the first dielectric isolation pillar (ST6) fig. 15B [0117] and the second dielectric isolation pillar (ST4) fig. 15B [0117].
Regarding claim 7, Jung in view of Chang and Guler teaches the semiconductor structure [0032, 0112] of claim 1. Jung in view of Chang and Guler (with reference to Chang) also teaches wherein the first contact (comprising 129-I) annotated fig. 1B above [0028-0029] is horizontally and vertically offset from the second contact (comprising 130-II) annotated fig. 1B above [0028].
Regarding claim 9, Jung in view of Chang and Guler teaches the semiconductor structure [0032, 0112] of claim 1. Jung also teaches wherein a bottom dielectric isolation (outer layer of two-layer ST structure [0110-0112]) layer directly contacts sidewalls (lower sidewalls of inner ST4/6 layer inset into BDI) of the first (ST6) and second dielectric isolation pillars (ST4).
Regarding claim 17, Jung teaches a method [0032, 0112] (refer to fig. 12, annotated fig. 15B below) comprising (necessarily comprises for the formation of the complete device):
constructing a first dielectric isolation pillar (ST6) fig. 15B [0117] disposed between a pair of p-type field effect transistors (pFETs) (P1-P2) [0033, 0117-0118] (refer to annotated fig. 15B below), the first dielectric isolation pillar (ST6) having a first (left) side and a second (right) side opposite the first (left) side (refer to annotated fig. 15B below), the pair of pFETs including adjacent pFET nanosheet stacks (P1-P2 include nanosheet channel stacks) [0116];
constructing a second dielectric isolation pillar (ST4) fig. 15B [0117] disposed between a pair of n-type field effect transistors (nFETs) (N1-N2) [0033, 0117-0118] (refer to annotated fig. 15B below), the pair of nFETs including adjacent nFET nanosheet stacks (N1-N2 include nanosheet channel stacks) [0116];
forming a first source/drain (S/D) epitaxial region (S/D structure in R1) fig. 12 [0034] having (including) a first contact (CA5) fig. 15B [0116] electrically connected to a backside power delivery network (BSPDN) (comprising M14) fig. 15B [0089, 0098], the first contact being disposed on (in relative proximity to) the (left) side of the first dielectric isolation pillar (ST6);
forming a second source/drain epitaxial region (S/D structure in R3) fig. 12 [0034]; and
wherein the first dielectric isolation pillar (ST6) directly contacts sidewalls of the adjacent pFET nanosheet stacks (as shown in annotated fig. 15B below, distal nanosheets directly contact ST’s; further, [0057] of Jung suggests direct contact with insulating layer constituting ST’s and nanosheets of stack), and wherein the second dielectric isolation pillar (ST4) directly contacts sidewalls of the adjacent nFET nanosheet stacks (as shown in annotated fig. 15B below, distal nanosheets directly contact ST’s; further, [0057] of Jung suggests direct contact with insulating layer constituting ST’s and nanosheets of stack) (for the purposes of Examination, fig. 15B has been considered from the orientation shown in annotated fig. 15B below),
[AltContent: arrow][AltContent: textbox (Nanosheets in direct contact with respective ST’s )][AltContent: arrow][AltContent: arrow][AltContent: arrow]
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Annotated fig. 15B of Jung
However, Jung does not explicitly disclose a second source drain epitaxial region (S/D structure in R3) having a second contact electrically connected to back-end-of-line (BEOL) components disposed below the BSPDN (comprising M14), the second contact being disposed on the second (right) side of the first dielectric isolation pillar (ST6), wherein the first dielectric isolation pillar (ST6) and the second dielectric isolation pillar (ST4) (between respective nanosheet stacks) have a same uniform width (variable width throughout).
Chang teaches a semiconductor structure (100) fig. 1B [0023] comprising a second source/drain epitaxial region (110C) fig. 1B [0023, 0027] having (including) a second contact (comprising 130-II) annotated fig. 1B below [0028] electrically connected to back-end-of-line (134-II) annotated fig. 1B below [0023, 0031] components disposed below the BSPDN (comprising 130-I) annotated fig. 1B below [0028] (134 connected to power supply components [0031]), the second contact (130-II) being disposed on (located near to to) the second (right) side (of pillar 114-P) annotated fig. 1B below [0021] that is opposite to the first (left) side of the first dielectric isolation pillar (114-P) (for the purposes of Examination, fig. 1B has been considered from the orientation shown in annotated fig. 15B below).
[AltContent: textbox (129-I)][AltContent: arrow][AltContent: arrow][AltContent: textbox (114-P)][AltContent: arrow][AltContent: textbox (130-I)][AltContent: arrow][AltContent: textbox (134-II)][AltContent: arrow][AltContent: textbox (130-II)]
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Reoriented fig. 1B of Chang
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor structure of Jung such that each source/drain structure is provided with a plurality of contacts [0017-0019, 0021-0023] in order to enhance the scaling down of the device [0002] by enhancing the integration density of contact structures [0017] while reducing contact resistance [0017-0018] and enhancing power delivery to individual S/D structures [0031], as taught by Chang.
However, Jung in view of Chang does not explicitly disclose wherein the first dielectric isolation pillar (ST6) and the second dielectric isolation pillar (ST4) (between respective nanosheet stacks) have a same uniform width (variable width throughout).
Guler teaches a semiconductor structure (1000) fig. 10A [0093] wherein the first dielectric isolation pillar (left 1020) fig. 10A [0095] and the second dielectric isolation pillar (right 1020) (positioned between respective nanostructure stacks left/right 1007 [0095]; pillars in direct contact with sidewalls of nanostructures in Jung’s structure) have a same uniform width (each identical 1020 have “a width” which is the same throughout the rectangular 1020 [0095]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the geometry of the isolation pillars separating the nanostructures of the FETs in Jung in view of Chang to be reshaped to have a same, uniform width throughout [0093-0095] in order to enhance the uniformity of transistor cell layout [0031, 0036] so as to increase the integration density of scaled-down transistor components [0001-0004, 0036] without compromising performance [0002, 0038], as taught by Guler.
Regarding claim 18, Jung in view of Chang and Guler teaches the method of claim 17. Jung also teaches wherein a dielectric gate cut pillar (ST5) fig. 15B [0117] separates the pair of pFETs (P1-P2) [0033, 0117-0118] from the pair of nFETs (N1-N2) [0033, 0117-0118] (see annotated fig. 15B above).
Regarding claim 19, Jung in view of Chang and Guler teaches the method [0032, 0112] of claim 18. Jung also teaches wherein the dielectric gate cut pillar (ST5) fig. 15B [0117] is vertically aligned with an shallow trench isolation (STI) region (STI region comprising space filled by ST5) fig. 15B [0117] (surfaces of dielectric ST5 considered as identical to surfaces of STI region; and
wherein the dielectric gate cut pillar (ST5) fig. 15B [0117] is parallel to both the first dielectric isolation pillar (ST6) fig. 15B [0117] and the second dielectric isolation pillar (ST4) fig. 15B [0117].
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Jung (U.S. PG Pub No US2022/0344463A1) (of record) modified by Chang (U.S. PG Pub No US2022/0052157A1) (of record) and Guler (U.S. PG Pub No US2020/0098878A1), as applied in claim 1 above, and further in view of Reznicek (U.S. PG Pub No US2021/0226032A1).
Regarding claim 2, Jung in view of Chang and Guler teaches the semiconductor structure [0032, 0112] of claim 1. Jung also teaches wherein a metal gate (MG) (gate material G01 comprising metal nitride) annotated fig. 15B [0043, 0051] (see also fig. 12) directly contacts sidewalls of the first (ST6) fig. 15B [0117] and second (ST4) fig. 15B [0117] dielectric isolation pillars (see fig. 15B).
However, Jung does not explicitly disclose wherein the metal gate (G01 material comprising metal nitride) is a high-k metal gate (material and dielectric constant not explicitly disclosed).
Reznicek teaches a semiconductor structure (100A) fig. 12 [0057, 0066] wherein the metal gate (HKMG comprising metal nitride such as TiN [0062]) is a high-k metal gate (metal nitride such as TiN of work function metal WFM layer 902 taught as high-k material [0062]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the metal nitride layer of the metal gate of Jung to explicitly comprise a high-k metal nitride material such as titanium nitride [0062] such that the metal gate is a high-k metal gate (HKMG) in order to enable work function modulation [0062] of the transistor structure so as to optimally regulate electron flow therein [0059], as taught by Reznicek.
Regarding claim 3, Jung in view of Chang, Guler, and Reznicek teaches the semiconductor structure [0032, 0112] of claim 2. Jung in view of Reznicek also teaches wherein the first (ST6) fig. 15B [0117] and second (ST4) fig. 15B [0117] dielectric isolation pillars each extend from a top surface of the HKMG (gate material G01 comprising metal nitride, ensured high-k by Reznicek) annotated fig. 15B [0043, 0051] (see also fig. 12) to a bottom surface of a shallow trench isolation (STI) region (STI region comprising space filled by ST6 and ST4) fig. 15B [0117] (surfaces of dielectric pillars ST4, ST6 considered as identical to surfaces of STI region).
Claims 8 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jung (U.S. PG Pub No US2022/0344463A1) (of record) modified by Chang (U.S. PG Pub No US2022/0052157A1) (of record) and Guler (U.S. PG Pub No US2020/0098878A1), as applied in claims 1 and 17 above, and further in view of Xie (U.S. PG Pub No US2021/0210349A1) (of record).
Regarding claim 8, Jung in view of Chang and Guler teaches the semiconductor structure [0032, 0112] of claim 1. However, Jung does not explicitly disclose wherein a bottom dielectric isolation (BDI) layer directly contacts respective top surfaces of the first source/drain epitaxial region (S/D structure in R1) fig. 12 [0034] and the second source/drain epitaxial region (S/D structure in R3) fig. 12 [0034].
Xie teaches a semiconductor structure [see title, fig. 13] wherein a bottom dielectric isolation (132) fig. 13 [0055] layer directly contacts respective top (peripheral) surfaces of the first source/drain epitaxial region (left 130) fig. 13 [0055-0056] and the second source/drain epitaxial region (right 130) fig. 13 [0055-0056].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the FET device of Jung such that lower source/drain regions [0055] are capped with a dielectric isolation layer [0055] in order to enable the formation of an upper, segmented source/drain region thereon [0056] – thereby enhancing the vertical integration density of source/drain regions and other transistor components [0055-0056] of the CFET architecture [0001-0005], as taught by Xie.
Regarding claim 20, Jung in view of Chang and Guler teaches the method [0032, 0112] of claim 17. However, Jung does not explicitly disclose wherein a bottom dielectric isolation (BDI) layer directly contacts respective top surfaces of the first source/drain epitaxial region (S/D structure in R1) fig. 12 [0034] and the second source/drain epitaxial region (S/D structure in R3) fig. 12 [0034].
Xie teaches a method of forming a semiconductor structure [see title, fig. 13] wherein a bottom dielectric isolation (132) fig. 13 [0055] layer directly contacts respective top (peripheral) surfaces of the first source/drain epitaxial region (left 130) fig. 13 [0055-0056] and the second source/drain epitaxial region (right 130) fig. 13 [0055-0056].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the FET device of Jung such that lower source/drain regions [0055] are capped with a dielectric isolation layer [0055] in order to enable the formation of an upper, segmented source/drain region thereon [0056] – thereby enhancing the vertical integration density of source/drain regions and other transistor components [0055-0056] of the CFET architecture [0001-0005], as taught by Xie.
Claims 10 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Jung (U.S. PG Pub No US2022/0344463A1) (of record) in view of Guler (U.S. PG Pub No US2020/0098878A1), Chang (U.S. PG Pub No US2022/0052157A1) (of record), and Paul (U.S. PG Pub No US2021/0020644A1) (of record).
Regarding claim 10, Jung teaches a semiconductor structure [0032, 0112] (refer to fig. 12, annotated fig. 15B below) comprising:
at least one a dielectric isolation pillar (ST6) fig. 15B [0117] disposed between a pair of field effect transistors (nFETs) (P1-P2) [0033, 0117-0118] (refer to annotated fig. 15B below), including a first FET (N1) and a second FET (N2), the pair of FETs (N1-N2) having the same conductivity type (n-type [0033, 0117-0118], the at least one dielectric isolation pillar (ST6) being included in a plurality of dielectric isolation pillars (ST4, ST6) [0117], the at least one dielectric isolation pillar (ST6) having a first (left) sidewall and a second (right) sidewall in opposed relation to the first (left) sidewall (refer to annotated fig. 15B below for orientation);
a first source/drain (S/D) epitaxial region (S/D structure in R2) fig. 12 [0034] of the first FET (N1) having (including) a first contact (CA5) fig. 15B [0116] electrically connected to a backside power delivery network (BSPDN) (comprising M15) fig. 15B [0089, 0098], the first contact (CA5) being disposed (adjacent) the first sidewall (left sidewall) of the at least one dielectric isolation pillar (ST6);
a second S/D source/drain epitaxial region (S/D structure in R3) fig. 12 [0034] of the second FET (N1), wherein the backside power delivery network is disposed on (supported by) a backside (shown as bottom) of the semiconductor structure opposite a/the frontside (shown as top) (for the purposes of Examination, fig. 15B has been considered from the orientation shown in annotated fig. 15B below).
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Annotated fig. 15B of Jung
However, Jung does not explicitly disclose the plurality of dielectric isolation pillars (ST4, ST6) having a same uniform width,
the first contact (CA5) being disposed along a first sidewall of the at least one dielectric isolation pillar (ST6); and
a second S/D epitaxial region (S/D structure in R3) having a second contact electrically connected to frontside back-end-of-line (BEOL) interconnect components disposed on a frontside of the semiconductor structure, the second contact being disposed along a second sidewall of the at least one dielectric isolation pillar (ST6).
Guler teaches a semiconductor structure (1000) fig. 10A [0093] wherein the plurality of dielectric isolation pillars (left and right 1020’s) fig. 10A [0095] and the second dielectric isolation pillar (right 1020) have a same uniform width (each identical 1020 have “a width” which is the same throughout the rectangular 1020 [0095]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the geometry of the isolation pillars separating the nanostructures of the FETs in Jung to be reshaped to have a same, uniform width throughout [0093-0095] in order to enhance the uniformity of transistor cell layout [0031, 0036] so as to increase the integration density of scaled-down transistor components [0001-0004, 0036] without compromising performance [0002, 0038], as taught by Guler.
However, Jung in view of Guler does not explicitly disclose,
the first contact (CA5) being disposed along a first sidewall of the at least one dielectric isolation pillar (ST6); and
a second S/D epitaxial region (S/D structure in R3) having a second contact electrically connected to frontside back-end-of-line (BEOL) interconnect components disposed on a frontside of the semiconductor structure, and the second contact being disposed along a second sidewall of the at least one dielectric isolation pillar (ST6).
Chang teaches a semiconductor structure (100) fig. 1B [0023] comprising a second S/D epitaxial region (110C) fig. 1B [0023, 0027] of the second FET (comprising right stack of 120s with 110C) fig. 1B [0023] (including) a second contact (comprising 130-II) annotated fig. 1B below [0028] electrically connected (through conductive 110C) to frontside back-end-of-line (BEOL) interconnect components (136) annotated fig. 1B below [0023, 0032] components disposed on a frontside (shown as top) of the semiconductor structure (comprising 130-I) annotated fig. 1B below [0028] (for the purposes of Examination, fig. 1B has been considered from the orientation shown in annotated fig. 15B below).
[AltContent: textbox (136)][AltContent: arrow][AltContent: textbox (129-I)][AltContent: arrow][AltContent: arrow][AltContent: textbox (114-P)][AltContent: arrow][AltContent: textbox (130-I)][AltContent: arrow][AltContent: textbox (130-II)]
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Reoriented fig. 1B of Chang
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor structure of Jung in view of Guler such that each source/drain structure is provided with a plurality of contacts [0017-0019, 0021-0023] in order to enhance the scaling down of the device [0002] by enhancing the integration density of contact structures [0017] while reducing contact resistance [0017-0018] and enhancing power delivery to individual S/D structures [0031], as taught by Chang.
However, Jung in view of Guler and Chang does not explicitly disclose the first contact (CA5) being disposed along a first sidewall of the at least one dielectric isolation pillar (ST6); and
the second contact (comprising 136 incorporated from Cheng) being disposed along a second sidewall of the at least one dielectric isolation pillar (ST6).
Paul teaches a semiconductor structure [0046-0047] comprising the first contact (right 192) fig. 6 [0047] being disposed along a first (left) sidewall of the at least one dielectric isolation pillar (160) fig. 6 [0046-0047]; and
the second contact (left 192) being disposed along a second (right) sidewall of the at least one dielectric isolation pillar (160).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have expanded both the contacts and dielectric pillars of Jung in view of Guler and Chang such that they border each other between adjected FETs [0046-0047] in order to improve the relative density of FET circuitry [0004] to enhance device integration density [0004]; scaling down devices while providing better control with lower leakage current, faster operations, and lower output resistance [0004] – among other features [0004-0009] - as taught by Paul.
Regarding claim 13, Jung in view of Guler, Chang, and Paul teaches the semiconductor structure [0032, 0112] of claim 10. Jung in view of Guler, Chang, and Paul (with reference to Guler) also teaches wherein a dielectric gate cut pillar (represented by right 120) fig. 10A [0093-0095] is vertically aligned (borders) with a shallow trench isolation (STI) region (1006) fig. 10A [0093] (when plurality of dielectric isolation pillars of Jung modified to have uniform width by Guler)
Regarding claim 14, Jung in view of Guler, Chang, and Paul teaches the semiconductor structure [0032, 0112] of claim 13. Jung also teaches wherein the dielectric gate cut pillar (ST5) fig. 15B [0117] is parallel to the at least one dielectric isolation pillar (ST6) fig. 15B [0117].
Regarding claim 15, Jung in view of Chang and Paul teaches the semiconductor structure [0032, 0112] of claim 10. Jung in view of Chang and Paul (with reference to Chang) also teaches wherein the first contact (comprising 129-I) annotated fig. 1B above [0028-0029] is horizontally and vertically offset from the second contact (comprising 130-II) annotated fig. 1B above [0028].
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Jung (U.S. PG Pub No US2022/0344463A1) (of record) modified by Chang (U.S. PG Pub No US2022/0052157A1) (of record), Guler (U.S. PG Pub No US2020/0098878A1), as applied in claim 1 above, and further in view of Reznicek (U.S. PG Pub No US2021/0226032A1).
Regarding claim 11, Jung in view of Guler, Chang, and Paul teaches the semiconductor structure [0032, 0112] of claim 10. Jung also teaches wherein a metal gate (MG) (gate material G01 comprising metal nitride) annotated fig. 15B [0043, 0051] (see also fig. 12) directly contacts the first (left) sidewall and the second (right) sidewall of the at least one dielectric isolation pillar (ST4 and/or ST6) fig. 15B [0117].
However, Jung does not explicitly disclose wherein the metal gate (G01 material comprising metal nitride) is a high-k metal gate HKMG (material and dielectric constant not explicitly disclosed).
Reznicek teaches a semiconductor structure (100A) fig. 12 [0057, 0066] wherein the metal gate (HKMG comprising metal nitride such as TiN [0062]) is a high-k metal gate HKMG (metal nitride such as TiN of work function metal WFM layer 902 taught as high-k material [0062]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the metal nitride layer of the metal gate of Jung to explicitly comprise a high-k metal nitride material such as titanium nitride [0062] such that the metal gate is a high-k metal gate (HKMG) in order to enable work function modulation [0062] of the transistor structure so as to optimally regulate electron flow therein [0059], as taught by Reznicek.
Regarding claim 12, Jung in view of Guler, Chang, and Paul teaches the semiconductor structure [0032, 0112] of claim 10. Jung also teaches wherein the at least one dielectric isolation pillar (ST4 and/or ST6) fig. 15B [0117] extends from a top surface of the MG (gate material G01 comprising metal nitride) see annotated fig. 15B orientation [0043, 0051] (see also fig. 12) to a bottom surface of a shallow trench isolation (STI) region (STI region comprising space filled by ST6 and ST4) fig. 15B [0117] (surfaces of dielectric pillars ST4, ST6 considered as identical to surfaces of STI region).
Reznicek teaches a semiconductor structure (100A) fig. 12 [0057, 0066] wherein the metal gate (HKMG comprising metal nitride such as TiN [0062]) is a high-k metal gate HKMG (metal nitride such as TiN of work function metal WFM layer 902 taught as high-k material [0062]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the metal nitride layer of the metal gate of Jung to explicitly comprise a high-k metal nitride material such as titanium nitride [0062] such that the metal gate is a high-k metal gate (HKMG) in order to enable work function modulation [0062] of the transistor structure so as to optimally regulate electron flow therein [0059], as taught by Reznicek.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Jung (U.S. PG Pub No US2022/0344463A1) (of record) modified by Guler (U.S. PG Pub No US2020/0098878A1), Chang (U.S. PG Pub No US2022/0052157A1) (of record), and Paul (U.S. PG Pub No US2021/0020644A1) (of record), as applied in claim 10 above, and further in view of Xie (U.S. PG Pub No US2021/0210349A1) (record).
Regarding claim 16, Jung in view of Guler, Chang, and Paul teaches the semiconductor structure [0032, 0112] of claim 10. However, Jung does not explicitly disclose wherein a bottom dielectric isolation (BDI) layer directly contacts respective top surfaces of the first source/drain epitaxial region (S/D structure in R1) fig. 12 [0034] and the second source/drain epitaxial region (S/D structure in R3) fig. 12 [0034].
Xie teaches a semiconductor structure [see title, fig. 13] wherein a bottom dielectric isolation (132) fig. 13 [0055] layer directly contacts respective top (peripheral) surfaces of the first source/drain epitaxial region (left 130) fig. 13 [0055-0056] and the second source/drain epitaxial region (right 130) fig. 13 [0055-0056].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the FET device of Jung such that lower source/drain regions [0055] are capped with a dielectric isolation layer [0055] in order to enable the formation of an upper, segmented source/drain region thereon [0056] – thereby enhancing the vertical integration density of source/drain regions and other transistor components [0055-0056] of the CFET architecture [0001-0005], as taught by Xie.
Response to Arguments
Applicant’s arguments, see pages 1-2, filed 05/18/2026, with respect to the rejection(s) of claim(s) 1, 10, and 17 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Guler (U.S. PG Pub No US2020/0098878A1) under 35 U.S.C. 103.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Newly-added Liaw (U.S. PG Pub No US2021/0098338A1), Zhang (U.S. PG Pub No US2021/0210489A1), and Ghani (U.S. PG Pub No US2022/0320085A1) teach other examples of nanostructure FETs separated by dielectric isolation pillar(s), wherein the dielectric isolation pillar(s) is shown with a uniform width throughout.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 06/11/2026
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