DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 9, and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jung (U.S. PG Pub No US2022/0344463A1).
Regarding claim 1, Jung teaches a semiconductor structure [0032, 0112] (refer to fig. 12, annotated fig. 15B below) comprising:
a first dielectric isolation pillar (ST6) fig. 15B [0117] disposed between a pair of p-type field effect transistors (pFETs) (P1-P2) [0033, 0117-0118] (refer to annotated fig. 15B below);
a second dielectric isolation pillar (ST4) fig. 15B [0117] disposed between a pair of n-type FETs (nFETs) (N1-N2) [0033, 0117-0118] (refer to annotated fig. 15B below);
a first source/drain (S/D) epi region (S/D structure in R1) fig. 12 [0034] having (including) a first contact (CA5) fig. 15B [0116] electrically connected to a backside power delivery network (BSPDN) (comprising M14) fig. 15B [0089, 0098], the first contact being disposed on (supported by) one (top) side of the first dielectric isolation pillar (ST6); and
a second S/D epi region (S/D structure in R3) fig. 12 [0034] having (including) a second contact (CA4) fig. 15B [0116] electrically connected to back-end-of-line (BEOL) components (comprising M14), the second contact being disposed on (supported by) the other (bottom) side of the first dielectric isolation pillar (ST6).
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Annotated fig. 15B of Jung
Regarding claim 2, Jung teaches a semiconductor structure [0032, 0112] of claim 1. Jung also teaches wherein a high-k metal gate (HKMG) (gate material G01 comprising metal nitride) annotated fig. 15B [0043, 0051] (see also fig. 12) directly contacts sidewalls of the first (ST6) fig. 15B [0117] and second (ST4) fig. 15B [0117] dielectric isolation pillars (see fig. 15B).
For the purposes of Examination, it is considered well-known in the art that a “metal-nitride layer” [0053 Jung] is a high-k metal-material (HKM).
Regarding claim 3, Jung teaches a semiconductor structure [0032, 0112] of claim 2. Jung also teaches wherein the first (ST6) fig. 15B [0117] and second (ST4) fig. 15B [0117] dielectric isolation pillars each extend from a top surface of the HKMG (gate material G01 comprising metal nitride) annotated fig. 15B [0043, 0051] (see also fig. 12) to a bottom surface of a shallow trench isolation (STI) region (STI region comprising space filled by ST6 and ST4) fig. 15B [0117] (surfaces of dielectric pillars ST4, ST6 considered as identical to surfaces of STI region).
Regarding claim 4, Jung teaches a semiconductor structure [0032, 0112] of claim 1. Jung also teaches wherein a dielectric gate cut pillar (ST5) fig. 15B [0117] separates the pair of pFETs (P1-P2) [0033, 0117-0118] from the pair of nFETs (N1-N2) [0033, 0117-0118] (see annotated fig. 15B above).
Regarding claim 5, Jung teaches a semiconductor structure [0032, 0112] of claim 4. Jung also teaches wherein the dielectric gate cut pillar (ST5) fig. 15B [0117] is vertically aligned with an STI region (STI region comprising space filled by ST5) fig. 15B [0117] (surfaces of dielectric ST5 considered as identical to surfaces of STI region).
Regarding claim 6, Jung teaches a semiconductor structure [0032, 0112] of claim 4. Jung also teaches wherein the dielectric gate cut pillar (ST5) fig. 15B [0117] is parallel to both the first (ST6) fig. 15B [0117] and second dielectric isolation pillars (ST4) fig. 15B [0117].
Regarding claim 7, Jung teaches a semiconductor structure [0032, 0112] of claim 1. Jung also teaches wherein the (top of) first contact (CA5) fig. 15B [0116] is horizontally and vertically offset from the (bottom of) second contact (CA4) fig. 15B [0116].
Regarding claim 9, Jung teaches a semiconductor structure [0032, 0112] of claim 1. Jung also teaches wherein a bottom dielectric isolation (outer layer of two-layer ST structure [0110-0112]) layer directly contacts sidewalls (lower sidewalls of inner ST4/6 layer inset into BDI) of the first (ST6) and second dielectric isolation pillars (ST4).
Regarding claim 17, Jung teaches a method [0032, 0112] (refer to fig. 12, annotated fig. 15B below) comprising (necessarily comprises for the formation of the complete device):
constructing a first dielectric isolation pillar (ST6) fig. 15B [0117] disposed between a pair of p-type field effect transistors (pFETs) (P1-P2) [0033, 0117-0118] (refer to annotated fig. 15B below);
constructing a second dielectric isolation pillar (ST4) fig. 15B [0117] disposed between a pair of n-type FETs (nFETs) (N1-N2) [0033, 0117-0118] (refer to annotated fig. 15B below);
forming a first source/drain (S/D) epi region (S/D structure in R1) fig. 12 [0034] having (including) a first contact (CA5) fig. 15B [0116] electrically connected to a backside power delivery network (BSPDN) (comprising M14) fig. 15B [0089, 0098], the first contact being disposed on (supported by) one (top) side of the first dielectric isolation pillar (ST6); and
forming a second S/D epi region (S/D structure in R3) fig. 12 [0034] having (including) a second contact (CA4) fig. 15B [0116] electrically connected to back-end-of-line (BEOL) components (comprising M14), the second contact being disposed on (supported by) the other (bottom) side of the first dielectric isolation pillar (ST6).
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Annotated fig. 15B of Jung
Regarding claim 18, Jung teaches the method of claim 17. Jung also teaches wherein a dielectric gate cut pillar (ST5) fig. 15B [0117] separates the pair of pFETs (P1-P2) [0033, 0117-0118] from the pair of nFETs (N1-N2) [0033, 0117-0118] (see annotated fig. 15B above).
Regarding claim 19, Jung teaches the method [0032, 0112] of claim 18. Jung also teaches wherein the dielectric gate cut pillar (ST5) fig. 15B [0117] is vertically aligned with an STI region (STI region comprising space filled by ST5) fig. 15B [0117] (surfaces of dielectric ST5 considered as identical to surfaces of STI region; and
wherein the dielectric gate cut pillar (ST5) fig. 15B [0117] is parallel to both the first (ST6) fig. 15B [0117] and second dielectric isolation pillars (ST4) fig. 15B [0117].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 8 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jung (U.S. PG Pub No US2022/0344463A1), as applied in claims 1 and 17 above, in view of Xie (U.S. PG Pub No US2021/0210349A1).
Regarding claim 8, Jung teaches a semiconductor structure [0032, 0112] of claim 1. However, Jung does not explicitly disclose teaches wherein a bottom dielectric isolation (BDI) layer directly contacts a top surface of the first and second S/D epi regions (S/D structure in R1, R3) fig. 12 [0034].
Xie teaches a semiconductor structure [see title, fig. 13] wherein a bottom dielectric isolation (132) fig. 13 [0055] layer directly contacts a top surface of the first and second S/D epi regions ((left/right 130s) fig. 13 [0055-0056].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the FET device of Jung such that lower source/drain regions [0055] are capped with a dielectric isolation layer [0055] in order to enable the formation of an upper, segmented source/drain region thereon [0056] – thereby enhancing the vertical integration density of source/drain regions and other transistor components [0055-0056] of the CFET architecture [0001-0005], as taught by Xie.
Regarding claim 20, Jung teaches the method [0032, 0112] of claim 17. Jung also teaches wherein a bottom dielectric isolation (BDI) layer directly contacts a top surface of the first and second S/D epi regions (S/D structure in R1, R3) fig. 12 [0034].
Xie teaches a method of forming a semiconductor structure [see title, fig. 13] wherein a bottom dielectric isolation (132) fig. 13 [0055] layer directly contacts a top surface of the first and second S/D epi regions (left/right 130s) fig. 13 [0055-0056].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the FET device of Jung such that lower source/drain regions [0055] are capped with a dielectric isolation layer [0055] in order to enable the formation of an upper, segmented source/drain region thereon [0056] – thereby enhancing the vertical integration density of source/drain regions and other transistor components.
Claims 10-15 are rejected under 35 U.S.C. 103 as being unpatentable over Jung (U.S. PG Pub No US2022/0344463A1) in view of Paul (U.S. PG Pub No US2021/0020644A1).
Regarding claim 10, Jung teaches a semiconductor structure [0032, 0112] (refer to fig. 12, annotated fig. 15B below) comprising:
at least one a dielectric isolation pillar (ST6 and/or ST4) fig. 15B [0117] disposed between a pair of p-type field effect transistors (pFETs) (P1-P2) [0033, 0117-0118] (refer to annotated fig. 15B below);
a first source/drain (S/D) epi region (S/D structure in R1) fig. 12 [0034] having (including) a first contact (CA5) fig. 15B [0116] electrically connected to a backside power delivery network (BSPDN) (comprising M14) fig. 15B [0089, 0098], the first contact (CA5) being disposed (adjacent) a first sidewall (left sidewall) of the at least one dielectric isolation pillar (ST6 and/or ST4);
a second S/D epi region (S/D structure in R3) fig. 12 [0034] having (including) a second contact (CA4) fig. 15B [0116] electrically connected to back-end-of-line (BEOL) components (comprising M14), the second contact being disposed (adjacent) a second sidewall (right sidewall) of the at least one dielectric isolation pillar (ST6 and/or ST4), wherein the first (left) sidewall is in opposed relation to the second (right) sidewall.
However, Jung does not explicitly disclose the first contact (CA5) being disposed along a first sidewall of the at least one dielectric isolation pillar (ST6 and/or ST4); and
the second contact (CA4) being disposed along a second sidewall of the at least one dielectric isolation pillar (ST6 and/or ST4).
Paul teaches a semiconductor structure [0046-0047] comprising the first contact (right 192) fig. 6 [0047] being disposed along a first (left) sidewall of the at least one dielectric isolation pillar (160) fig. 6 [0046-0047]; and
the second contact (left 192) being disposed along a second (right) sidewall of the at least one dielectric isolation pillar (160).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have expanded both the contacts and dielectric pillars of Jung such that they border each other between adjected FETs [0046-0047] in order to improve the relative density of FET circuitry [0004] to enhance device integration density [0004]; scaling down devices while providing better control with lower leakage current, faster operations, and lower output resistance [0004] – among other features [0004-0009] - as taught by Paul.
Regarding claim 11, Jung teaches a semiconductor structure [0032, 0112] of claim 10. Jung also teaches wherein a high-k metal gate (HKMG) (gate material G01 comprising metal nitride) annotated fig. 15B [0043, 0051] (see also fig. 12) directly contacts sidewalls of the at least one dielectric isolation pillar (ST4 and/or ST6) fig. 15B [0117].
For the purposes of Examination, it is considered well-known in the art that a “metal-nitride layer” [0053 Jung] is a high-k metal-material (HKM).
Regarding claim 12, Jung teaches a semiconductor structure [0032, 0112] of claim 10. Jung also teaches wherein the at least one dielectric isolation pillar (ST4 and/or ST6) fig. 15B [0117] extends from a top surface of the HKMG (gate material G01 comprising metal nitride) annotated fig. 15B [0043, 0051] (see also fig. 12) to a bottom surface of a shallow trench isolation (STI) region (STI region comprising space filled by ST6 and ST4) fig. 15B [0117] (surfaces of dielectric pillars ST4, ST6 considered as identical to surfaces of STI region).
Regarding claim 13, Jung teaches a semiconductor structure [0032, 0112] of claim 10. Jung also teaches wherein a dielectric gate cut pillar (ST5) fig. 15B [0117] separates the pair of pFETs (P1-P2) [0033, 0117-0118] from the pair of nFETs (N1-N2) [0033, 0117-0118] (see annotated fig. 15B above).
Regarding claim 14, Jung teaches a semiconductor structure [0032, 0112] of claim 13. Jung also teaches wherein the dielectric gate cut pillar (ST5) fig. 15B [0117] is parallel to the at least one dielectric isolation pillar (ST4, ST6) fig. 15B [0117].
Regarding claim 15, Jung teaches a semiconductor structure [0032, 0112] of claim 10. Jung also teaches wherein the (top of) first contact (CA5) fig. 15B [0116] is horizontally and vertically offset from the (bottom of) second contact (CA4) fig. 15B [0116].
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Jung (U.S. PG Pub No US2022/0344463A1) modified by Paul (U.S. PG Pub No US2021/0020644A1), as applied in claim 10 above, and further in view of Xie (U.S. PG Pub No US2021/0210349A1).
Regarding claim 16, Jung in view of Paul teaches a semiconductor structure [0032, 0112] of claim 10. However, Jung in view of Paul does not explicitly disclose wherein a bottom dielectric isolation (BDI) layer directly contacts a top surface of the first and second S/D epi regions (S/D structure in R1, R3) fig. 12 [0034].
Xie teaches a semiconductor structure [see title, fig. 13] wherein a bottom dielectric isolation (132) fig. 13 [0055] layer directly contacts a top surface of the first and second S/D epi regions (left/right 130s) fig. 13 [0055-0056].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the FET device of Jung such that lower source/drain regions [0055] are capped with a dielectric isolation layer [0055] in order to enable the formation of an upper, segmented source/drain region thereon [0056] – thereby enhancing the vertical integration density of source/drain regions and other transistor components.
Conclusion
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 10/29/2025
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892