Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 7-19 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2024/0014166) in view of Chung et al. (US 2020/0411472).
As for claims 1-2, Kim et al. disclose in Fig. 3 and the related text a semiconductor device, comprising:
a base substrate 3 including an interconnection layer 9/13;
a plurality of chips CH1a/CH2a/CH3a/CH4a stacked on the base substrate; and
an protective film 50a’/55a between each adjacent pair of chips in the plurality of chips stacked on the base substrate and on side surfaces of at least each chip in the plurality of chips other than an uppermost chip in the plurality of chips (Fig. 3),
wherein a lowermost chip CH1a in the plurality of chips has a metal pad PD-Bf electrically connected to the interconnection layer (Fig. 3),
each chip in an adjacent pair of chips CH1a/CH2a/CH3a/CH4a in the plurality of chips stacked on the base substrate 3 has an electrode PD_Db/42 contacting an electrode DP_Df/via of 36 of the other chip in the adjacent pair (Fig. 3), a first chip CH1a in the plurality of chips CH1a/CH2a/CH3a/CH4a comprises a first memory array chip and a first peripheral circuit chip directly bonded to the first memory array chip,
a second chip CH2a in the plurality of chips CH1a/CH2a/CH3a/CH4a comprises a second memory array chip and a second peripheral circuit chip directly bonded to the second memory array chip [0039],
the first chip and second chip CH1a/CH2a are directly bonded to each other such that the first memory array chip is directly bonded to the second peripheral chip (Fig. 3),
a first electrode PD_Db/42 is on a first (upper) surface of the first chip facing toward a second (lower) surface of the second chip CH2a (fig. 3),
a second electrode PD_Df/via of 36 on the second surface of the second chip (fig. 3),
the first electrode PD_Db/42 is directly bonded to the second electrode PD_Df/ via of 36 without a solder ball connection therebetween (fig. 3), and
there is no polymeric adhesive layer between the first chip and the second chip (Fig. 3).
Kim et al. do not disclose the protection layer is an inorganic protection layer, wherein the inorganic protective film comprises at least one of SiO2, SiOC, SiN, and SiCN.
Chung et al. teach in Fig. 14 and the related text a protection layer 140/130/132/134/136 is an inorganic protection layer [0048], wherein the inorganic protective film comprises at least one of SiO2, SiOC, SiN, and SiCN [0048].
Kim et al. and Chung et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Kim et al. to have inorganic material as material of the protection layer, as taught by Chung et al., in order to improve device performance and reduce device defects (Chung et al.: [0051]).
As for claims 3-4, Kim et al. disclose the semiconductor device according to claim 1, wherein the inorganic protective film is an insulating film formed by a coating process, wherein the coating process is a spin coating process.
Claims 3-4 is drawn to a process by which the product is made. Even though product by process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product by process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. Because the product by process does not change the end product, Applicant’s claimed invention does not distinguish over prior art. See MPEP § 2113.
As for claim 7, Kim et al. disclose the semiconductor device according to claim 1, wherein the first electrode and the second electrode of the first and second chips are each a through-silicon via (Fig. 3).
As for claim 8, Kim et al. disclose the semiconductor device according to claim 1, wherein the electrode of each chip in the plurality of chips is a through-silicon via (Fig. 3).
As for claims 9, 12 and 18, Kim et al. disclose the semiconductor device according to claim 17, except wherein a thickness of the inorganic protective film on the side surfaces of the lowermost memory chip is thicker than a thickness of the inorganic protective film on the side surfaces of the uppermost memory chip; and the number of layers in the plurality of layers on the side surfaces of the lowermost chip is equal to the number of chips in the plurality of chips stacked on the substrate.
Chung et al. teach in Fig. 14 and the related text a thickness of the protective film 130/132/134/136 on the side surfaces of the lowermost memory chip 50 is thicker than a thickness of the protective film on the side surfaces of the uppermost memory chip 90; and the number of layers in the plurality of layers 130/132/134/136 on the side surfaces of the lowermost chip is equal to the number of chips in the plurality of chips stacked on the substrate (Fig. 14).
Kim et al. and Chung et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Kim et al. to have the limitations, as taught by Chung et al., in order to improve device performance and reduce device defects (Chung et al.: [0051]).
As for claim 10, Kim et al. disclose the semiconductor device according to claim 1, wherein the protective film 50a/55a is on side surfaces of the uppermost chip (Fig. 3).
As for claim 11, Kim et al. disclose the semiconductor device according to claim 10, wherein the protective film is a single layer 55a on the side surfaces of the uppermost chip (Fig. 3), and the protective film is a plurality of layers 50a/55a on the side surfaces of the lowermost chip (Fig. 3).
As for claim 13, Kim et al. disclose the semiconductor device according to claim 1, wherein the protective film 50a/55a is on an upper surface of the base substrate on which the plurality of chips are stacked (Fig. 3).
As for claim 14, Kim et al. disclose the semiconductor device according to claim 13, further comprising: a molded resin layer 55a covering the protective layer 50a, the plurality of chips, and the upper surface of the base substrate 3, wherein the protective film is exposed an outer edge (lower) surface of the molded resin layer (Fig. 3).
As for claim 15, Kim et al. disclose the semiconductor device according to claim 1, further comprising: a molded resin layer 55a covering the protective layer, the plurality of chips, and an upper surface of the base substrate (Fig. 3).
As for claim 16, Kim et al. disclose the semiconductor device according to claim 15, wherein the protective film 50a is exposed an outer edge (lower) surface of the molded resin layer (Fig. 3).
As for claim 17, Kim et al. disclose in Fig. 3 and the related text a semiconductor device, comprising:
a base substrate 3 including an interconnection layer 9/13; a plurality of memory chips CH1a/CH2a/CH3a/CH4a [0039] stacked on the base substrate (Fig. 3), each memory chip in the plurality of memory chips comprising a memory array chip and a peripheral circuit chip directly bonded to the memory array chip (Fig. 3, [0039]); and
a protective film 50a/55a between each adjacent pair of memory chips in the plurality of memory chips and on side surfaces of at least each chip in the plurality of memory chips other than an uppermost memory chip in the plurality of memory chips (Fig. 3),
wherein each memory chip in an adjacent pair of memory chips in the plurality of memory chips has a through-silicon via 42 (electrically) contacting a through-silicon via 42 of the other memory chip in the adjacent pair (Fig. 3),
the through-silicon via 42 of a lowermost memory chip CH1a in the plurality of memory chips is electrically connected to the interconnection layer 9/13,
a first memory chip in the plurality of memory chips comprises a first memory array chip and a first peripheral circuit chip directly bonded to the first memory array chip (Fig. 3, [0039]),
a second memory chip in the plurality of memory chips comprises a second memory array chip and a second peripheral circuit chip directly bonded to the second memory array chip (Fig. 3, [0039]),
the first memory chip CH1a and second memory chip CH2a are directly bonded to each other such that the first memory array chip is directly bonded to the second peripheral chip (Fig. 3 [0039]),
a first electrode PD_Db is on a first surface of the first memory chip facing toward a second surface of the second memory chip (Fig. 3),
a second electrode PD_Df on the second surface of the second memory chip (Fig. 3),
the first electrode is directly bonded to the second electrode without a solder ball connection therebetween (Fig. 3), and
there is no polymeric adhesive layer between the first memory chip and the second memory chip (Fig. 3).
Kim et al. do not disclose the protection layer is an inorganic protection layer.
Chung et al. teach in Fig. 14 and the related text a protection layer 140/130/132/134/136 is an inorganic protection layer [0048].
Kim et al. and Chung et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Kim et al. to have inorganic material as material of the protection layer, as taught by Chung et al., in order to improve device performance and reduce device defects (Chung et al.: [0051]).
As for claim 19, Kim et al. disclose the semiconductor device according to claim 17, wherein the inorganic protective film 50a/55a is on side surfaces of the uppermost memory chip CH4a ,the inorganic protective film is a single layer 55a on the side surfaces of the uppermost memory chip (fig. 3), and the inorganic protective film is a plurality of layers 50a/55a on the side surfaces of the lowermost memory chip CH1a (Fig. 3).
As for claim 22, Kim et al. disclose the semiconductor device according to claim 1, wherein the inorganic protective film 50a/55a on side surfaces of each chip in the plurality of chips is different in a direction orthogonal to the respective side surfaces of each chip in the plurality of chips (Fig. 3).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. in view of Chung et al. and further in view of Hosomi (US 2014/0246781, as disclosed in previous office action).
As for claim 5, Kim et al. in view of Chung et al. disclosed disclose the semiconductor device according to claim 1, except the base substrate includes a controller in an interior of the base substrate or the memory array chip bonded to a peripheral circuit chip.
Hosomi teaches in Fig. 1 and the related text a base substrate 1 includes a controller 2 in an interior of the base substrate or a chip 4 bonded to a peripheral circuit chip 2 (Fig. 1, [0022]).
Chung et al., Kim et al. and Hosomi are analogous art because they both are directed chip packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the combined device because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the combined device to include the limitations as taught by in order to control the operation of the chips [0022].
Response to Arguments
Applicant’s arguments with respect to claim(s) above have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TRANG Q TRAN/Primary Examiner, Art Unit 2811
Prosecution Insights