Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-19 and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 lines 5-6 and claim 17 lines 6-7 recited the limitation of “the plurality other”. There is insufficient antecedent basis for those limitations in the claim.
Claim 1 line 6-7 recited the limitation of “the stacked plurality of chips”. There is insufficient antecedent basis for those limitations in the claim.
Claim 17 line 10-13 and 15-16, recited the limitation of “the stacked plurality of memory chips”. There is insufficient antecedent basis for those limitations in the claim.
Claim 21 line 3 recited the claimed limitation of “the first memory array chip is directly bonded to the base substrate” is unclear. How can the first memory array chip directly bond to the second peripheral chip and also directly bond to the base substrate?
Claim Rejections - 35 USC § 103
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-4, 7-8, 10, 13, 15, 17 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Yoon et al. (US 2023/0072616) in view of Liu et al. (US 2020/0212004).
As for claim 1, Yoon et al. disclose in Figs. 2A-2E and the related text a semiconductor device, comprising:
a base substrate 400/500 including an interconnection layer TE/BS/BP;
a plurality of (memory) chips SC1/SC2/SC3/SC4 stacked on the base substrate (Fig. 2A-2E, [0028]); and
a protective film AD/pMD between each adjacent pair of chips in the plurality of (memory) chips stacked on the base substrate and on side surfaces of at least each chip in the plurality (of memory chips) other than an uppermost chip in the stacked plurality of chips (Fig. 2A-2E), wherein
a lowermost chip SC1 in the stacked plurality of chips has a metal pad 110 electrically connected to the interconnection layer TE/BS/BP (Fig. 2A-2E), wherein the lowermost chip SC1 is a first chip (Figs. 2A-2E),
each (memory) chip in an adjacent pair of (memory) chips in (the stack of) the plurality of chips stacked on the base substrate has an electrode 150/160 contacting an electrode of the other chip in the adjacent pair (Fig. 2A-2E),
a first chip and the second chip of the plurality of chips are memory chips [0028] and the first chip is directly bonded to the second chip (Fig. 2A-2E).
Yoon et al. do not disclose the first chip in the plurality of chips comprises a first memory array chip and a first peripheral circuit chip directly bonded to the first memory array chip, the second chip in the plurality of chips comprises a second memory array chip and a second peripheral circuit chip directly bonded to the second memory array chip, and the first chip and second chip are directly bonded to each other such that the first memory array chip is directly bonded to the second peripheral chip.
Liu et al. in Fig. 1B and the related text a memory chip comprises a first memory array chip 105 and a first peripheral circuit chip 103 directly bonded to the first memory array chip 105.
Yoon et al. and Liu et al. are analogous art because they both are directed memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yoon et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Yoon et al., to include the (first/second) memory chip comprises a first memory array chip and a first peripheral circuit chip directly bonded to the first memory array chip, as taught by Liu et al, in order to operate memory devices.
Yoon et al. in view of Liu et al. teach the first chip and second chip are directly bonded to each other such that the first memory array chip is directly bonded to the second peripheral chip or bond to the base substrate.
As for claims 3-4, Yoon et al. in view of Liu et al. disclosed the semiconductor device according to claim 1, wherein the protective film is an insulating film formed by a coating process, wherein the coating process is a spin coating process.
The recited limitation “formed by a coating process, wherein the coating process is a spin coating process” is drawn to a process by which the product is made. Even though product by process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product by process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. Because the product by process does not change the end product, Applicant’s claimed invention does not distinguish over prior art. See MPEP § 2113.
As for claims 7-8 and 17, Yoon et al. in view of Liu et al. disclosed the semiconductor device according to claim 1, Yoon et al. further disclose wherein the electrode of each of the first and second chips is a through-silicon via 150/160 (Figs. 2A-2E, [0016]), wherein each of memory chip has the through-silicon 150/160 via contacting a through-silicon via of the other memory chip in the adjacent pair (fig. 2A-2E), and the through silicon via of a lowermost memory chip in the stacked plurality of memory chips is electrically connected to the interconnection layer (Fig. 2A-2E).
As for claim 10, Yoon et al. in view of Liu et al. disclosed the semiconductor device according to claim 1, Yoon et al. further disclose the protective film AD/pMD is on side surfaces of the uppermost chip SC4 (fig. 2A-2E).
As for claim 13, Yoon et al. in view of Liu et al. disclosed the semiconductor device according to claim 1, Yoon et al. further disclose the protective film AD/pMD is on an upper surface of the base substrate on which the plurality of chips are stacked (figs. 2D-2E).
As for claim 15, Yoon et al. in view of Liu et al. disclosed the semiconductor device according to claim 1, Yoon et al. further disclose semiconductor device according to claim 1, further comprising: a molded resin layer pMD covering the protective layer AD, the plurality of chips SC1-SC4, and an upper surface of the base substrate 400/500 (fig. 2D-2E).
Claims 2, 5, 9, 11-12, 14, 16 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Yoon et al. in view of Liu et al. and further in view of Chung et al. (US 2020/0411472, as disclosed in previous office action).
As for claims 2, 5, 9, 11-12, 14, 18 and 16, Yoon et al. in view of Liu et al. disclosed the semiconductor device according to claim 1, except the protective film comprises at least one of SiO2, SiOC, SiN, and SiCN; wherein the base substrate includes a controller in an interior of the base substrate; wherein a thickness of the protective film on the side surfaces of the lowermost chip is thicker than a thickness of the protective film on the side surfaces of the uppermost chip; wherein the protective film is a single layer on the side surfaces of the uppermost chip, and the protective film is a plurality of layers on the side surfaces of the lowermost chip; wherein the number of layers in the plurality of layers on the side surfaces of the lowermost chip is equal to the number of chips in the plurality of chips stacked on the substrate; wherein the protective film is exposed an outer edge surface of the molded resin layer.
Chung et al. disclose in Fig. 1/14 and the related text a protective film comprises at least one of SiO2, SiOC, SiN, and SiCN [0044], wherein a (horizontal) thickness of the protective film on the side surfaces of the lowermost chip 50 is thicker than a thickness of the protective film on the side surfaces of the uppermost chip 90 (fig. 14), wherein the protective film 130/132/134/136 is a single layer on the side surfaces of the uppermost chip 90, and the protective film 130/132/134/136 is a plurality of layers on the side surfaces of the lowermost chip 50 (fig. 14), wherein the number of layers in the plurality of layers on the side surfaces of the lowermost chip 50 is equal to the number of chips in the plurality of chips 50/70/80/90 stacked on the substrate 100 (fig. 14), wherein the protective film 130/132/134/136 is exposed an outer edge surface of the molded resin layer (fig. 14).
Yoon et al., Liu et al. and Chung et al. are analogous art because they both are directed memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the combined device because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the combined device to include the limitations as taught by Chung et al, in order to provide better protection for the devices.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Yoon et al. in view Liu et al. and further in view of Hosomi (US 2014/0246781).
As for claim 5, Yoon et al. in view of Liu et al. disclosed disclose the semiconductor device according to claim 1, except the base substrate includes a controller in an interior of the base substrate or the memory array chip bonded to a peripheral circuit chip.
Hosomi teaches in Fig. 1 and the related text a base substrate 1 includes a controller 2 in an interior of the base substrate or a chip 4 bonded to a peripheral circuit chip 2 (Fig. 1, [0022]).
Chung et al., Liu et al. and Hosomi are analogous art because they both are directed chip packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the combined device because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the combined device to include the limitations as taught by in order to control the operation of the chips [0022].
Response to Arguments
Applicant’s arguments with respect to claim(s) above have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TRANG Q TRAN/Primary Examiner, Art Unit 2811
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