Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are now pending in the application under prosecution and have been examined.
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors.
The specification should be amended to reflect the status of all related application, whether patented or abandoned. Therefore, applications noted by their serial number and/or attorney docket number should be updated with correct serial number and patent number if patented.
The first instance of all acronyms or abbreviation should be spelled out for clarity, whether or not considered well known in the art.
In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
37 C.F.R. § 1.83(a) requires the Drawings to illustrate or show all claimed features.
Applicant must clearly point out the patentable novelty that they think the claims present, in view of the state of the art disclosed by the references cited or the objections made, and must also explain how the amendments avoid the references or objections. See 37 C.F.R. § 1.111(c).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/07/2022 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Claim Rejections - 35 USC§ 101
35 U.S.C.101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C.101 because the claimed invention is directed to an abstract idea without significantly more.
Claim 1 recites: A processor comprising: one or more circuits to cause information to be stored from one of two or more different tensors having one or more variable dimensions, wherein the one of the two or more different tensors is to represent the two or more different tensors.
ANALYSIS
Step 1: This part of the eligibility analysis evaluates whether the claim falls within any
statutory category. MPEP 2106.03. The claim recites a processor and, therefore, being a machine, which a statutory category of invention.
Step 2A Prong One: This part of the eligibility analysis evaluates whether the claim recites a
judicial exception. The limitation: cause information to be stored from one of two or more different tensors having one or more variable dimensions, wherein the one of the two or more different tensors is to represent the two or more different tensors.
This feature, under its broadest reasonable interpretation, encompasses a mental process. The specification describes a tensor being a representation of numbers, wherein a second tensor is to be generated by at least performing a reshape operation on a first tensor. This encompasses a user manually or with the aid of pen and paper converting a tensor to have a different dimension in order to be compatible with a processing requirement.
Step 2A Prong Two: The claim recites the additional elements of a processor and one or more circuits recited at a high level of generality and, therefore, comprise mere instructions to apply the exception.
Step 28: This part of the eligibility analysis evaluates whether the claim as a whole amounts to significantly more than the recited exception, i.e., whether any additional element, or combination of additional elements, adds an inventive concept to the claim. MPEP 2106.05. As explained with respect to Step 2A, Prong Two, the processor and circuits are at best mental processing information from one of two or more different tensors having one or more variable dimensions, which do not provide an inventive concept.
Claim 1 is ineligible; and Independent claims 8, 15, are similarly ineligible.
Dependent claims 2-7, 9-14, and 16-20 similarly recite limitations involving various modifications to tensors that, a user can used as information processed from the one of two or more different tensors having one or more variable dimensions which are generis representations of the tensors, and, are, therefore also ineligible.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1-20 are rejected under 35 U.S.C. 102(a2) as being anticipated by US 20230252273 (RACAPE).
With respect to claim 1, RACAPE teaches processor comprising: one or more circuits to cause information to be stored from one of two or more different tensors having one or more variable dimensions, wherein the one of the two or more different tensors is to represent the two or more different tensors (apparatus comprising one or more processors, the one or more processors to used parameter bitstreams (decoded bitstreams) to decompose a first tensor based on the decoded bitstreams stored in memory or buffer into a second tensor and a third tensor, the decoded one or more of the second tensor and the third tensor based on one or more derived sizes) [Par. 0009-0010; Par. 0071-0082; Par. 0117-0118].
With respect to claim 8, RECAPE teaches method, comprising: causing information to be stored from one of two or more different tensors having one or more variable dimensions (parameters (like Weights and/or Biases) stored as multi-dimensional arrays (also referred to herein as “tensors”) being integer weight tensor can then be invoked with input variable (decoded bitstreams) used to decompose a tensor into a second tensor and a third tensor) The tensors having variable number of rows and columns [Par. 0007-0008; Par. 0040-0042], wherein the one of the two or more different tensors is to represent the two or more different tensors (the decoding from the bitstream one or more sizes corresponding to at least one or more of the second tensor and the third tensor) [Par.0117-0118; Par. 0071-0082].
FIG. 6 illustrates an example of a method 600 for decoding tensors resulting for a tensor decomposition, according to an embodiment as described above. A bitstream comprising coded data representative of a neural network is input to the decoder. At 601, it is determined whether an original tensor has been decomposed into a first tensor and a second tensor, e.g the first and second tensors are respectively a G and H tensors resulting from a low rank decomposition. At 602, if the current unit to decode comprises weights a tensor resulting from a tensor decomposition, a size of the first tensor is decoded from the bitstream. For instance, in the case of a G tensor, the size of the first tensor is a number of rows of the G tensor.
At 603, the first tensor is decoded based on the decoded size. At 604, a size of the second tensor is derived from the decoded size. For instance, when the second tensor is an H tensor, the size of the second tensor is a number of columns of the H tensor. At 605, the second tensor is decoded based on the derived size. At 606, the decoder can reconstruct the decomposed tensor from the decoded first and second tensors.
With respect to claim 15, RECAPE teaches system comprising: one or more processors to cause information to be stored from one of two or more different tensors having one or more variable dimensions, wherein the one of the two or more different tensors is to represent the two or more different tensors (computer program comprising instructions which when executed by one or more processors cause the one or more processors to perform the encoding method or decoding method: storing parameters as multi-dimensional tensors wherein at least one first tensor of at least one layer of at least one Deep Neural Network is decomposed into a second tensor and a third tensor whose parameters are encoded in bitstreams featured in one or more sizes corresponding to at least one or more of second tensor and third tensor) [Par. 0009-0010; Par.0117-0118; Par. 0071-0082].
With respect to claim 2, and corresponding method of claim 9 and system of claim 16, RECAPE teaches the processor, wherein the one of the two or more different tensors is to represent the two or more different tensors by causing the information from the one of the two or more different tensors to be used as data of another of the two or more different tensors (tensor decomposition to compress large tensors of weights with at least two smaller tensors produced and further compressed, quantized and entropy coded to be stored or transmitted within a bitstream) [Par. 0031-0034]..
With respect to claim 3, and corresponding method of claim 11 and system of claim 17, RECAPE teaches the processor, wherein the information comprises elements of the one of the two or more different tensors (tensors of one or more DNN, different decompositions performed with decomposition tensor type identification parameter identifier describing link between tensors) [Tables 1-2; Par. 0065-0069].
With respect to claim 4, and corresponding method of claim 11 and system of claim 18, RECAPE teaches the processor, wherein the one or more circuits are to generate a correspondence between dimensions of pairs of the two or more different tensors (different decompositions performed with decomposition tensor type identification parameter identifier describing syntax element from tensor unit header that maps tensor units to uniquely identifiable data structures that depend on the topology storage format) [Gig. 5; Par. 0059; Tables 1-2; Par. 0065-0069].
With respect to claim 5, and corresponding method of claim 12 and system of claim 19, RECAPE teaches the processor, wherein the two or more different tensors are to comprise a first tensor and a second tensor, wherein the second tensor is to be generated by at least performing a reshape operation on the first tensor (different decompositions to be performed where a tensor of a convolution or depth-wise convolution layers can be reshaped into a 2-dimension matrix without changing its data) [Par. 0040-0044; Par. 00117].
With respect to claim 6, and corresponding method of claim 13, RECAPE teaches the processor, wherein the one or more circuits are to cause the information to be stored by at least performing a compiler (using layer and parameter set performing encoding/decoding operations corresponding to tensors) [Par. 0059-0062].
With respect to claim 7 and corresponding method of claim 14 and system of claim 20, RECAPE teaches the processor, wherein the one or more circuits are to generate a correspondence between dimensions of pairs of the two or more different tensors based, at least in part, on a leading item in a list of tensor dimensions and an ultimate item in a list of dimensions (tensor dimensions defined by its decoded syntax tensor used for specifying the reconstruction dimension with depth-wise reconstruction parameters used to decompose into variable dimension) [Par. 0026-0029; Par. 0110-0117].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
LIN ZOU CHEN et al (CN 107516129 A) “Tucker Decomposition Of Depth Of Dimension-based Adaptive Network Compression Method “Tucker decomposition depth network compression method based on dimension-adjustment, comprising a dimension adaptive regulation process and dimension suitable for the weight tensor decomposition process, by suitable adjusting the size of each dimension of the tensor to generate a new any-order tensor, and the tensor decomposition through learning of the core tensor and the transfer matrix, so as to achieve the purpose of network optimizing compression. Compared with current low-rank compression method, the invention under the condition of maintaining network performance, network parameter with a larger compression ratio, can obtain higher compression ratio, at the same time, does not need to store guiding position of the non-zero element, there is no need to record index which can more effectively use storage space.”
R. Nagai and T. Tomono, "Tensor Network-Based Continuous Variable Quantum Circuit Optimization for Preparation of GKP State," 2023 IEEE International Conference on Quantum Computing and Engineering (QCE), Bellevue, WA, USA, 2023, pp. 385-386.
Peng, Ruojing • Gray, Johnnie • Chan, Garnet Kin-Lic, “Arithmetic Circuit Tensor Networks, Multivariable Function Representation, and High-dimensional Integration”, arXiv Article arXiv.org, 2022-08-16.
WO 2022251317 A1 (YUAN et al) teaching systems and methods provide improved neural network compression by training, based on training data and an optimization problem, a deep neural network to produce a trained deep neural network by iteratively updating a weight matrix of the deep neural network according to, at each iteration, minimizing a rank value of the weight matrix until a memory capacity metric is satisfied.
YOON (US 20200117999) teaching Data Processing Method For Modifying Machine Learning Models Based On Characteristics Of Memory To Improve Locality, By Performing Machine Learning Computations Using Updated Machine Learning Model Which Is Generated Based On Received Data.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PIERRE MICHEL BATAILLE whose telephone number is (571)272-4178. The examiner can normally be reached Monday - Thursday 7-6 ET.
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/PIERRE MICHEL BATAILLE/Primary Examiner, Art Unit 2138
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