DETAILED ACTION
This Notice is responsive to communication filed on 04/13/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/13/2026 has been entered.
Response to Amendment
The amendment filed on 04/13/2026 under 37 C.F.R. 1.111 has been entered. Claims 1, 2, 4, 5, 7, 8, 10-12, 14-16, and 20-21 remain pending in the application. Claims 3 and 6 have been cancelled. Claims 9, 13, and 17-20 are currently withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 5, 10, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 20210098381) and further in view of Bharath et al. (US 20200098621).
Regarding claim 1, Yu discloses:
A semiconductor device assembly, comprising:
a first semiconductor device subassembly (annotated below), including:
a first substrate Fig. 14: 170+180+190 forming a first outermost side of the assembly,
the first substrate Fig. 14: 170+180+190 having a first inner surface (annotated below) and a first outer surface (annotated below),
a first stack of semiconductor dies Fig. 14: 130B (para. 0059) disposed on the first inner surface, and
a first interconnect structure (annotated below) disposed on the first inner surface,
the interconnect structure having a first conductive pillar Fig. 14: 120B and
a first dielectric material Fig. 14: 140B surrounding the first conductive pillar Fig. 14: 120B,
wherein a height of the first stack Fig. 14: 130B is less than or equal to a height of the first interconnect structure (shown in Fig. 14);
a second semiconductor device subassembly (annotated below), including:
a second substrate Fig. 14: 200 forming a second outermost side Fig. 14: 210b of the assembly opposite to the first outermost side,
the second substrate Fig. 14: 200 having a second inner surface Fig. 14: IF1 and a second outer surface Fig. 14: 210b,
a second stack of semiconductor dies Fig. 14: 130A (para. 0059) disposed on the second inner surface Fig. 14: IF1, and
a second interconnect structure (annotated below) disposed on the second inner surface Fig. 14: IF1,
the second interconnect structure having a second conductive pillar Fig. 14: 120A and
a second dielectric material Fig. 14: 140A surrounding the second conductive pillar Fig. 14: 120A, and
wherein a height of the second stack Fig. 14: 130A is less than or equal to a height of the second interconnect structure (shown in Fig. 14); and
an encapsulant material Fig. 14: 140A+140B at least partially encapsulating the first and second stacks Fig. 14: 130A+130B and the first and second interconnect structures (annotated below),
wherein the encapsulant comprises a different material than the first dielectric material and the second dielectric material, and
wherein the first conductive pillar Fig. 14: 120B is directly coupled to the second conductive pillar Fig. 14: 120A (via 154A).
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Bharath discloses the following claim limitations not disclosed by Yu:
wherein the encapsulant Fig. 1A: 127 comprises a different material (para. 0039, i.e. nonconductive film NCF) than the first dielectric material and the second dielectric material (para. 0043, “dielectric material” such as bismaleimide triazine BT resin).
It would have been obvious to one of ordinary skill in the art before the effective filing
date of the invention to modify Yu with Bharath in order to embed one or more dies in a layer, while also having a material with a coefficient of thermal expansion that may mitigate of minimize the stress between the dies and package substrate arising from uneven thermal expansion (para. 0039).
Regarding claim 2, Yu discloses:
The semiconductor device assembly of claim 1:
wherein the first die stack Fig. 14: 130B is spaced apart from the second die stack Fig. 14: 130A by a gap, and
wherein the gap is at least partially filled with an adhesive Fig. 14: 152A (para. 0075) or underfill material.
Regarding claim 4, Yu discloses:
The semiconductor device assembly of claim 1:
wherein the first substrate Fig. 14: 170+180+190 has external connections Fig. 14: 190 at the first outermost side of the assembly, and
wherein a portion of the external connections Fig. 14: 190 are connected to the second die stack Fig. 14: 130A through the coupled first and second conductive pillars Fig. 14: 120A+120B (para. 0094; Fig. 14 shows the connectivity).
Regarding claim 5, Yu discloses:
The semiconductor device assembly of claim 1:
wherein at least one of the first and second die stacks Fig. 14: 130A is directly bonded to the corresponding first or second substrate Fig. 14: 200 by solder balls or by wire bonds (Fig. 1: 132, 134, 133; para. 0060 teaches metallization layers).
Regarding claim 10, Yu discloses:
The semiconductor device assembly of claim 1, wherein:
the first semiconductor subassembly further comprises a first group (annotated below) of interconnect structures including the first interconnect structure (annotated below);
the second semiconductor subassembly further comprises a second group (annotated below) of interconnect structures including the second interconnect structure (annotated below); and
each interconnect structure of the first and second groups includes a single conductive pillar Fig. 14: 120A/120B surrounded by a discrete region of dielectric material Fig. 14: 140A/140B.
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Regarding claim 21, Yu discloses:
The semiconductor device assembly of claim 1:
wherein the second dielectric material Fig. 14: 140A is directly coupled to the first dielectric material Fig. 14: 140B by an adhesive material Fig. 14: 152A (para. 0075, 0053).
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 20210098381) as applied to claim 1 above, and further in view of Gandhi (US 20170148769).
Regarding claim 7, Yu discloses:
The semiconductor device assembly of claim 1, wherein the first and second conductive pillars Fig. 14: 120A/120B are directly coupled (see Fig. 14: 154A) via a solder joint.
Gandhi discloses the following claim limitation not disclosed by Yu.
Via a solder joint Fig. 3A: 340 (para. 0016).
It would have been obvious to one of ordinary skill in the art before the effective filing
date of the invention to modify Yu’s invention with Gandhi’s in order to form a joint with a solder having a suitable bond material thickness increasing the bond strength of the conductive joint (para. 0015).
Regarding claim 8, Yu discloses:
The semiconductor device assembly of claim 7, wherein the solder joint Fig. 154A is surrounded by an encapsulant material or adhesive Fig. 14: 152A directly coupling the first dielectric Fig. 14: 140B to the second dielectric Fig. 14: 140A.
Claims 11 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 20210098381) as applied to claim 1 above, and further in view of Kim (US 20200227386).
Regarding claim 11, Kim discloses the following claim limitations not disclosed by Yu:
The semiconductor device assembly of claim 1, wherein the first conductive pillar Fig. 2C 217 is soldered to the first substrate Fig. 2C 260+262, and the second conductive pillar Fig. 2C: 217 is soldered to the second substrate Fig. 2C: 260+262 (para. 0035). Kim teaches another package substrate may be coupled to the present package substrate 200 in para. 0043).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Yu’s invention with Kim’s invention in order to enable an improved signal integrity margin and enhancing electrical performance while decreasing signal loss of the semiconductor package (para. 0013).
Regarding claim 22, Yu discloses:
The semiconductor device assembly of claim 1, wherein the first interconnect structure is coupled to the first inner surface (via. Fig. 14: 154B/152B) by a solder structure, and
wherein the first dielectric material Fig. 14: 140B is coupled to the first inner surface by an adhesive material Fig. 14: 152B.
Kim discloses the following claim limitation not disclosed by Yu.
By a solder structure. Para. 0035 teaches solder bumps connecting the bottom ends of the interconnects to the substrate 260.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Yu’s invention with Kim’s invention in order to enable an improved signal integrity margin and enhancing electrical performance while decreasing signal loss of the semiconductor package (para. 0013).
Claims 12, 14, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 20210098381), and further in view of Albini (US 20210305506).
Regarding claim 12, Yu discloses:
A semiconductor device subassembly, comprising:
a substrate Fig. 5: 200 (annotated below) including:
an inner surface (annotated), and an outer surface Fig. 5: 210b exclusive of any conductive structures (none shown in Fig. 5);
a stack of semiconductor dies Fig. 5: 130A (para. 0059) disposed on the inner surface; and
an interconnect structure (annotated), including:
a lower surface (annotated) disposed on the inner surface (annotated) of the substrate Fig. 5: 200,
an upper surface Fig. 5: 120t opposite the lower surface, and
at least one conductive pillar Fig. 5: 120A extending from the lower surface to the upper surface Fig. 5: 120t, and
a dielectric material Fig. 5: 140A surrounding the at least one conductive pillar Fig. 5: 120A and extending from the lower surface to the upper surface Fig. 5: 120t such that an uppermost surface of the dielectric material Fig. 5: 140t is coplanar with a top surface of the conductive pillar Fig. 5: 120t,
wherein a height of the die stack is less than a height of the interconnect structure.
Albini discloses the following claim limitation not disclosed by Yu.
wherein a height of the die stack Fig. 6: 105a/b/c is less than a height of the interconnect structure Fig. 6: 205 (shown in Fig. 6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Yu’s invention with Albini’s in order to have an interconnection structure with a height greater than the height of the die stack and in contact with a metal layer that serves as an access line which helps support a reduced contact resistance, improving the overall memory device performance (para. 0065).
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Regarding claim 14, Yu discloses:
The semiconductor device subassembly of claim 12:
wherein the interconnect structure is a first interconnect structure (annotated above), and
wherein the subassembly further comprises a second interconnect structure (annotated above) having a second conductive pillar Fig. 5: 120A and a second dielectric material Fig. 1: 140A surrounding the second conductive pillar Fig. 5: 120A,
wherein the second dielectric material Fig. 1: 140A is separated from the first dielectric material Fig. 1: 140A (Fig. 5 shows these are separated by the circuit components 130B).
Regarding claim 15, Yu discloses:
The semiconductor device subassembly of claim 12:
wherein the interconnect structure further includes a contact pad Fig. 5: 240 (connecting via) which is in direct contact with the inner surface of the substrate (annotated above) and with the conductive pillar Fig. 5: 120A.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 20210098381) and Albini (US 20210305506) as applied to claim 12 above, and further in view of Kim (US 20200227386).
Regarding claim 16, Yu discloses:
The semiconductor device subassembly of claim 15, wherein the interconnect structure is coupled to the substrate by a solder joint.
Kim discloses the following claim limitation not disclosed by Yu:
By a solder joint. Para. 0035 teaches solder bumps connecting the bottom ends of the interconnects to the substrate 260.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Yu’s invention with Kim’s invention in order to enable an improved signal integrity margin and enhancing electrical performance while decreasing signal loss of the semiconductor package (para. 0013).
Conclusion
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/Nkechinyere Esiaba/Examiner, Art Unit 2817 /NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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