DETAILED ACTION
This Notice is responsive to communication filed on 10/20/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
An amendment filed on 10/20/2025 has been acknowledged and entered into the record.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 12, and 14-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu (US 20200381397).
Regarding claim 12, Yu teaches a semiconductor device subassembly Fig. 26: 562, comprising:
a substrate Fig. 26: 520 including:
an inner surface (annotated below), and an outer surface (annotated below) exclusive of any conductive structures;
a stack of semiconductor dies Fig. 26: 320, 120, 220, 420 disposed on the inner surface (annotated below); and
an interconnect structure (annotated below), including:
a lower surface (annotated below) disposed on the inner surface (annotated below) of the substrate Fig. 26: 520, an upper surface (annotated below) opposite the lower surface (annotated below), and at least one conductive pillar Fig. 26: 552 (left) extending from the lower surface to the upper surface surrounded by a region of dielectric material Fig. 26: 450 (see also Fig. 26: 454, 456, 534) extending from the lower surface to the upper surface (Pg. 8, para. 0064 “forming a dielectric layer to encapsulating the portions of the TSVs…”),
wherein a height of the die stack is less than a height of the interconnect structure (Fig. 26 shows this size orientation where height of the die stack, not including dielectric layers 356, 454, is less than the height of the interconnect structure annotated).
Regarding claim 14, Yu teaches the subassembly Fig. 26: 562 wherein the interconnect structure is a first interconnect structure (annotated below), and wherein the subassembly further comprises a second interconnect structure (annotated below) having a second conductive pillar Fig. 26: 552 (right) and a second discrete region of dielectric material Fig. 26: 450 surrounding the second conductive pillar Fig. 26: 552 (right).
Regarding claim 15, Yu teaches the subassembly Fig. 26: 562 wherein the interconnect structure further includes a contact pad Fig. 26: 542 which is in direct contact with the inner surface of the substrate Fig. 26: 520 and with the conductive pillar Fig. 26: 552.
Regarding claim 16, Yu teaches the semiconductor device subassembly of claim 15, wherein the interconnect structure is coupled to the substrate by a solder joint Fig. 26: 542 (para. 0060, bonding pad used to bond structure to substrate).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8, 10, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 1,190,449), and further in view of Yu (US 20200381397) and Nakano (US 11069612).
Regarding claim 1, Kim teaches a semiconductor device assembly Fig. 1C: 140, comprising:
a first semiconductor device subassembly (annotated below), including:
a first substrate Fig. 1B: 102 having a first inner surface (annotated below) forming a first outermost side (annotated below) of the assembly Fig. 1B: 150 and a first outer surface (annotated below),
a first stack of semiconductor dies (annotated below) disposed on the first inner surface, and
a first interconnect structure (annotated below) disposed on the first inner surface, having a first conductive pillar (annotated below), and a first region of dielectric material (annotated below) surrounding the first conductive pillar,
wherein a height of the first stack is less than or equal to a height of the first interconnect structure (shown in Fig. 1C);
a second semiconductor device subassembly (annotated below), including:
a second substrate (annotated below) having a second inner surface (annotated below) forming a second outermost side of the assembly and a second outer surface (annotated below),
a second stack of semiconductor dies (annotated below) disposed on the second inner surface, and
a second interconnect structure (annotated below) disposed on the second inner surface, having a second conductive pillar (annotated below), and a second region of dielectric material (annotated below) surrounding the second conductive pillar,
wherein the second outermost side is opposite to the first outermost side (shown in Fig. 1C), and
wherein a height of the second stack is less than or equal to a height of the second interconnect structure (shown in Fig. 1C); and
an encapsulant material (annotated below) at least partially encapsulating the first and second stacks and the first and second interconnect structures.
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But Kim fails to teach wherein the encapsulant comprises a different material than the dielectric material. However, Yu teaches wherein the encapsulant comprises a different material than the dielectric material ([para 0026], “encapsulant…formed of molding compound, molding underfill, a resin, an epoxy…”; [para 0013], “dielectric material such as silicon oxide, silicon nitride…”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Kim’s and Yu’s teachings and use an encapsulant different from the dielectric material for the purpose of electrically connecting bond pads to the conductive pillars/TSVs (para 0064) and isolating the TSVs from a semiconductor substrate (para 0013).
Kim also fails to explicitly teach wherein the first conductive pillar is directly coupled to the second conductive pillar. However, Nakano teaches wherein the first conductive pillar Fig. 3: 320a (coupled to 302a) is directly coupled to the second conductive pillar Fig. 3: 320a (coupled to 302b). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Kim and Nakano for the purpose of providing a continuous optical and electrical path between the semiconductor dies (col. 4, lines 15-17).
Regarding claim 3, Kim teaches the semiconductor device assembly of claim 1, wherein the first substrate Fig. 1C: 102 has external connections Fig. 1C: 113 at the first outermost side of the assembly.
Regarding claim 4, Kim teaches wherein the semiconductor device assembly of claim 3, wherein a portion of the external connections Fig. 1C: 113 are connected to the second die stack through the coupled first and second conductive pillars (the annotated second stack is connected to the annotated second conductive pillars, which is soldered to the annotated first interconnect structure, which is soldered to the first substrate, and connected to the external connections).
Regarding claim 5, Kim teaches the semiconductor assembly of claim 1, wherein at least one of the first and second die stacks is directly bonded to the corresponding first or second substrate by solder balls or by wire bonds (Fig. 1C shows the first stack is bonded to the first substrate via solder balls).
Regarding claim 6, Kim teaches the semiconductor assembly of claim 1, wherein at least one of the first and second substrates comprises a printed circuit board or an interface die (col. 5, lines 54-55, first substrate 102 is a PCB).
Regarding claim 7, Nakano teaches the semiconductor assembly of claim 1, wherein the first and second conductive pillars Fig. 3: 320a are directly coupled via a solder joint Fig. 1: 132, 134 (i.e. col. 6, lines 16-24 teaches solder material as part of the connection layer joining the first and second pillars).
Regarding claim 8, Nakano teaches the semiconductor device of claim 7, wherein the solder joint Fig. 1: 132, 134 is surrounded by an encapsulant material or adhesive Fig. 1: 106 (i.e. connection layer) directly coupling the first dielectric Fig 1: 122 (of 102b) to the second dielectric Fig. 1: 122 (of 102a).
Regarding claim 10, Kim teaches the semiconductor device assembly of claim 1, wherein: the first semiconductor subassembly further comprises a first group of interconnect structures including the first interconnect structure; the second semiconductor subassembly further comprises a second group of interconnect structures including the second interconnect structure; wherein each interconnect structure of the first and second groups includes a single conductive pillar surrounded by a discrete region of dielectric material (annotated below).
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Regarding claim 11, Kim teaches the semiconductor device assembly of claim 1, wherein the first conductive pillar is soldered to the first substrate, and the second conductive pillar is soldered to the second substrate (col. 6, lines 62-66).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 11990449 B2), Yu et al. (US 20200381397 A1), and Nakano (US 11069612 B2) as applied to claim 1 above, and further in view of Bharath et al. (US 20200098621 A1).
Regarding claim 2, Kim, Yu and Nakano fail to teach the substantial features of the semiconductor device assembly of claim 1, wherein the first die stack is spaced from the second die stack by a gap, and wherein the gap is at least partially filled with an adhesive or underfill material. However, Bharath teaches the gap is at least partially filled with an adhesive or underfill material Fig. 1A: 127 (para 0039). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Kim’s, Yu’s, and Bharath’s teachings to fill the gap with an underfill for the purpose of assisting with soldering the die to the package substrate and to mitigate stress between the dies and the substrate (para 0039).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-8, 10-12, and 14-16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NKECHINYERE ESIABA whose telephone number is (571)272-0720. The examiner can normally be reached Monday - Friday 10am-5pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nkechinyere Esiaba/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 January 9, 2026