DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 – 6, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEE et al. (2016/0300950) in view of Noh et al. (8674359).
With regard to claim 1, LEE et al. disclose a thin film transistor (for example, see fig. 3) comprising:
an active layer (portions 133, 134, 135 functioning as an active layer) including an oxide semiconductor layer (134);
a metal layer (metal layers 173, 175 functioning as a metal layer) disposed on the active layer (133, 134, 135) and overlapping with at least a portion of the active layer (133, 134, 135);
a gate electrode (155) provided on the active layer (133, 134, 135) and spaced apart from the active layer (133, 134, 135), and overlapping with at least a portion of the active layer (133, 134, 135); and
a gate insulating film (142) disposed between the active layer (133, 134, 135) and the gate electrode (155),
wherein the active layer (133, 134, 135) further includes: a channel portion (134); a first connection portion (133) contacting one side of the channel portion (134); and a second connection portion (135) contacting another side of the channel portion (134), and wherein the metal layer (173, 175) includes a first metal layer (173) contacting an upper surface of the first connection portion (133), and a second metal layer (175) contacting an upper surface of the second connection portion (135);
wherein a lower surface of the first metal layer (173) and a lower surface of the second metal layer (175) directly contact an upper surface of the active layer (133, 134, 135).
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LEE et al. (2016/0300950) does not clearly disclose an entire lower surface of the first metal layer and an entire lower surface of the second metal layer directly contact an upper surface of the active layer wherein an end of the first metal layer aligns with an end of the first connection portion.
However, Noh et al. disclose an entire lower surface of the first metal layer (referred to as “143a1” by examiner’s annotation shown in fig. 4 below; wherein the first metal layer 143a1 is a portion of the metal layer 143a) and an entire lower surface of the second metal layer (referred to as “143a2” by examiner’s annotation shown in fig. 4 below; wherein the first metal layer 143a2 is a portion of the metal layer 143a) directly contact upper surface of the active layer (the active layer including connection portions 142a); wherein an end (referred to as “E1” by examiner’s annotation shown in fig. 4 below) of the first metal layer (143a1) aligns with an end (referred to as “E2” by examiner’s annotation shown in fig. 4 below) of the first connection portion (referred to as “142a1” by examiner’s annotation shown in fig. 4 below).
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Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the LEE et al. (2016/0300950)’s device to have an entire lower surface of the first metal layer and an entire lower surface of the second metal layer directly contact an upper surface of the active layer wherein an end of the first metal layer aligns with an end of the first connection portion as taught by Noh et al. in order to prevent the active layer from being damaged due to over-etching for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 2, LEE et al. disclose the channel portion (134) is doped with copper (for example, paragraph [0066]).
With regard to claim 3, LEE et al. disclose the gate electrode (155) includes: a first gate electrode; and a second gate electrode disposed on the first gate electrode and including titanium (the gate electrode 155 may have a multilayer structure. Therefore, the gate electrode 155 includes: a first gate electrode; and a second gate electrode disposed on the first gate electrode; for example, paragraph [0074]).
With regard to claim 4, LEE et al. disclose each of the first metal layer (173) and the second metal layer (173) includes titanium (for example, see paragraph [0093]).
With regard to claim 5, LEE et al. disclose a light shielding layer (70) disposed under the active layer (133, 134, 135).
With regard to claim 6, LEE et al. disclose the light shielding layer (70) includes: a first light shielding layer; and a second light shielding layer on the first light shielding layer, wherein each of the first light shielding layer and the second light shielding layer includes at least one of molybdenum (Mo) and titanium (Ti). (the light shielding layer 70 may have a multilayer film structure. Therefore, the light shielding layer 70 includes: a first light shielding layer; and a second light shielding layer on the first light shielding layer wherein each of the first light shielding layer and the second light shielding layer made of a metal material and the metal material inherently includes at least one of molybdenum (Mo) and titanium (Ti); for example, paragraph [0060]).
With regard to claim 14, LEE et al. disclose a display apparatus (for example, see fig. 3) comprising:
a thin film transistor including an oxide semiconductor active layer (134; or portions 133, 134, 135, having oxide semiconductor 134, functioning as an oxide semiconductor active layer), a metal layer (173, 175) disposed on the oxide semiconductor active layer (134; or portions 133, 134, 135), a gate electrode (155) provided on the oxide semiconductor active layer (134; or portions 133, 134, 135), and a gate insulating film (142) disposed between the oxide semiconductor active layer (134; or portions 133, 134, 135) and the gate electrode (155), wherein the oxide semiconductor active layer (133, 134, 135) includes a channel portion (134), a first connection portion (133) contacting one side of the channel portion (134) and a second connection portion (135) contacting the other side of the channel portion (134); wherein the metal layer (173, 175) overlaps with at least a portion of the oxide semiconductor active layer (133, 134, 135) and includes a first metal layer (173) contacting an upper surface of the first connection portion (133), and a second metal layer (175) contacting an upper surface of the second connection portion (135), and wherein the gate electrode (155) is spaced apart from the active layer (133, 134, 135) and overlaps with at least a portion of the oxide semiconductor active layer (133, 134, 135);
wherein a lower surface of the first metal layer (173) and a lower surface of the second metal layer (175) directly contact an upper surface of the oxide semiconductor active layer (133, 134, 135).
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LEE et al. (2016/0300950) does not clearly disclose an entire lower surface of the first metal layer and an entire lower surface of the second metal layer directly contact an upper surface of the active layer wherein an end of the first metal layer aligns with an end of the first connection portion.
However, Noh et al. disclose an entire lower surface of the first metal layer (referred to as “143a1” by examiner’s annotation shown in fig. 4 below; wherein the first metal layer 143a1 is a portion of the metal layer 143a) and an entire lower surface of the second metal layer (referred to as “143a2” by examiner’s annotation shown in fig. 4 below; wherein the first metal layer 143a2 is a portion of the metal layer 143a) directly contact upper surface of the active layer (the active layer including connection portions 142a); wherein an end (referred to as “E1” by examiner’s annotation shown in fig. 4 below) of the first metal layer (143a1) aligns with an end (referred to as “E2” by examiner’s annotation shown in fig. 4 below) of the first connection portion (referred to as “142a1” by examiner’s annotation shown in fig. 4 below).
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Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the LEE et al. (2016/0300950)’s device to have an entire lower surface of the first metal layer and an entire lower surface of the second metal layer directly contact an upper surface of the active layer wherein an end of the first metal layer aligns with an end of the first connection portion as taught by Noh et al. in order to prevent the active layer from being damaged due to over-etching for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEE et al. (2016/0300950) in view of Noh et al. (8674359) and further in view of ZHANG et al. (2024/0013727).
With regard to claim 7, LEE et al. (2016/0300950) does not clearly disclose the light shielding layer and the gate electrode are electrically connected to each other.
However, ZHANG et al. discloses the light shielding layer (22) and the gate electrode (6) are electrically connected to each other. (for example, see paragraph [0057], fig. 5).
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Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the LEE et al. (2016/0300950)’s device to have the light shielding layer and the gate electrode are electrically connected to each other as taught by ZHANG et al. in order to secure currents flow through the gate layer for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Claim(s) 8 - 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEE et al. (2016/0300950) in view of Noh et al. (8674359) and further in view of LEE et al. (2021/0202910).
With regard to claims 8 and 9, LEE et al. (2016/0300950) does not clearly disclose a hydrogen blocking layer disposed on the gate insulating film; wherein the hydrogen blocking layer includes: a first hydrogen blocking layer; and a second hydrogen blocking layer disposed on the first hydrogen blocking layer.
However, LEE et al. (2021/0202910) discloses a hydrogen blocking layer (134, 142) disposed on the gate insulating film (132); wherein the hydrogen blocking layer (134, 142) includes: a first hydrogen blocking layer (134); and a second hydrogen blocking layer (142) disposed on the first hydrogen blocking layer (134). (for example, see fig. 1).
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Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the LEE et al. (2016/0300950)’s device to have a hydrogen blocking layer disposed on the gate insulating film; wherein the hydrogen blocking layer includes: a first hydrogen blocking layer; and a second hydrogen blocking layer disposed on the first hydrogen blocking layer as taught by LEE et al. (2021/0202910) in order to prevent diffusion of a hydrogen into the semiconductor layer for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 10, LEE et al. (2021/0202910) disclose the hydrogen blocking layer (134, 142) made of copper oxide (for example, see paragraphs [0054]; [0066]) and the gate electrode (138) made of copper (for example, see paragraph [0059]) has a same composition (eg. copper) as the gate electrode (138).
Response to Amendment
5. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812