DETAILED ACTION
This Office action responds to Applicant’s amendments and arguments filed on 05/05/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The present Office action is made with all previously suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-3.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2022/0051972) in view of Sridharan (US 2022/0406673).
Regarding claim 1, Kim shows (see, e.g., Kim: figs. 2-5) most aspects of the instant invention including a semiconductor package, comprising:
A semiconductor chip 40 (see, e.g., Kim: par. [0173])
A package structure 20 configured to accommodate the semiconductor chip 40 therein
wherein the package structure 20 comprises:
A substrate 22 having one surface 213 and the other surface opposite 214 to the one surface 213
At least one conductive via 223/241 extending through the one surface 213 and the other surface 214 of the substrate 22
A wiring layer 26 formed at the one surface 213, to transmit an electrical signal (see, e.g., Kim: par. [0208])
A chip accommodation portion 281 as a space formed through removal of a portion of a substrate 22 from the other surface 214 in a direction toward the one surface 213
A contact pad 282 connected to the wiring layer 26 and formed to be exposed through the chip accommodation portion 281
The semiconductor chip 40 inserted into the chip accommodation portion 281 and connected to the contact pad 282
wherein:
The semiconductor chip 40 is inserted after forming the wiring layer 26 (see, e.g., Kim: figs. 3b, and 4a)
The writing layer 26 extends along the one surface 213 (see, e.g., Kim: fig. 5) and includes a connection portion 24/232/282
The connection portion 252 formed on the one surface 213 of the substrate 22
Kim, however, fails to show that the connection portion 252 directly connects the contact pad 282 with a via pad 241a of one of the least one conductive via 223/241 on the one surface of the substrate 22. Sridharan, in a similar device to Kim, shows (see, e.g., Sridharan: fig. 4) that the connection portion 354 (formed on the one surface of the substrate 340) directly connects the contact pad 352 (formed on the one surface of the substrate 340) with a via pad 358 of one of the least one conductive via 345 on one surface of the substrate. Sridharan further shows that such connection is through the redistribution layer trace 354 that provides electrical interconnections between the die pads 312 and package terminals 345 (see, e.g., Sridharan: par. [0040]). Sridharan also shows that such direct connections are short paths that significantly improves electrical properties such a signal transmission rate, and substantially prevents generating of parasitic element (see, e.g., Sridharan: abstract).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the direct connection between the contact pad and the conductive via of Sridharan in the semiconductor package of Kim to provide short paths that significantly improves electrical properties such a signal transmission rate, and substantially prevents generating of parasitic element.
Kim in view of Sridharan shows (see, e.g., Sridharan: fig. 4) that the connection portion 354 is covered by the wiring layer 362/364 such that the connection portion 354 is not exposed through the chip accommodation portion (defined by the region that includes the mold compound 330).
Regarding claim 2, Kim in view of Sridharan shows (see, e.g., Kim: figs. 2-5) that:
The substrate 22 comprises a residual portion remaining after a portion of the substrate is removed to a predetermined depth (211-212) from a side of the substrate corresponding to the other surface 214 thereof in a direction toward the one surface 213 thereof (see, e.g., Kim: par. [0079])
The contact pad 282 is caused to be exposed within the chip accommodation portion 281 by removing the portion of the substrate to the predetermined depth
The contact pad 282 has a length extending from one surface toward the chip accommodation portion that is greater than a thickness of the residual portion after the substrate is removed to form the chip accommodation portion such that the contact pad 282 extends through the residual portion
Regarding claim 3, Kim in view of Sridharan shows (see, e.g., Kim: figs. 2-5) that:
A first bump 283 formed at the contact pad 282
A portion of the first bump 283 protruding into the interior of the chip accommodation portion 281 at the residual portion
Response to Arguments
Applicants’ arguments have been considered but are moot in view of the new grounds of rejection.
Examiner has read and considered Applicants’ arguments.
The applicants argue:
Kim fails to disclose or otherwise render obvious "the connection portion formed on the one surface of the substrate directly connects the contact pad with a via pad of one of the at least one conductive via on the one surface of the substrate," as recited in amended claim 1.
The examiner responds:
In view of the new grounds of rejection, Sridharan, in a similar device to Kim, shows (see, e.g., Sridharan: fig. 4) that the connection portion 354 (formed on the one surface of the substrate 340) directly connects the contact pad 352 (formed on the one surface of the substrate 340) with a via pad 358 of one of the least one conductive via 345 on one surface of the substrate. Sridharan further shows that such connection is through the redistribution layer trace 354 that provides electrical interconnections between the die pads 312 and package terminals 345 (see, e.g., Sridharan: par. [0040]). Sridharan also shows that such direct connections are short paths that significantly improves electrical properties such a signal transmission rate, and substantially prevents generating of parasitic element (see, e.g., Sridharan: abstract).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the direct connection between the contact pad and the conductive via of Sridharan in the semiconductor package of Kim to provide short paths that significantly improves electrical properties such a signal transmission rate, and substantially prevents generating of parasitic element.
Kim in view of Sridharan shows (see, e.g., Sridharan: fig. 4) that the connection portion 354 is covered by the wiring layer 362/364 such that the connection portion 354 is not exposed through the chip accommodation portion (defined by the region that includes the mold compound 330).
Conclusion
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, this action is made final. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIBERIU DAN ONUTA whose telephone number is (571) 270-0074 and between the hours of 9:00 AM to 5:00 PM (Eastern Standard Time) Monday through Friday or by e-mail via Tiberiu.Onuta@uspto.gov. If attempts to reach the examiner by telephone or email are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/TIBERIU DAN ONUTA/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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