Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hattori et al. (US 2020/0381557, as disclosed in previous office action).
As for claim 1, Hattori et al. disclose in Figs. 6-7 and the related text a semiconductor device comprising:
a first electrode 16;
a second electrode 18;
a first oxide semiconductor layer 10 provided between the first electrode and the second electrode, and extending in a first (vertical) direction (fig. 6);
a gate electrode 12 around the first oxide semiconductor layer (Figs. 6-7);
a second oxide semiconductor layer 22 provided between the gate electrode and the first oxide semiconductor layer, and extending in the first direction (figs. 6-7); and
a gate insulating layer 14 provided between the gate electrode and the second oxide semiconductor layer (fig. 6-7), wherein a length of (a lower portion of) the second oxide semiconductor layer 22 is shorter than a length of (an entire of) the first oxide semiconductor layer 10 in the first direction (Fig. 6-7).
As for claim 2, Hattori et al. disclose the semiconductor device according to claim 1, wherein the first oxide semiconductor layer 10 is in contact with the first electrode 16 and the second electrode 18 (fig. 6).
As for claim 3, Hattori et al. disclose the semiconductor device according to claim 1, wherein the gate insulating layer 14 further includes a portion provided between the second oxide semiconductor 22 layer and the first electrode 12 (figs. 6-7).
As for claim 4, Hattori et al. disclose the semiconductor device according to claim 1, wherein the first oxide semiconductor layer 10 includes a first portion surrounded by the first electrode 10 (fig. 6-7).
As for claim 5, Hattori et al. disclose the semiconductor device according to claim 1, wherein the gate electrode 12 surrounds the first oxide semiconductor layer 10 (fig. 6-7).
As for claim 6, Hattori et al. disclose the semiconductor device according to claim 1, wherein a chemical composition of the first oxide semiconductor layer 10 [0027] and a chemical composition of the second oxide semiconductor layer 22 are different from each other [0083].
As for claim 21, Hattori et al. disclose the semiconductor device according to claim 1, wherein the gate insulating layer 14 provided between the second oxide semiconductor layer 22 and the first electrode 16 (Fig. 6).
Claim Rejections - 35 USC § 103
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Hattori et al..
As for claims 7-8, Hattori et al. disclose the semiconductor device according to claim 6, except wherein an atomic concentration of indium (In) of the second oxide semiconductor layer is higher than an atomic concentration of indium (In) of the first oxide semiconductor layer; or wherein an atomic concentration of gallium (Ga) of the first oxide semiconductor layer is higher than an atomic concentration of gallium (Ga) of the second oxide semiconductor layer.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to include an atomic concentration of indium (In) of the second oxide semiconductor layer is higher than an atomic concentration of indium (In) of the first oxide semiconductor layer; or an atomic concentration of gallium (Ga) of the first oxide semiconductor layer is higher than an atomic concentration of gallium (Ga) of the second oxide semiconductor layer, in order to reduce the resistivity of the device.
Generally, differences in concentration do not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration is critical. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 105 USPQ 233, 235 (CCPA 1955). See also In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Laboratories Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989), and In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990).
Response to Arguments
Applicant's response filed on 12/22/2025 is acknowledged and is answered as follows.
Applicant’s arguments, see pgs. 6-7, with respect to the rejection of claim 1 and 21 that Hattori et al. do not disclose a length of the second oxide semiconductor layer is shorter than a length of the first oxide semiconductor layer in the first direction and the gate insulating layer provided between the second oxide semiconductor layer and the first electrode have been fully considered but they are not persuasive in view of the following reasons.
Claim does not clearly define the length of the first oxide semiconductor and the length of the second oxide semiconductor layer. For broad interpretation, a length of the first oxide semiconductor and a length of the second oxide semiconductor layer can consider as the length of a portion of the first oxide semiconductor and the length of an entire of the second oxide semiconductor layer.
Therefore, Hattori et al. teach in Fig. 6-7 a length of (a lower portion of) the second oxide semiconductor layer 22 is shorter than a length of (an entire of) the first oxide semiconductor layer 10 in the first (vertical) direction; and the gate insulating layer 14 provided between the second oxide semiconductor layer 22 and the first electrode 16 (in diagonal direction).
Hattori et al. still disclose the claimed invention.
In view of the foregoing reasons, the Examiner believes that all Applicant’s arguments and remarks are addressed. The Examiner has determined that the previous Office Action is still proper based on the above responses. Therefore, the rejections are sustained and maintained.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm).
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/TRANG Q TRAN/Primary Examiner, Art Unit 2811
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