DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s amendments necessitated the shift in grounds of rejection detailed below. The shift in grounds of rejection renders Applicant’s arguments moot.
See relevant art: US-20240222298-A1, US-20230420429-A1, US-20210134724-A1, US-20210134728-A1
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-15, 17 is/are rejected under 35 U.S.C. 102 (A)(1) as being anticipated by Lin et al. (US 20230136541 A1; Lin).
Regarding claim 1, Lin discloses a semiconductor package comprising: a first semiconductor die (Fig. 2H, 26; ¶64) comprising a plurality of connections (Fig. 2H, 26a; ¶65); a second semiconductor die (Fig. 2H, 26; ¶64) comprising a plurality of connections (Fig. 2H, 26a; ¶65); a redistribution layer (Fig. 2H, 20; ¶64) comprising a first surface (top) having upper connections (Fig. 2H, 202; ¶61) coupled to the first and second semiconductor dies and a second surface (bottom) having lower connections (Fig. 2H, 201 coplanar with bottom surface of RDL; ¶61), wherein particular upper connections are electrically coupled to particular lower connections by metallization (Fig. 2H, 201; ¶61) within the redistribution layer; and an interconnect bridge (Fig. 2H, 2A; ¶52/64) overlapping a portion of the first and second semiconductor dies, the interconnect bridge comprising upper connections (Fig. 2H, top 21a; ¶64) bonded to the lower connections of the redistribution layer and lower connections (Fig. 2H, 22a; ¶52), the interconnect bridge comprising: a first plurality of conductors (Fig. 2H, not shown; ¶64) configured to electrically couple the plurality of connections of a first semiconductor die and the plurality of connections of the second semiconductor die through the redistribution layer by using the paired upper (Fig. 2H, 202; ¶61) and lower connections (Fig. 2H, 201 coplanar with bottom surface of RDL; ¶61) of the redistribution layer (Fig. 2H, 20; ¶64) at laterally separated locations; and a second plurality of conductors (Fig. 2H, 210; ¶53,81) that traverse through the thickness of the interconnect bridge to electrically couple particular lower connections of the interconnect bridge to particular upper connections of the interconnect bridge and to power-input (Fig. 2H, pads 26a; ¶65,81) connections of the first and second semiconductor dies in a region where the interconnect bridge overlaps the first and second semiconductor dies.
Regarding claim 2, Lin discloses the semiconductor package of claim 1, wherein the interconnect bridge (Fig. 2H, 2A; ¶52/64) is substrateless.
Applicant defines the bridge substrate as being attached to a metallization layer.
Lin bridge comprises a layer called a substrate. However, it is an integral part of the interconnect bridge rather than attached to the interconnect bridge. In light of applicant’s discussion the bridge 2A is substrateless..
Regarding claim 3, Lin discloses the semiconductor package of claim 1, wherein the interconnect bridge (Fig. 2H, 2A; ¶52/53/64) is a metallization layer of a silicon bridge die.
Regarding claim 4, Lin discloses the semiconductor package of claim 1, wherein the redistribution layer (Fig. 2H, 20; ¶64) is an organic redistribution layer comprising polyimide. (¶62)
Regarding claim 6, Lin discloses the semiconductor package of claim 1, wherein the redistribution layer (Fig. 2H, 20; ¶64) comprises copper conductors.(¶62)
Regarding claim 7, Lin discloses the semiconductor package of claim 1, wherein the first plurality of conductors (Fig. 2H, not shown; ¶64) are interface signal conductors and the second plurality of conductors are power conductors. (Fig. 2H, 210; ¶53/81)
Regarding claim 8, Lin discloses the semiconductor package of claim 1, wherein the second plurality of conductors (Fig. 2H, 210; ¶53/81) traverse through the thickness of the interconnect bridge from a first solder bump (Fig. 2G-1, 27A; ¶72) on one or more lower connections (Fig. 2H, 22a; ¶52) of the interconnect bridge (Fig. 2H, 2A; ¶52/53/64) to one or more lower connections (Fig. 2H, 201 coplanar with bottom surface of RDL; ¶61) of the redistribution layer. (Fig. 2H, 20; ¶64)
Regarding claim 9, Lin discloses the semiconductor package of claim 1, wherein the plurality of connections (Fig. 2H, 26A; ¶65) of the first (Fig. 2H, 26; ¶64) and second (Fig. 2H, 26; ¶64) semiconductor dies are coupled to solder bumps ((Fig. 2H, 260; ¶65), and the upper connections (Fig. 2H, 202; ¶61) of the redistribution layer (Fig. 2H, 20; ¶64) are coupled to the first and second semiconductor dies connections through the solder bumps.
Regarding claim 10, Lin discloses the semiconductor package of claim 1, further comprising a third plurality (Fig. 2H, 23; ¶47) of conductors that traverse through the thickness of the interconnect bridge and are electrically coupled to one or more connections of the first (Fig. 2H, 26A; ¶65) and second (Fig. 2H, 26A; ¶65) semiconductor dies (Fig. 2H, 26; ¶64) in regions where the interconnect bridge (Fig. 2H, 2A; ¶52/53/64) does not overlap the first or second semiconductor dies.
Regarding claim 11, Lin discloses the semiconductor package of claim 10, wherein the lower connections (Fig. 2H, 22A; ¶52) of the interconnect bridge (Fig. 2H, 2A; ¶52/53/64) are in a same plane (length of third plurality of conductors laterally overlapping lower connections) as connections to the third plurality of conductors (Fig. 2H, 23; ¶47).
Regarding claim 12, Lin discloses the semiconductor package of claim 1, wherein the upper (Fig. 2H, 202; ¶61) and lower (Fig. 2H, 201 coplanar with bottom surface of RDL; ¶61) connections of the redistribution layer (Fig. 2H, 20; ¶64) are in different positions.
Regarding claim 13, Lin discloses the semiconductor package of claim 10, further comprising a circuit board (Fig. 2H, not shown; ¶78) comprising a plurality of connections (not shown ) electrically coupled to the lower connections (Fig. 2H, 22A; ¶52) of the interconnect bridge (Fig. 2H, 2A; ¶52/53/64) and the connections to the third plurality of conductors (Fig. 2H, 23; ¶47) coupled to the connections of the first (Fig. 2H, 26; ¶64) and second (Fig. 2H, 26; ¶64) semiconductor dies in regions where the interconnect bridge does not overlap the first or second semiconductor dies.
Bumps 290 couple circuit board to the chips and bridge through package substrate 29.
Regarding claim 14, Lin discloses the semiconductor package of claim 13, wherein the circuit board (Fig. 2H, not shown; ¶78) connections (not shown) are electrically coupled to the lower connections (Fig. 2H, 22A; ¶52) of the interconnect bridge (Fig. 2H, 2A; ¶52/53/64) and the connections to the third plurality of conductors (Fig. 2H, 23; ¶47) through solder bumps (Fig. 2H, 27a; ¶72).
Bumps 290 couple circuit board to the chips and bridge through package substrate 29.
Regarding claim 15, Lin discloses a semiconductor package comprising: a first semiconductor die (Fig. 2H, 26; ¶64) comprising a plurality of connections (Fig. 2H, 26a; ¶65); a second semiconductor die (Fig. 2H, 26; ¶64) comprising a plurality of connections (Fig. 2H, 26a; ¶65); a redistribution layer (Fig. 2H, 20; ¶64) comprising a first surface having upper connections (Fig. 2H, 202; ¶61) coupled to the first and second semiconductor dies through first solder bumps (Fig. 2H, 260; ¶65) and a second surface having lower connections (Fig. 2H, 201 coplanar with bottom surface of RDL; ¶61), wherein particular upper connections are electrically coupled to particular lower connections by metallization (Fig. 2H, 201; ¶61)within the redistribution layer; an interconnect bridge (Fig. 2H, 2A; ¶52/53/64) overlapping a portion of the first and second semiconductor dies, the interconnect bridge comprising upper connections (Fig. 2H, 21a; ¶64) bonded to the lower connections (Fig. 2H, 201 coplanar with bottom surface of RDL; ¶61) of the redistribution layer and lower connections (of the interconnect bridge), the interconnect bridge comprising: a first plurality of conductors (Fig. 2H, not shown; ¶64) configured to electrically couple the plurality of connections of the first semiconductor die and the plurality of connections of the second semiconductor die through the solder bumps and the redistribution layer; by using the paired upper and lower connections of the redistribution layer at laterally separated locations; and a second plurality of conductors (Fig. 2H, 210; ¶53) that travers through the thickness of the interconnect bridge to electrically couple one or more particular lower connections of the interconnect bridge to particular upper connections of the interconnect bridge and through the first solder bumps to power-input (connected to 210; ¶81) connections of the first and second semiconductor dies in a region where the interconnect bridge overlaps the first and second semiconductor dies; copper pillars (Fig. 2H, 23; ¶47) formed outside the region where the interconnect bridge overlaps the first and second semiconductor dies; and a plurality of second solder bumps (Fig. 2H, 27A; ¶72) connected to the copper pillars and the lower connections of the interconnect bridge.
Regarding claim 17, Lin discloses the semiconductor package of claim 15, further comprising a circuit board (Fig. 2H, not shown; ¶78) coupled to the plurality of second solder bumps (Fig. 2H, 27A; ¶72).
Bumps 290 couple circuit board to the second solder bumps, chips, and bridge through package substrate 29.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 20230136541 A1;Lin) in view of Kuo et al. (US-20190088600-A1; Kuo)
Regarding claim 5, Lin discloses the semiconductor package of claim 1, but is silent on wherein the redistribution layer comprises silicon dioxide.
Kuo discloses a package where a redistribution layer (Fig. 1a, 110; ¶15)
comprises silicon dioxide (Fig. 1a, 116; ¶28)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to use silicon dioxide as the material to fabricate a bridge because one of ordinary skill in the art would find it obvious to use a known material
Lin discloses the claimed invention except for the material used to fabricate the bridge being silicon dioxide. It would have been obvious to one having ordinary skill in the art, before the effective filing date, to use silicon dioxide to fabricate the bridge, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. See MPEP2144.07
Claim(s) 16, 18 - 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 20230136541 A1;Lin) in view of Chiang et al. (US 20200243449 A1; Chiang)
Regarding claim 16, Lin discloses the semiconductor package of claim 15, but is silent on wherein the first solder bumps are C4 solder.
Lin does not specifically cite C4 type bumps. However C4 bumps are solder bumps. For clarity Chiang is added to show that C4 for bumps (Fig. 2, 132a/132b;¶20 Chiang) used for making electrical connections between package layers.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to use C4 bumps when making adhesive electrical connections between layers, since it has been held to be within the general skill of a worker in the art to select a known material, such has solder bumps, on the basis of its suitability for the intended use as a matter of obvious design choice. See MPEP2144.07
Regarding claim 18, Lin discloses a semiconductor package comprising: a first semiconductor die (Fig. 2H, 26; ¶64) comprising a plurality of connections (Fig. 2H, 26a; ¶65); a second semiconductor die (Fig. 2H, 26; ¶64) comprising a plurality of connections (Fig. 2H, 26a; ¶65); a redistribution layer (Fig. 2H, 20; ¶64) comprising a first surface having upper connections (Fig. 2H, 202; ¶61) in contact with connections to the first and second semiconductor dies and a second surface having lower connections (Fig. 2H, 201 coplanar with bottom surface of RDL; ¶61), wherein particular upper connections are electrically coupled to particular lower connections by metallization (Fig. 2H, 201; ¶61) within the redistribution layer; and an interconnect bridge (Fig. 2H, 2A; ¶52/53/64) overlapping a portion of the first and second semiconductor dies, the interconnect bridge comprising upper connections (Fig. 2H, 21a; ¶64) bonded to the lower connections of the redistribution layer…, the interconnect bridge comprising: a first plurality of conductors (Fig. 2H, not shown; ¶64) configured to electrically couple the plurality of connections of the first semiconductor die and the plurality of connections of the second semiconductor die through the redistribution layer by using paired upper and lower connections of the redistribution layer at laterally separated locations; and a second plurality of conductors (Fig. 2H, 210; ¶53) that traverse through the thickness of the interconnect bridge to electrically couple particular lower connections of the interconnect bridge to upper connections of the interconnect bridge and to power-input (connected to 210; ¶81) connections of the first and second semiconductor dies in a region where the interconnect bridge overlaps the first and second semiconductor dies; copper pillars ( (Fig. 2H, 23; ¶47) formed outside the region where the interconnect bridge overlaps the first and second semiconductor dies; and a plurality of second solder bumps (Fig. 2H, 27A; ¶72) connected to the copper pillars and the lower connections of the interconnect bridge.
Lin is silent on the interconnect bridge comprising upper connections coupled to the lower connections of the redistribution layer through first solder bumps
Chiang discloses a package where a bridge is connected to overlapping layers (Fig. 2, 152/160a/160b; ¶19) and chips (Fig. 2, 110/120; ¶22) through solder bumps (Fig. 2, 132a/132b;¶21)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to connect the bridge to the RDL by solder bumps because it is obvious to one of ordinary skill in the art to choose a widely known bonding technique for its suitability as a conductive adhesive, as a matter of design choice.
Also the use of solder bumps to bond and make electrical connection would yield no more than the predictable outcome which one of ordinary skill would have expected to achieve with this common tool of the trade and is therefore an obvious expedient. MPEP 2143 (D)
Regarding claim 19, Lin in view of Chiang discloses the semiconductor package of claim 18, wherein the first solder bumps (Fig. 2, 132a/132b;¶20 Chiang) are C4 solder.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to use C4 bumps when making adhesive electrical connections between layers, since it has been held to be within the general skill of a worker in the art to select a known material, such has solder bumps, on the basis of its suitability for the intended use as a matter of obvious design choice. See MPEP2144.07
Regarding claim 20, Lin in view of Chiang discloses the semiconductor package of claim 18, further comprising a circuit board (Fig. 2H, not shown; ¶78) coupled to the plurality of second solder bumps(Fig. 2H, 27A; ¶72).
Bumps 290 couple circuit board to the second solder bumps, chips, and bridge through package substrate 29.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAWRENCE C TYNES JR. whose telephone number is (571)270-7606. The examiner can normally be reached 9AM-5PM.
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/LAWRENCE C TYNES JR./ Examiner, Art Unit 2899