DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed October 23, 2025 have been fully considered but they are not persuasive.
Applicant argues the claimed “a substrate of the interconnect bridge” requires the claimed substrate to be a permanent (silicon) integral part of the bridge component itself.
The examiner disagrees. The interconnect bridge of Shih is formed on substrate 300. Therefore, substrate 300 is a substrate of the interconnect bridge until it is removed. The claim does not define an interconnect bridge substrate as argued in remarks.
To overcome the Shih rejection the claim could recite, “the interconnect bridge comprising a silicon substrate, removing the silicon substrate of the interconnect bridge to expose an interconnect layer on a surface opposite the redistribution layer”
Upon further consideration, a new ground(s) of rejection is made on claims 14-19 in view of Tsai et al. (US 20210091005 A1, Tsai), Kang et al. (US 20220045008 A1; Kang), and Rubin et al. (US 20210134728 A1; Rubin) .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8,10-13 is/are rejected under 35 U.S.C. 102(A)(1) as being anticipated by Shih (US 20180102311 A1, Shih).
Regarding claim 1, Shih discloses a semiconductor packaging process comprising: forming a redistribution layer (Fig.13, 900; ¶47) on a first surface (top of 550), the redistribution layer comprising a first redistribution layer surface (bottom) comprising a plurality of connections (Fig.13, 918; ¶49) and a second redistribution layer surface (top) comprising a plurality of connections (Fig.13, 918; ¶49) , wherein one or more particular connections on the first redistribution layer surface (bottom) are electrically coupled (Fig.13, through 914; ¶49) to one or more particular connections on the second redistribution layer surface (top), and wherein at least a portion of the plurality of connections on the first redistribution layer surface (bottom) are electrically coupled to a plurality of connections (Fig.13, 210; ¶27) on one of an interconnect bridge (Fig.13, 101; ¶29) or a plurality of semiconductor dies; bonding a plurality of connections (Fig.13, pads associated with 121/111; ¶51) of the other one of the interconnect bridge or the plurality of semiconductor dies (Fig.13, 11/12; ¶51) to at least a portion of the plurality of connections (Fig.13, 918; ¶49) on the second redistribution layer surface (top); removing a substrate (Fig.11, 300; ¶46 bridge formed on the substrate) of the interconnect bridge to expose an interconnect layer (Fig.13, 200/210; ¶25) , the interconnect layer comprising: a first plurality of conductors (Fig.13, 204; ¶27) configured to electrically couple, through the redistribution layer (Fig.13, 900; ¶47), a plurality of connections (Fig.13, pads associated with 111; ¶51) of a first semiconductor die (Fig.13, 11 ; ¶51) of the plurality of semiconductor dies and a plurality of connections (Fig.13, pads associated with 121; ¶51) of a second semiconductor die (Fig.13, 12; ¶51) of the plurality of semiconductor dies; and a second plurality of conductors (Fig.13, vias between 204/208; ¶27) configured to electrically couple one or more particular connections (Fig.13, 210; ¶27) on a first surface (bottom) of the interconnect layer to one or more connections (Fig.13, 208; ¶27) on a second exposed surface (top) of the interconnect layer, and to one or more connections (Fig.13, pads associated with 121/111; ¶51) of the first and second semiconductor dies in a region where the interconnect bridge overlaps the first and second semiconductor dies. (Fig.13, 11/12; ¶51)
Regarding claim 2, Shih discloses the process of claim 1, wherein the first surface comprises the interconnect bridge (Fig.13, 101 electrically coupled with 210; ¶29), and wherein said bonding comprises forming solder bumps (Fig.13, 111/121; ¶29) between the plurality of connections on the first redistribution layer (Fig.13, 900; ¶47) surface (bottom) and the plurality of connections on the plurality of semiconductor dies. (Fig.13, 11/12; ¶51)
Regarding claim 3, Shih discloses the process of claim 1, wherein the first surface comprises the plurality of semiconductor dies (Fig.13, 11/12; ¶51 mounted on the first surface), and wherein said bonding comprises bonding the plurality of connections (Fig.13, 918; ¶49) on the first redistribution layer (Fig.13, 900; ¶47) surface (bottom) and the plurality of connections (Fig.13, pads associated with 121/111; ¶51) on the plurality of semiconductor dies.
Regarding claim 4, Shih discloses the process of claim 1, further comprising forming solder bumps (Fig.13, 810; ¶45) on the second surface comprising the exposed interconnect layer.(Fig.13, 200; ¶25)
Regarding claim 5, Shih discloses the process of claim 4, further comprising bonding a plurality of circuit board connections (not labeled ; ¶52) on a first surface of a circuit board to the solder bumps (Fig.13, 810; ¶45) on the second surface comprising the exposed interconnect layer (Fig.13, 200; ¶25) to electrically couple the one or more connections on the second surface comprising the exposed interconnect layer to the plurality of connections of the circuit board.
Regarding claim 6, Shih discloses the process of claim 5, wherein the second surface comprising the exposed interconnect layer (Fig.13, 200; ¶25) further comprises a plurality of connections to a third plurality of conductors (Fig.13, 510; ¶34) electrically coupled to connections of the first and second semiconductor dies (Fig.13, 11/12; ¶51) in regions where the interconnect bridge (Fig.13, 101; ¶29) does not overlap the first or second semiconductor dies, and wherein said bonding the plurality of circuit board (¶52) connections on the first surface of the circuit board to the solder bumps (Fig.13, 510; ¶34) on the second surface comprising the exposed interconnect layer (Fig.13, 200; ¶25) further comprises bonding a second plurality of circuit board connections to the third plurality of conductors (through 810).
Regarding claim 7, Shih discloses the process of claim 1, wherein the interconnect layer (Fig.13, 200; ¶25-26) is a metallization layer of a silicon bridge die.
Regarding claim 8, Shih discloses the process of claim 1, wherein the redistribution layer (Fig.13, 900; ¶47-48) is an organic redistribution layer comprising polyimide. (Fig.13, 912; ¶47-48 polyimide)
Regarding claim 10, Shih discloses the process of claim 1, wherein the redistribution layer (Fig.13, 900; ¶47-48) comprises copper conductors. (Fig.13, 914; ¶47-49)
Regarding claim 11, Shih discloses the process of claim 1, wherein the first plurality of conductors (Fig.13, 204; ¶27) are interface signal conductors and the second plurality of conductors (Fig.13, vias between 204/208; ¶27) are power conductors.(¶36)
Conductors 204, 208, and associated interconnecting vias function as power and signal interfaces based on positioning and the signal from interconnect via 510.(¶36)
Regarding claim 12, Shih discloses the process of claim 1, wherein the second plurality of conductors (Fig.13, vias between 204/208; ¶27) are power conductors running vertically, at least in part, between the second surface of the interconnect bridge (Fig.13, 101; ¶29)comprising the exposed interconnect layer (Fig.13, 200; ¶25-26) and one or more of the portion of the plurality of connections on the second redistribution layer surface.
Conductors 204, 208, and associated interconnecting vias function as power and signal interfaces based on positioning and the signal from interconnect via 510.(¶36)
Regarding claim 13, Shih discloses the process of claim 1, wherein the plurality of connections on the first redistribution layer surface (Fig.13, bottom 918; ¶47-48) are in different positions along a horizontal axis than the plurality of connections on the second redistribution layer surface. (Fig.13, top 918; ¶47-48)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih (US 20180102311 A1, Shih) in view of Evans et al. (US 20170194308 A1; Evans)
Regarding claim 9, Shih discloses the process of claim 1, but is silent on wherein the redistribution layer is a fabricated redistribution layer comprising silicon dioxide.
Evans discloses a package where a die bridge is fabricated of silicon dioxide (Fig. 10, 1002; ¶128)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to use silicon dioxide as the material to fabricate a bridge because one of ordinary skill in the art would find it obvious to use a known material
Xie discloses the claimed invention except for the material used to fabricate the bridge being silicon dioxide. It would have been obvious to one having ordinary skill in the art at the time the invention was made to use silicon dioxide to fabricate the bridge, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. See MPEP2144.07
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (US 20210091005 A1, Tsai) in view of Kang et al. (US 20220045008 A1; Kang)
Regarding claim 14, Tsai discloses a semiconductor packaging process comprising: attaching a first semiconductor die (Fig. 1A, 100; ¶18) and a second semiconductor die (Fig. 1A, 110; ¶18) to a first carrier (Fig. 1A, C; ¶18); forming a molding compound 3around the first and second semiconductor dies; grinding the molding compound to form a first surface comprising a plurality of exposed connections (Fig. 1B, 104/114; ¶22) to the first and second semiconductor dies; forming a redistribution layer (Fig. 1D, 300; ¶18) on the first surface, the redistribution layer comprising a first redistribution layer surface comprising a plurality of connections and a second redistribution layer surface comprising a plurality of connections, wherein one or more particular connections (Fig. 1D, 320; ¶23) on the first redistribution layer surface (bottom) are electrically coupled to one or more particular connections (Fig. 1D, 410; ¶25) on the second redistribution layer surface, and wherein at least a portion of the plurality of connections on the first redistribution layer surface are electrically coupled to the exposed connections of the first and second semiconductor dies; bonding a plurality of connections (Fig. 1I, 434; ¶29) of an interconnect bridge (Fig. 1I, 430; ¶29) to at least a portion of the plurality of connections on the second redistribution layer surface (top); forming a plurality of copper pillars (Fig. 1I, 420; ¶27) on connections of the second redistribution layer surface outside a region of overlap between the interconnect bridge and the first and second semiconductor dies; forming a molding compound (Fig. 1J, 450; ¶31) over the interconnect bridge and copper pillars; …the interconnect layer comprising: a first plurality of conductors (Fig. 1J, 433; ¶29) configured to electrically couple, through the redistribution layer, a plurality of connections of the first semiconductor die and a plurality of connections of the second semiconductor die; …where the interconnect bridge overlaps the first and second semiconductor dies; forming solder bumps (Fig. 1M, 700; ¶35) on … exposed connections of the pillars (Fig. 1M, 420; ¶28); and removing the carrier. (Fig. 1A, C; ¶34)
Tsai is silent on removing a substrate of the interconnect bridge to expose connections to an interconnect layer of the interconnect bridge and expose connections to the copper pillars,… and a second plurality of conductors configured to electrically couple one or more particular connections on a first surface of the interconnect layer to one or more exposed connections on a second surface of the interconnect layer, and to one or more connections of the first and second semiconductor dies in a region; forming solder bumps on exposed connections of the interconnect layer and exposed connections of the pillars; and removing the carrier.
Fig. 2A- Fig. 2F is made by the same process steps as Fig. 1A- Fig. 1M, except that a difference with respect to the process previously described is that the semiconductor bridge 1430 and the integrated passive devices 1440 are directly connected to the metallization tier 1320, without intervening contact pads 410 (illustrated, e.g., in FIG. 1I) formed therebetween. Tsai discloses alternative bridge structure interchangeable with bridge 1430 formed by the same process steps as Figs 2A-2F, where the bridge (Fig. 3C, 1430; ¶40) includes through vias (Fig. 3C, 1435; ¶40) to be connected to solder bumps (Fig. 1M, 700; ¶35), establishing dual-side vertical connection between the front surface and the rear surface of the bridge. Tsai does not specifically discloses the TSVs of bridge 1430 exposed by removing the substrate.
Kang discloses a connection structure where an interconnect bridge (Figs. 4/20, 120; ¶35) comprising an interconnect layer (Figs. 4/20, 123; ¶35); and pillars (Figs. 4/20, 114-2; ¶35) outside the bridge area attached to a substrate (Figs. 4/20, 950; ¶91). The bridge and pillars are molded (Figs. 4/20, 113-1; ¶91). The substrate is removed (Fig 21;¶94) to expose connections to conductive pillar and connections to the interconnect bridge. The bridge comprises a second plurality of conductors (Figs. 4/21, 125; ¶91) configured to electrically couple one or more particular connections (Figs. 4/21, connected to 126; ¶91) on a first surface (bottom) of the interconnect layer (Figs. 4/21, 123; ¶35) to one or more exposed connections (Figs. 4/21, 124; ¶35) on a second surface (Top) of the interconnect layer, and to one or more connections (Figs. 4, 220/320; ¶35) of the first and second semiconductor dies (Figs. 4, 200/300; ¶35) in a region; forming solder bumps (Fig.4/20, 150; ¶34) on exposed connections of the interconnect layer and exposed connections of the pillars; and removing the carrier. (Figs. 4/20, 950; ¶91)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to combine the process of Kang with that of Tsai for establishing dual-side vertical connection between the front surface and the rear surface of the bridge.
Regarding claim 15, Tsai in view of Kang discloses the process of claim 14, further comprising attaching the solder bumps to a circuit board. (Fig. 1N, 800; ¶36 Tsai)
Regarding claim 16, Tsai in view of Kang discloses the process of claim 14, wherein, prior to said removing the substrate of the interconnect bridge, the plurality of copper pillars (Fig. 1I, 420; ¶27) extend vertically above the interconnect layer (Fig. 1I, 433; ¶29) of the interconnect bridge.
Claim(s) 17,18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rubin et al. (US 20210134728 A1; Rubin) in view of Tsai et al. (US 20210091005 A1, Tsai).
Regarding claim 17, Rubin discloses a semiconductor packaging process comprising: forming a plurality of copper pillars (Fig. 1B, 124; ¶48) on a surface of a carrier (Fig. 1B, 100; ¶47) over a first region; attaching an interconnect bridge (Fig. 1B, 110; ¶44-47) to the carrier; forming a molding compound (Fig. 1B, 122; ¶47) around the interconnect bridge and pillars; grinding (CMP; ¶47 mechanical polishing is grinding) the molding compound to form a first surface (top) comprising a plurality of exposed connections (not shown) to the interconnect bridge and pillars (Fig. 1B, 124; ¶48); forming a redistribution layer (Fig. 1C, 130; ¶49) on the first surface, the redistribution layer comprising a first redistribution layer surface (bottom) comprising a plurality of connections (top ends of 134/136) and a second redistribution layer surface comprising a plurality of connections (bottom ends of 134/136), wherein one or more particular connections on the first redistribution layer surface are electrically coupled (Fig. 1C, 134/136; ¶49) to one or more particular connections on the second redistribution layer surface, and wherein at least a portion of the plurality of connections on the first redistribution layer surface are electrically coupled to the exposed connections of the interconnect bridge and pillars; attaching a plurality of connections (pads not labeled) of first and second semiconductor dies (Fig. 1D, 140/150; ¶49) to at least a portion of the plurality of connections on the second redistribution layer surface; forming a molding compound (Fig. 1D, 170; ¶53) over the first and second semiconductor dies;… the interconnect layer comprising: a first plurality of conductors (Fig. 1D, on top surface of 110 connected to 136; 49) configured to electrically couple, through the redistribution layer (Fig. 1C, 130; ¶49), a plurality of connections (pads on bottom of chips not labeled) of the first semiconductor die and a plurality of connections of the second semiconductor die; and removing the carrier. (¶58)
The claim is written broadly enough that claimed carrier 100 can reasonably be interpreted as the substrate that is removed as well as the claimed carrier.
Rubin is silent on removing a substrate of the interconnect bridge to expose connections to an interconnect layer and expose connections to the copper pillars, the interconnect layer comprising: a first plurality of conductors configured to electrically couple, through the redistribution layer, a plurality of connections of the first semiconductor die and a plurality of connections of the second semiconductor die; and a second plurality of conductors configured to electrically couple one or more particular connections on a first surface of the interconnect layer to one or more exposed connections on a second surface of the interconnect layer, and to one or more connections of the first and second semiconductor dies in a region where the interconnect bridge overlaps the first and second semiconductor dies; forming solder bumps on exposed connections of the interconnect layer and exposed connections of the pillars;
However an alternate embodiment of Rubin discloses removing a substrate (Fig. 5B, 100 carrier; ¶76) of the interconnect bridge (Fig. 5B, 110; ¶77) to expose connections (Fig. 5B, bottom surface of 110; ¶77) to an interconnect layer and expose connections to the copper pillars (Fig. 5B, 504; ¶33-35,75), the interconnect layer comprising: a first plurality of conductors (Fig. 5B, top surface of 110 connected to 526; ¶,75) configured to electrically couple, through the redistribution layer (Fig. 5B, 530; ¶76), a plurality of connections (pads not labeled on bottom of chip) of the first semiconductor die (Fig. 5B,140; ¶76) and a plurality of connections (pads not labeled on bottom of chip) of the second semiconductor die (Fig. 5B,150; ¶76); and a second plurality of conductors (interlevel vias not shown; ¶45) configured to electrically couple one or more particular connections on a first surface of the interconnect layer to one or more exposed connections (not shown coupled to 546) on a second surface (bottom) of the interconnect layer, and to one or more connections of the first and second semiconductor dies in a region where the interconnect bridge overlaps the first and second semiconductor dies (interlevel vias between 526 and 546 not shown; ¶45); forming solder bumps (Fig. 5B,580; ¶77) on exposed connections (exposed to stack of 546/554/580) of the interconnect layer and exposed (exposed to 544/554/580) connections of the pillars; (Fig. 5B, 504; ¶33-35,75)
Rubin discloses figure 3 is made in same way as figure 1. Figure 4 is made in the same way as figure 3. Figure 5 is made in the same way as figure 4. The difference is in this embodiment, the chip interconnect bridge 110 is constructed to have a network of wiring/traces that extend from the bottom surface to the upper surface of the chip interconnect bridge 110 to provide package-to-die connections (e.g., vertical power/ground distribution and/or I/O signal distribution) through the chip interconnect bridge 110. Therefore, figure 5 is compatible with figure 1.
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to use the interconnect bridge of figure 5A and Fig. 5B for providing to provide package-to-die connections through the bridge.
Regarding claim 18, Rubin discloses the process of claim 17, further comprising attaching the solder bumps (Fig. 1E, 180; ¶59) to a circuit board. (Fig. 1E, 192; ¶59)
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rubin et al. (US 20210134728 A1; Rubin) in view of Tsai et al. (US 20210091005 A1, Tsai) and further in view of Liao et al. (US 2019009685 A1; Liao).
Regarding claim 19, Rubin discloses process of claim 17, but is silent on wherein, prior to said grinding, the plurality of copper pillars extend vertically above an interconnect layer of the interconnect bridge.
Liao discloses a process of forming an interconnect bridge pillar structure where prior to grinding (¶29) the pillars (Fig. 1H, 24; ¶23) are vertically above an interconnect layer (Fig. 1H, 25; ¶24) of the interconnect bridge. (Fig. 1H, 27; ¶24)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to reduce process steps by grinding the pillars and mold in the same step.
Conclusion
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/LAWRENCE C TYNES JR./Examiner, Art Unit 2899