DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office action is in response to the RCE filed 2/20/2026 with claims filed 12/23/2025 in which claims 1, 25, 32-34, and 38 were amended.
Claims 1-38 are pending with claims 12, 13, and 19-33 remaining withdrawn and claims 1-11, 14-18, and 34-38 presented for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5-9, 14-18, 34, 35, and 38 are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al (US 2020/0373420 and Chou hereinafter).
As to claims 1, 2, 5-9, and 14-18: Chou discloses [claim 1] a power device (Fig. 6) comprising: a channel layer (112; [0020]); a source electrode (131; [0024]) and a drain electrode (141; [0024]) on both sides of the channel layer (112), respectively; a gate electrode (121; [0024]) over the channel layer (112) between the source electrode (131) and the drain electrode (141); a first field plate (comprising 132 and 133; [0037]) above the gate electrode (121) and extending in a direction (horizontal direction) from the gate electrode (121) toward the drain electrode (141), the first field plate (comprising 132 and 133) including a metal (132 and 133 can comprise the same types of material as 122, which includes metal layers; [0038] and [0035]); a first dielectric layer (151; [0037]) on a lower surface (lower surface of 133) of the first field plate (comprising 132 and 133), a side surface of the first field plate, or both the lower surface of the first field plate and the side surface of the first field plate; a barrier layer (113; [0020]) on the channel layer (112); and a second dielectric layer (comprising 150 and 152; [0028]) at least partially in a space between the gate electrode (121) and the drain electrode (141), wherein the second dielectric layer (comprising 150 and 152) directly contacts the barrier layer (113), and wherein the second dielectric layer (comprising 150 and 152) directly contacts sidewalls (vertical portions of 121) and an upper surface (top surface adjacent of 121 adjacent to 122) of the gate electrode (121); [claim 2] wherein the first field plate (comprising 132 and 133) contacts the source electrode (131) and is integral (as 131, 132, and 133 are all connected, they are interpreted to be integral) with the source electrode (131); [claim 6] wherein the first dielectric layer (151) fills a space between the first field plate (comprising 132 and 133) and the gate electrode (121); [claim 7] wherein the second dielectric layer (comprising 150 and 152) covers the first field plate (comprising 132 and 133) and the first dielectric layer (151); [claim 9] the second dielectric layer (150) is in a space between the first field plate (comprising 132 and 133) and the gate electrode (121); [claim 14] further comprising: a second field plate (comprising 142 and 143; [0037]) connected to the drain electrode (141) and extending in a direction (143 extends horizontally toward 121 on the left side) from the drain electrode (141) toward the gate electrode (121); [claim 15] wherein the channel layer (112) includes a GaN-based material (GaN; [0023]); [claim 16] wherein the barrier layer (113) is configured to induce a 2-dimensional electron gas (2DEG) (2DEG; [0023]) in the channel layer (112); [claim 17] wherein the barrier layer (113) includes a nitride including at least one of Al, Ga, In, and B (AlGaN; [0023]), and the gate electrode (121) is in direct contact (114 is optional and can thus be withheld such that 121 touches 113; [0024]) with the barrier layer (113); [claim 18] wherein the gate electrode (121) includes at least one of Ni, Pt, Pd, and Au (Au, Ni, Pt, or Pd; [0025]).
Chou fails to expressly disclose [claims 1, 6, 7, and 9] where the first dielectric is a high-k dielectric; where the second dielectric is a low-k dielectric; [claim 5] wherein the high-k dielectric layer includes at least one of SiON, SiN, Al2O3, HfO, and ZrO; [claim 8] wherein the low-k dielectric layer includes SiO.
Chou discloses that the dielectric layer 150 can be a single layer or multi-layers of materials such as silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric materials, etc., see [0029]. Chou further discloses that the dielectric layers 151 and 152 can be of a material selected from the materials for forming the dielectric layer 150, see [0038]-[0039].
Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to choose the claimed first dielectric layer (151 of Chou) to be a high-k dielectric such as silicon nitride or silicon oxynitride and the claimed second dielectric (comprising 150 and 152 of Chou) to be SiO (the application identifies SiO as low-k) as stated in KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007), a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing the claimed dielectric layers from the list of materials listed in Chou; if this leads to the anticipated success, in the instant case layers that can electrically isolate the field plates and gate electrode from one another, it is likely the product not of innovation but of ordinary skill.
As to claims 34, 35, and 38: Chou discloses [claim 34] a power device (Fig. 6) comprising: a channel layer (112; [0020]); a source electrode (131; [0024]), a gate electrode (121; [0024]), and a drain electrode (141; [0024]) spaced apart from each other in a first direction (right horizontal direction) on the channel layer (112), the gate electrode (121) between the source electrode (131) and the drain electrode (141); a first metal structure (comprising 132 and 133; [0037]) on the source electrode (131) and spaced apart from the gate electrode (121), the first metal structure including a first field plate (133; [0037]), the first field plate (133) extending in the first direction (horizontal direction) over the gate electrode (121) such that a lower surface of the first field plate (133) faces the gate electrode (121), and a side surface of the first field plate (133) is over a region of the channel layer (112) between the gate electrode (121) and the drain electrode (141); a first dielectric layer (151; [0037]) on a lower surface (lower surface of 133) of the first field plate (133), the side surface of the first field plate, or both the lower surface of the first field plate and the side surface of the first field plate; a barrier layer (113; [0020]) on the channel layer (112); and a second dielectric layer (comprising 150 and 152; [0028]) at least partially in a space between the gate electrode (121) and the drain electrode (141), wherein the second dielectric layer (comprising 150 and 152) directly contacts the barrier layer (113), and wherein the second dielectric layer (comprising 150 and 152) directly contacts sidewalls (vertical portions of 121) and an upper surface (top surface adjacent of 121 adjacent to 122) of the gate electrode (121); [claim 35] wherein the first metal structure (comprises 132 and 133) includes a vertical portion (132 and portion of 133 that is directly over 132), the vertical portion (132 and portion of 133 that is directly over 132) extends from a top surface of the source electrode (131) in a direction perpendicular (vertical direction) to the top surface of the source electrode (131), and the first field plate (133) extends in the first direction (horizontal direction) from a sidewall (right sidewall of portion of 133 that is directly over 132) of the vertical portion (132 and portion of 133 that is directly over 132); [claim 38] further comprising: a second metal structure (comprising 142 and 143; [0037]) on the drain electrode (141), wherein the second metal structure (comprising 142 and 143) is spaced apart from the gate electrode (121) and the first metal structure (comprising 132 and 133), the second metal structure (comprising 142 and 143) includes a second field plate (143), and the second field plate (left side of 143) extends toward the first metal structure (comprising 132 and 133) in a direction (left horizontal direction) opposite the first direction.
Chou fails to expressly disclose [claim 34] where the first dielectric is a high-k dielectric; where the second dielectric is a low-k dielectric.
Chou discloses that the dielectric layer 150 can be a single layer or multi-layers of materials such as silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric materials, etc., see [0029]. Chou further discloses that the dielectric layers 151 and 152 can be of a material selected from the materials for forming the dielectric layer 150, see [0038]-[0039].
Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to choose the claimed first dielectric layer (151 of Chou) to be a high-k dielectric such as silicon nitride or silicon oxynitride and the claimed second dielectric (comprising 150 and 152 of Chou) to be SiO (the application identifies SiO as low-k) as stated in KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007), a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing the claimed dielectric layers from the list of materials listed in Chou; if this leads to the anticipated success, in the instant case layers that can electrically isolate the field plates and gate electrode from one another, it is likely the product not of innovation but of ordinary skill.
Claims 3, 4, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Chou as applied to claims 1 and 9 above, and further in view of Banerjee et al (US 2020/0335617 and Banerjee hereinafter).
As to claim 3: Although the structure disclosed by Chou shows substantial features of the claimed invention (discussed in paragraph 7 above), it fails to expressly disclose:
wherein the first field plate has a thickness of about 10 nm to about 10 μm.
Banerjee in Fig. 7 shows a field plate 726/7262 that can have a same thickness as 522/526, see [0056]. Banerjee discloses in [0049] that the thickness of 522/526 can be between 50 nm and 500 nm.
As stated in MPEP 2144.05(I), “[i]n the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976)”.
As to claim 4: Although the structure disclosed by Chou shows substantial features of the claimed invention (discussed in paragraph 7 above), it fails to expressly disclose:
wherein the high-k dielectric layer has a thickness of about 100 nm to about 3 μm.
Chou discloses that the low-k and high-k dielectric layers are ILD layers.
Banerjee discloses in Fig. 7 ILD layers 500, 600, and 700, where each ILD can have a thickness in a range from 50 nm to 500 nm, see [0047], [0050], and [0055].
It is well known in the prior art that the thickness of the ILD layer affects electrical isolation and cross-talk between adjacent conductive features.
Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to choose an ILD thickness of Chou to be within the claimed range from the teachings of ILD thicknesses in Banerjee that overlap with the claimed range for the purposes of providing an ILD of sufficient thickness to reduce or prevent cross-talk and improve electrical isolation between adjacent conductive features. Further, as stated in MPEP 2144.05(I), “[i]n the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976)”.
As to claim 10: Although the structure disclosed by Chou shows substantial features of the claimed invention (discussed in paragraph 7 above), it fails to expressly disclose:
wherein the low-k dielectric layer has a thickness of about 100 nm to about 3 μm.
Chou discloses that the low-k and high-k dielectric layers are ILD layers.
Banerjee discloses in Fig. 7 ILD layers 500, 600, and 700, where each ILD can have a thickness in a range from 50 nm to 500 nm, see [0047], [0050], and [0055].
It is well known in the prior art that the thickness of the ILD layer affects electrical isolation and cross-talk between adjacent conductive features.
Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to choose an ILD thickness of Chou to be within the claimed range from the teachings of ILD thicknesses in Banerjee that overlap with the claimed range for the purposes of providing an ILD of sufficient thickness to reduce or prevent cross-talk and improve electrical isolation between adjacent conductive features. Further, as stated in MPEP 2144.05(I), “[i]n the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976)”.
Claims 11, 36, and 37 are rejected under 35 U.S.C. 103 as being unpatentable over Chou as applied to claims 1 and 34 above, and further in view of Kudymov et al (US 2016/0190297 and Kudymov hereinafter).
As to claim 11: Although the structure disclosed by Chou shows substantial features of the claimed invention (discussed in paragraph 7 above), it fails to expressly disclose:
further comprising: a plurality of first field plates above the gate electrode, wherein the first field plate is one of the plurality of first field plates, lengths of the plurality of first field plates gradually increase in the direction from the gate electrode toward the drain electrode as a distance of the plurality of first field plates increases from the channel layer.
Kudymov discloses a nitride-based semiconductor further comprising: a plurality of first field plates (Fig. 2; 145 and 210; [0042]) above the gate electrode (135; [0042]), wherein the first field plate (145) is one of the plurality of first field plates (comprising 145 and 210), lengths of the plurality of first field plates gradually increase in the direction (horizontal direction) from the gate electrode (135) toward the drain electrode (130; [0042]) as a distance of the plurality of first field plates increases from the channel layer (as shown in the Figure, the distance between the rightmost edge of each field plate 145 and 210 decreases, thus the length increases, and the drain electrode 130 as one moves further from the channel layer 105; [0044]-[0045]).
Therefore, given the teachings of Kudymov, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Chou by employing the well-known or conventional features of HEMT fabrication, such as displayed by Kudymov, by employing a plurality of field plates over the gate electrode, where the length of the field plates increases as one moves vertically further away from the channel layer in order to improve breakdown voltage of the device ([0005]) and improve the shielding surface states and prevent the exchange of surface charges ([0043]).
As to claims 36 and 37: Although the structure disclosed by Chou shows substantial features of the claimed invention (discussed in paragraph 8 above), it fails to expressly disclose:
[claim 36] wherein the first metal structure includes a plurality of first field plates spaced apart from each other in a vertical direction along the vertical portion of the first metal structure, the plurality of first field plates include the first field plate, and the plurality of first field plates extend different lengths in the first direction; [claim 37] further comprising: a plurality high-k dielectric layers on lower surfaces of the plurality of first field plates, side surfaces of the plurality of first field plates, or both the lower surfaces of the plurality of first field plates and the side surfaces of the plurality of first field plates.
Kudymov discloses a nitride-based semiconductor [claim 36] wherein the first metal structure includes a plurality of first field plates (Fig. 2; comprising 145 and 210; [0042]) spaced apart from each other in a vertical direction along the vertical portion of the first metal structure, the plurality of first field plates (comprising 145 and 210) include the first field plate (145), and the plurality of first field plates (comprising 145 and 210) extend different lengths in the first direction (as shown in the Figure, the distance between the rightmost edge of each field plate 145 and 210 decreases, thus the length increases, and the drain electrode 130 as one moves further from the channel layer 105; [0044]-[0045]).
As to [claim 37] further comprising: a plurality high-k dielectric layers on lower surfaces of the plurality of first field plates, side surfaces of the plurality of first field plates, or both the lower surfaces of the plurality of first field plates and the side surfaces of the plurality of first field plates, when the plurality of field plates of Kudymov are modified into the structure of Banerjee in view of Meng, each field plate will be covered by an overlying interlayer dielectric layer such as 500, 600, or 700, which have been noted as being high-k in the rejection of claim 34.
Therefore, given the teachings of Kudymov, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Chou by employing the well-known or conventional features of HEMT fabrication, such as displayed by Kudymov, by employing a plurality of field plates over the gate electrode, where the length of the field plates increases as one moves vertically further away from the channel layer in order to improve breakdown voltage of the device ([0005]) and improve the shielding surface states and prevent the exchange of surface charges ([0043]).
Response to Arguments
Applicant’s arguments with respect to claims 1-11, 14-18, and 34-38 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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JOSEPH C. NICELY
Primary Examiner
Art Unit 2813
/JOSEPH C. NICELY/Primary Examiner, Art Unit 2813
3/25/2026
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