DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12 March 2026 has been entered.
Claim and Specification Status
The Examiner acknowledges the amendments to claims 1 and 5-7 in the Applicant’s response dated 12 March 2026. The claim amendments have been addressed below.
The Examiner acknowledges the amendments to withdrawn claims 11 and 17-18 in the Applicant’s response dated 12 March 2026.
The Examiner acknowledges the addition of new claim 22 in the Applicant’s response dated 12 March 2026. The new claim has been addressed below.
The Examiner acknowledges the cancellation of claim 21 in the Applicant’s response dated 12 March 2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 9-10 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Yen-Chun Tseng et al. (US 2022/0131032 A1; hereinafter “Tseng”) in view of Yoshihiro Okada (US 2010/0181489 A1; hereinafter “Okada”).
Regarding Claim 1, Tseng teaches a semiconductor device comprising:
a semiconductor device layer (100, Fig. 1A, para [0035] describes a micro light-emitting device 100 including a semiconductor device layer) comprising:
a first semiconductor layer doped with impurities of a first conductivity type (110, Fig. 1A, para [0035] describes a first type semiconductor layer 110 wherein para [0046] describes the first type semiconductor layer may be a p-type doped semiconductor layer);
a light emitting layer provided on an upper surface of the first semiconductor layer (120, Fig. 1A, para [0036] describes a light-emitting layer 120 arranged on an upper surface of the first semiconductor layer 110);
a second semiconductor layer provided on an upper surface of the light emitting layer (172 and 174, Fig. 1A, para [0035] and para [0036] describes a second type semiconductor layer 172 and 174 arranged on an upper surface of the light emitting layer 120) and doped with impurities of a second conductivity type (172 and 174, Fig. 1A, para [0046] describes the second type semiconductor layer 172 and 174 may be an n-type doped semiconductor layer);
a first electrode at an upper portion of the semiconductor device layer (160, Fig. 1A, para [0035] describes a second type electrode 160, herein referred to as the first electrode, arranged on an upper portion of the semiconductor device layer), the first electrode being on an upper surface of the second semiconductor layer (160 and 174, Fig. 1A, para [0036] describes wherein the first electrode 160 is arranged on an upper surface of the second semiconductor layer 174); and
a second electrode at the upper portion of the semiconductor device layer (150, Fig. 1A, para [0035] describes a first type electrode 150, herein referred to as the second electrode, arranged on an upper portion of the semiconductor device layer), the second electrode being on the upper surface of the second semiconductor layer (150 and 174, Fig. 1A, para [0036] describes wherein the second electrode 150 is arranged on an upper surface of the second semiconductor layer 174); and
a passivation layer (180, Fig. 1A, para [0065] describes a passivation layer 180 covering at least side surfaces of the first electrode 160 and second electrode 150).
Tseng fails to explicitly disclose a passivation layer covering at least one from among an entirety of an upper surface of the first electrode and an entirety of an upper surface of the second electrode.
However, Okada teaches a similar semiconductor device comprising:
a passivation layer (40, Fig. 8, para [0091] describes an insulating film 40 acting as a passivation layer) covering at least one from among an entirety of an upper surface of the first electrode and an entirety of an upper surface of the second electrode (40 and 18, Fig. 8, para [0091] describes wherein the passivation layer 40 covers an entirety of an upper surface of a bias electrode 18 wherein the bias electrode 18 is a second upper electrode).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Tseng with Okada to further disclose a semiconductor device wherein a passivation film covers at least an entirety of an upper surface of a first electrode or an entirety of an upper surface of a second electrode in order to provide the advantage of suppressing creeping discharge from an electrode and further increasing insulating properties in a device increasing device performance (Okada, para [0093]).
Regarding Claim 2, the combination of Tseng and Okada discloses the semiconductor device of claim 1, wherein the passivation layer comprises a material that does not chemically react with an electrolyte (Okada, 40, Fig. 8, para [0091] describes an insulating film 40 acting as a passivation layer wherein the insulating film is a parylene film which does not chemically react with an electrolyte).
Regarding Claim 3, the combination of Tseng and Okada discloses the semiconductor device of claim 2, wherein the passivation layer comprises parylene (Okada, 40, Fig. 8, para [0091] describes an insulating film 40 acting as a passivation layer wherein the insulating film is a parylene film).
Regarding Claim 5, the combination of Tseng and Okada discloses the semiconductor device of claim 1, wherein the first electrode is electrically connected to the first semiconductor layer by the first electrode extending through the second semiconductor layer and the light emitting layer (Tseng, 160 and 110, Fig. 1A, para [0036] describes wherein the first electrode 160 may have a through hole 162 extending to the first semiconductor layer 110 wherein the first electrode 160 is electrically connected to the first semiconductor layer 110 through direct contact by extending through the second semiconductor layer 172 and 174 and the light emitting layer 120), and
wherein the second electrode electrically connected to the second semiconductor layer (Tseng, 150, Fig. 1A, para [0036] describes wherein the second electrode 150 is arranged on the second semiconductor layer 174 and para [0035] describes wherein the second electrode 150 is electrically connected to the second semiconductor layer 174 through a conductive layer 130).
Regarding Claim 9, the combination of Tseng and Okada discloses the semiconductor device of claim 1, wherein the first semiconductor layer comprises a p-type semiconductor layer (Tseng, 110, Fig. 1A, para [0046] describes wherein the first type semiconductor layer may be a p-type doped semiconductor layer), and the second semiconductor layer comprises an n-type semiconductor layer (Tseng, 172 and 174, Fig. 1A, para [0046] describes the second type semiconductor layer 172 and 174 may be an n-type doped semiconductor layer).
Regarding Claim 10, the combination of Tseng and Okada discloses the semiconductor device of claim 1, wherein the semiconductor device comprises one of a laser device, a detector device, a sensor device, a power device, and a transistor device (Okada, para [0001] describes wherein the invention relates to a radiation detector device).
Regarding Claim 22, the combination of Tseng and Okada discloses the semiconductor device of claim 1, wherein the passivation layer covers only one from among the entirety of the upper surface of the first electrode and the entirety of the upper surface of the second electrode (Okada, 40, 16 and 18, Fig. 8, para [0091] describes wherein the passivation layer 40 covers an entirety of an upper surface of a bias electrode 18 wherein the bias electrode 18 is a second upper electrode and further wherein the passivation layer 40 does not cover an entirety of an upper surface of a first lower electrode 16 as shown in Fig. 8).
Claims 6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Yen-Chun Tseng et al. (US 2022/0131032 A1; hereinafter “Tseng”) in view of Yoshihiro Okada (US 2010/0181489 A1; hereinafter “Okada”) and in further view of Junghoon Kim et al. (US 2020/0168589 A1; hereinafter “Kim”).
Regarding Claim 6, the combination of Tseng and Okada discloses the semiconductor device of claim 1, wherein the passivation layer covers the entirety of the upper surface of the second electrode (Okada, 40 and 18, Fig. 8, para [0091] describes wherein the passivation layer 40 covers an entirety of an upper surface of a bias electrode 18 wherein the bias electrode 18 is a second upper electrode)
Tseng and Okada fail to explicitly disclose the semiconductor device of claim 1, wherein the passivation layer covers the entirety of the upper surface of the first electrode and the entirety of the upper surface of the second electrode.
However, Kim teaches a similar semiconductor device, wherein the passivation layer covers the entirety of the upper surface of the first electrode and the entirety of the upper surface of the second electrode (170, Fig. 5E, para [0067] describes wherein passivation film 170 is formed to cover the first and second electrodes 152 and 156 and further covering an entire upper surface of the semiconductor device as shown in Fig. 5E).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Tseng and Okada with Kim to further disclose a semiconductor device wherein a passivation layer covers an entirety of an upper surface of a first electrode and an entirety of an upper surface of a second electrode in order to provide the well-known advantage of providing a protective layer entirely over a first electrode and a second electrode preventing potential parasitic capacitance and damage to the electrodes during subsequent manufacturing steps.
Regarding Claim 8, the combination of Tseng and Okada discloses all the limitations of claim 1.
Tseng and Okada fail to explicitly disclose the semiconductor device of claim 1, wherein the first semiconductor layer comprises an n-type semiconductor layer, and the second semiconductor layer comprises a p-type semiconductor layer.
However, Kim teaches a similar semiconductor device, wherein the first semiconductor layer comprises an n-type semiconductor layer (153, Fig. 5E, para [0047] describes the first semiconductor layer 153 as an n-type semiconductor layer), and the second semiconductor layer comprises a p-type semiconductor layer (155, Fig. 5E, para [0047] describes the second semiconductor layer 155 as a p-type semiconductor layer).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Tseng and Okada with Kim to further disclose a semiconductor device wherein a first semiconductor layer comprises an n-type semiconductor layer, and a second semiconductor layer comprises a p-type semiconductor layer in order to provide the advantage of enabling corresponding electrodes to be disposed in an upward/downward direction in a light emitting device thereby providing a great advantage capable of reducing a chip size and to further provide the well-known advantage of enabling a semiconductor device to be arranged in multiple configurations diversifying device functionality increasing the number of potential intended uses.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yen-Chun Tseng et al. (US 2022/0131032 A1; hereinafter “Tseng”) in view of Yoshihiro Okada (US 2010/0181489 A1; hereinafter “Okada”) and in further view of Jae Kwon Kim et al. (US 2018/0145224 A1; hereinafter “Kim II”).
Regarding Claim 7, the combination of Tseng and Okada discloses all the limitations of claim 1.
Tseng and Okada fail to explicitly disclose the semiconductor device of claim 1, wherein the semiconductor device further comprises an insulating layer provided between the second semiconductor layer and the first electrode, and wherein: the passivation layer extends from the upper surface of the first electrode onto a side surface of the first electrode, and extends along the side surface of the first electrode to an upper surface of the insulating layer; or the passivation layer extends from the upper surface of the second electrode onto a side surface of the second electrode, and extends along the side surface of the second electrode to the upper surface of the insulating layer.
However, Kim II teaches a similar semiconductor device, semiconductor device of claim 1, wherein the semiconductor device further comprises an insulating layer provided between the second semiconductor layer and the first electrode (133, Fig. 22, para [0160] describes a reflective insulation layer 133 covering a mesa 130, placing between a second semiconductor layer 127 and a first electrode layer 135), and
wherein:
the passivation layer extends from the upper surface of the first electrode onto a side surface of the first electrode (139 and 135, annotated Fig. 22, para [0153] describes an upper insulation layer 139 which may act as a passivation layer wherein the passivation layer 139 extends from an upper surface of the first electrode 135 onto a side surface of the first electrode 135 through an opening OP1 connecting the passivation layer 139 to the insulating layer 133), and extends along the side surface of the first electrode to an upper surface of the insulating layer (139 and 133, annotated Fig 22, para [0153] describes the passivation layer 139 which extends along the side surface of the first electrode 135 to an upper surface of the insulating layer 133 through opening OP1); or
the passivation layer extends from the upper surface of the second electrode onto a side surface of the second electrode (139 and 137, Fig. 22, para [0153] describes the passivation layer 139 wherein the passivation layer 139 extends from an upper surface of the second electrode 137 onto a side surface of the second electrode 137 through an opening OP2 connecting the passivation layer 139 to the insulating layer 133), and extends along the side surface of the second electrode to the upper surface of the insulating layer (139 and 133, annotated Fig 22, para [0153] describes the passivation layer 139 which extends along the side surface of the second electrode 137 to an upper surface of the insulating layer 133 through opening OP2).
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Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Tseng and Okada with Kim II to further disclose a semiconductor device that comprises an insulating layer provided between a second semiconductor layer and a first electrode and wherein a passivation layer extends from an upper surface of the first electrode onto a side surface of the first electrode, and extends along the side surface of the first electrode to an upper surface of the insulating layer in order to provide the advantage of further providing a layer with good reflectance on an active layer resulting in a device which may have a more controlled light transmission (Kim II, para [0178-0180]).
Response to Arguments
Applicant’s arguments with respect to claims 1-3, 5-10 and 22 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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