Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1, 14, 24 and 28 are objected to because of the following informalities:
Regarding claim 1, 3rd limitation, line 6, “the control terminal …” should correctly be “the at least one of the control terminal …”, see 2nd limitation, line 3.
Regarding claim 14, 3rd limitation, page 4, line 1, “the control terminal …” should correctly be “the at least one of the control terminal …”, see 2nd limitation, line 4.
Regarding claim 24, 3rd limitation, line 6, “the control terminal …” should correctly be “the at least one of the control terminal …”, see 2nd limitation, line 3.
Regarding claim 28, 3rd limitation, page 6, line 1, “the control terminal …” should correctly be “the at least one of the control terminal …”, see 2nd limitation, line 4.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 25, 31 and 32 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 2, discloses “the first partial matching circuit and the second partial matching circuit being in electrical communication without an intervening impedance circuit component”. It is not clear what “intervening impedance circuit component” is intended, because the specification is vague regarding claimed subject matter.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-9, 12-20, and 23-30 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KAHLOON et al. (20200059204), hereafter called KAHLOON.
Regarding claims 1, 14, 24 and 28, KAHLOON (Fig. 4) discloses a package (110) comprising: a transistor (102) formed on a die, see paras. [0017]-[0025], including a control terminal and an output terminal; and a first partial matching circuit (404) connected to at least one of the control terminal (input (112)) of the transistor (102), the first partial matching circuit (404) is inherently configured to tune an input impedance of the transistor die; the control terminal and the output terminal of the transistor coupled to a package (110) comprising the transistor die, the package including a second partial matching circuit (104) for the transistor die. Regarding harmonic frequency claimed in claim 14, wherein KAHLOON discloses second harmonic frequency and operate at a plurality of frequencies, see [0019]-[0022], [0039] and [0067]-[0072].
Regarding claims 2, 25, 31 and 32, further comprising: wherein the first partial matching circuit (404) and the second partial matching circuit (104) being in electrical communication without an intervening impedance circuit component.
Regarding claims 3 and 26, wherein the second partial matching circuit (104) for the transistor die is tunable for the transistor die to operate at a plurality of frequencies, see [0019]-[0022], [0039] and [0067]-[0072].
Regarding claims 4, 16 and 27, wherein to tune the input impedance of the transistor die comprises to increase the input impedance of the transistor die, see [0019]-[0022] , [0039] and [0066]-[0070]. These paragraphs disclose how output impedance is tuned by selecting desired inductance and capacitance values. Therefore, by selecting desired inductance and capacitance values of the input matching (504) of Figure 5, the input impedance can also be tuned.
Regarding claims 5 and 15, wherein the first partial matching circuit comprises an input partial matching circuit (404) connected to the control terminal of the transistor (102).
Regarding claims 6 and 17, wherein claim 1, 2nd limitation discloses “a first partial matching circuit connected to at least one of the control terminal of the transistor and the output terminal of the transistor”, meaning either matching circuits (404/104) can be read as claimed first partial matching circuit. Accordingly, “an output partial matching circuit” claimed in claim 6 can be read on output matching circuit (104) of KAHLOON, because it is connected to the output terminal of the transistor (102). And second partial matching circuit claimed in claim 1 is now input matching circuit (404) of KAHLOON.
Regarding claims 7 and 18, wherein the first partial matching circuit comprises an input partial matching circuit (404) connected to the control terminal of the transistor (102) and/or an output partial matching circuit (104) connected to the output terminal of the transistor (102).
Regarding claims 8 and 19, wherein the first partial matching circuit (104/304) comprises a resonator (LC) circuit, see Fig. 3.
Regarding claims 9 and 20, wherein the resonator circuit comprises a series resonator circuit including an inductive element (342) and a shunt capacitor (344) connected in series to a ground terminal, see Fig. 3.
Regarding claims 12 and 23, wherein the resonator circuit is selected to increase an input impedance of the transistor die, see [0063].
Regarding claim 13, wherein the first partial matching circuit (104/304) configured to terminate a second harmonic frequency of a signal at a fundamental operating frequency of the transistor die, see para. [0033].
Regarding claim 29, wherein the first matching circuit comprises an input matching circuit (404) connected to the control terminal of the transistor (102).
Regarding claim 30, wherein to tune the input impedance of the transistor die comprises to increase the input impedance of the transistor die, see [0019]-[0022] , [0039] and [0066]-[0070]. These paragraphs disclose how output impedance is tuned by selecting desired inductance and capacitance values. Therefore, by selecting desired inductance and capacitance values of the input matching (504) of Figure 5, the input impedance can also be tuned.
Claim(s) 1, 2, 5-7, 14, 17, 18, 24, 25, 28, 31 and 32 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Andre et al. (20230136967), hereafter called ANDRE.
Regarding claims 1, 14, 24 and 28, ANDRE (Fig. 4/6) discloses an integrated circuit comprises die (10), which comprises a transistor (60) including a control terminal (input terminal connected to RFIN) and an output terminal (connected to RFOUT); and a first partial matching circuit (50) connected to at least one of the control terminal of the transistor and the output terminal of the transistor, the first partial matching circuit is inherently configured to tune an input impedance of the transistor die; the control terminal and the output terminal of the transistor coupled to a package (30) comprising the transistor die, the package including a second partial matching circuit (70) for the transistor die.
Regarding claims 2, 25, 31 and 32, further comprising: wherein the first partial matching circuit (50) and the second partial matching circuit (70) being in electrical communication without an intervening impedance circuit component.
Regarding claims 5 and 15, wherein the first partial matching circuit comprises an input partial matching circuit (50) connected to the control terminal of the transistor (60).
Regarding claims 6 and 17, wherein claim 1, 2nd limitation discloses “a first partial matching circuit connected to at least one of the control terminal of the transistor and the output terminal of the transistor”, meaning either matching circuits (50/70) can be read as claimed first partial matching circuit. Accordingly, “an output partial matching circuit” claimed in claim 6 can be read on output matching circuit (70) of ANDRE, because it is connected to the output terminal of the transistor (60). And second partial matching circuit claimed in claim 1 is now input matching circuit (50) of ANDRE.
Regarding claims 7 and 18, wherein the first partial matching circuit comprises an input partial matching circuit (50) connected to the control terminal of the transistor (60) and/or an output partial matching circuit (70) connected to the output terminal of the transistor (60).
Regarding claim 13, wherein the first partial matching circuit (104/304) configured to terminate a second harmonic frequency of a signal at a fundamental operating frequency of the transistor die, see para. [0033].
Regarding claim 29, wherein the first matching circuit comprises an input matching circuit (404) connected to the control terminal of the transistor (102).
Regarding claim 30, wherein to tune the input impedance of the transistor die comprises to increase the input impedance of the transistor die, see [0019]-[0022] , [0039] and [0066]-[0070]. These paragraphs disclose how output impedance is tuned by selecting desired inductance and capacitance values. Therefore, by selecting desired inductance and capacitance values of the input matching (504) of Figure 5, the input impedance can also be tuned.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional reference(s) cited in PTO-892 show further analogous prior art circuitry.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Khanh V. Nguyen whose telephone number is (571) 272-1767. The examiner can normally be reached from 8:30 AM – 5:00 PM EST.
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/KHANH V NGUYEN/ Primary Examiner, Art Unit 2843
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