DETAILED ACTION
Claims 1-2 and 5-16 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 13, 2025, has been entered.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
In the substitute specification submitted on December 23, 2024, on page 18, line 24, it appears that “12” be replaced with --13--.
Claim Recommendations
In claim 1, the examiner recommends inserting a descriptor (e.g. “given”, “plurality of”, “multiple”, “associated”, “corresponding”, etc.) before “operations” in lines 3, 5, and 8, and after “to the” in line 7. While it is reasonably clear that “the operations” in line 8 refers to the operations of line 3, the additional descriptor would prevent one from misinterpreting “the operations” as a reference to the further operations of line 7.
A similar recommendation is made for claims 15-16.
Claim Interpretation
The following is a quotation of MPEP 2111.04(II):
“The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.”
“The broadest reasonable interpretation of a system (or apparatus or product) claim having structure that performs a function, which only needs to occur if a condition precedent is met, requires structure for performing the function should the condition occur. The system claim interpretation differs from a method claim interpretation because the claimed structure must be present in the system regardless of whether the condition is met and the function is actually performed.”
Claim 15 has been identified as a method claim including at least one contingent limitation. Specifically, in the last paragraph, the forwarding and allowing steps are not required to be performed if the claimed identifying does not occur. The examiner recommends preceding the final paragraph with a new paragraph setting forth --identifying that the subsequent operation uses and overwrites the result of the operation;--. The last paragraph could then be reworded as
--…in response to the identifying.--.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, 8, 10-12, and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Srinivasa et al., U.S. Patent Application Publication No. 2023/0011446 A1, in view of Warnes, U.S. Patent Application Publication No. 2002/0013691, and Katsura et al., JP 2012-168888 (a translation of which was previously provided).
Referring to claim 1, Srinivasa has taught an apparatus (FIG.2, processor) comprising: processing circuitry comprising one or more execution units (FIG.2, 112+128), the one or more execution units configured to perform operations in response to instructions (see paragraphs [0051]-[0054]);
one or more registers (FIG.2, registers 114) to store data accessed by the processing circuitry (see paragraphs [0044] and [0058]. Operands operated on by execution units are read from the register(s) and results generated by execution units are stored to the register(s));
forwarding circuitry to selectively forward results of the operations from the one or more execution units to be written back to the one or more registers and to the one or more execution units for use as operands of further operations subsequent to the operations (see paragraphs [0082]-[0083]. From FIG.3, a result of operation 130C is written to element TC (illustrated as C) on its way to the register file. While it is in TC, if a subsequent consumer operation needs that result to proceed with its operation, forwarding circuitry will forward the data in TC to that consumer operation); and
write-back reschedule circuitry configured to, for an operation of the operations:
cause a given execution unit of the one or more execution units, the given execution unit performing the operation, to stall the operation prior to a write-back stage of the given execution unit, wherein stalling the operation causes a result of the operation to be held at the given execution unit and prevents the result of the operation from being written back to the one or more registers while the operation is stalled (see paragraphs [0005] and [0061]-[0064]. The write-back of a result of an operation performed by an execution unit is stalled for at least one cycle by first writing the result to one of the temporary storage elements 128 (A, B, C, or D) of the execution unit. After the at least one stall cycle, a result is moved (written back) from one of A, B, C, and D, into the register file);
determine, based on monitoring subsequent operations to be performed by the processing circuitry, whether to forward the result of the operation to be written back to a register of the one or more registers or to forward the result of the operation to a further execution unit of the one or more execution units (again, see paragraphs [0082]-[0083]. If circuitry detects that a subsequent consumer instruction uses one of the results in A, B, C, or D, the result is forwarded to an execution unit allocated to the consumer instruction. If there is no consumer instruction, then no forwarding to an execution unit is necessary); and
control the forwarding circuitry to forward the result of the operation according to the determination (see paragraphs [0082]-[0083]. When a consumer is detected, the forwarding circuitry will be controlled to transfer the appropriate result from A, B, C, or D, to the execution unit allocated to the consumer);
wherein the write-back reschedule circuitry is configured to control the
forwarding circuitry to forward the result of the operation to the further execution unit of the one or more execution units in response to identifying a subsequent operation that uses the result of the operation (again, as described above, when an execution unit is to execute a subsequent operation that needs a value stored in a temporary storage element, that value will be forwarded to that execution unit);
Srinivasa has not taught wherein the write-back reschedule circuitry is
configured to control the forwarding circuitry to allow the result of the operation held at the given execution unit at a stage at which the operation was stalled to be overwritten without writing back the result of the operation to the one or more registers in response to identifying that the subsequent operation that uses and overwrites the result of the operation. However, Warnes has first taught an instruction whose destination register is the same as a source register of the instruction (see paragraph [0088]). This would allow an instruction’s encoding to require fewer bits since one register would need to be encoded to indicate both a source and destination. This also allows the system to discard a previous result after its used to generate a new result, which could reduce register utilization. As a result, it would have first been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Srinivasa such that the subsequent instruction both uses and overwrites the result of the operation. Furthermore, Katsura has taught reducing power consumption by suppressing the writing of the result of a preceding instruction to a register when it is detected that a subsequent instruction writes its result to the same register (see the “Background-Art” section in the provided translation). As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Srinivasa such that the write-back reschedule circuitry is configured to control the forwarding circuitry to allow the result of the operation held at the given execution unit at a stage at which the operation was stalled to be overwritten without writing back the result of the operation to the one or more registers in response to identifying that the subsequent operation that uses and overwrites the result of the operation. That is, while a result is stored in a temporary storage element, if a subsequent instruction is identified as using and writing to the same register that the result is to be written to, the result in the temporary storage would simply not be written to the register file to save power. Instead, that result will be overwritten (when it is that temporary element’s turn to be written again) without register write-back.
Srinivasa, as modified, has further taught that stalling the operation causes a result of the operation to be held at the given execution unit such that performing the subsequent operation will cause the result of the operation to be lost (the operation is stalled at the execution unit by keeping it in the temporary storage element and preventing it from being written to the register file. When a subsequent instruction both uses and overwrites the result of the operation (as taught by Warnes), the result of the operation never makes it to the register file (as taught by Katsura), i.e., it is lost (there will be no record of it in the register file)).
Referring to claim 5, Srinivasa, as modified, has taught the apparatus according to claim 1, wherein: the write-back reschedule circuitry is configured to identify the subsequent operation that uses the result of the operation based on the subsequent operation reading from a particular register to which the result of the operation is due to be written (see paragraphs [0082]-[0083]. Basically, a producer instruction that writes a value to register Rx will temporarily store that value in one of A, B, C, or D. If a subsequent consumer instruction reads from register Rx, it is forwarded the value from the one of A, B, C, or D, instead of having to retrieve the value from Rx).
Referring to claim 8, Srinivasa, as modified, has taught the apparatus according to claim 1, wherein: each execution unit has a plurality of stages (see FIG.3, which shows operations 130A-D each using an execution unit with a different number of stages (N1 to Nx)); and the write-back reschedule circuitry is configured to, for each operation, stall the operation at a stage immediately prior to the write-back stage of the given execution unit (see paragraphs [0061]-[0063]. Just after stage Nx is write-back. However, instead of actually entering that stage and writing the result to the register file, the operation is stalled by instead writing the result to a temporary storage element TX (e.g. operation 130A stores its result to storage element A)).
Referring to claim 10, Srinivasa, as modified, has taught the apparatus according to claim 1, wherein:
the write-back reschedule circuitry is configured to detect a write-back conflict where two or more conflicting operations performed by respective execution units sharing a write-back port are scheduled to reach a write-back stage of the respective execution units at the same clock cycle (see FIG.3 and paragraphs [0061]-[0064]. Basically, operations 130A and 130B are detected to be conflicting in cycle 132 and, thus, the result of 130A is written to temporary storage A and the result of 130B is written to temporary storage B. The temporary storage is required because only one result can be written per cycle on a shared port (paragraph [0020]); and
the write-back reschedule circuitry is responsive to detection of the write-back conflict to cause at least one of the execution units sharing the write-back port to stall a respective conflicting operation of the conflicting operations and to control the forwarding circuitry to forward results of the conflicting operations on different clock cycles (again, see paragraphs [0061]-[0064]. At least one operation is stalled by writing a result to temporary storage as opposed to a register file. Then forwarding of the results from temporary storage to the register file is controlled on a round-robin basis (e.g. see paragraph [0064])).
Referring to claim 11, Srinivasa, as modified, has taught the apparatus according to claim 10, wherein: the execution units sharing the write-back port have different associated latencies (see FIG.3 and paragraph [0054]. There are a different number of N stages for the execution units, which correspond to different latencies).
Claim 12 is rejected for similar reasoning as claim 11 (e.g. in FIG.3, one type of operation takes four cycles (N1-N4) in the top row, and another type takes three cycles (N1-N3) in the second row from the top).
Referring to claim 14, Srinivasa, as modified, has taught the apparatus according to claim 1, wherein: the processing circuitry comprises a vector processor (see paragraphs [0051] and [0053]).
Claim 15 is rejected for similar reasoning as claim 1.
Claim 16 is mostly rejected for similar reasoning as claim 1. Srinivasa has further taught a non-transitory computer-readable medium to store computer-readable code for fabrication of an apparatus with the claimed components of claim 16 (see FIG.7 and paragraphs [0091]-[0092]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Srinivasa in view of Warnes, Katsura, and the examiner’s taking of Official Notice.
Referring to claim 13, Srinivasa, as modified, has taught the apparatus according to claim 1, but has not taught wherein: the processing circuitry comprises a matrix processor. However, a matrix processor and/or a processor that operates on matrices was well known in the art before applicant’s invention. A matrix processor is built to more efficiently perform matrix calculations. Alternatively, any processor that is instructed to perform any well-known matrix math is a matrix processor. As a result, in order to carry out matrix functionality, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Srinivasa such that the processing circuitry comprises a matrix processor.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 15 is alternatively rejected under 35 U.S.C. 102(a)(2) as being anticipated by Srinivasa.
Referring to claim 15, when the forwarding and allowing of the last paragraph are not performed (when the identifying does not occur), claim 15 is rejected for a subset of similar reasoning set forth in the rejection of claim 1. Note that Warnes and Katsura are not relied upon for this rejection.
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-6, 8, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Patel, U.S. Patent No. 5,222,240, in view of Arakawa, WO/2012/14374 A1, and Katsura.
Referring to claim 1, Patel has taught an apparatus (at least FIG.1) comprising: processing circuitry comprising one or more execution units (from the abstract, there is an execution unit to execute data transfer instructions, such as loads. The execution unit is interpreted to include the temporary register), the one or more execution units configured to perform operations in response to instructions (from the abstract, load operations would be performed in response to load instructions);
one or more registers (FIG.2, registers 30) to store data accessed by the processing circuitry (see column 5, lines 53-60);
forwarding circuitry to selectively forward results of the operations from the one or more execution units to be written back to the one or more registers and to the one or more execution units for use as operands of further operations subsequent to the operations (see the abstract, which states that a result of an instruction may be bypassed to the proper execution block. Further, the result is eventually forwarded/written to the register file); and
write-back reschedule circuitry configured to, for an operation of the operations (for each load operation):
cause a given execution unit of the one or more execution units, the given execution unit performing the operation, to stall the operation prior to a write-back stage of the given execution unit, wherein stalling the operation causes a result of the operation to be held at the given execution unit and prevents the result of the operation from being written back to the one or more registers while the operation is stalled (see the abstract, which states that the result of a load instruction is stalled from being written to the register file until the writeback stage of the next load instruction. Until that time, the result sits in a temporary register of the execution unit);
determine, based on monitoring subsequent operations to be performed by the processing circuitry, whether to forward the result of the operation to be written back to a register of the one or more registers or to forward the result of the operation to a further execution unit of the one or more execution units (again, see the abstract. It is determined whether to bypass/forward the result in the temporary register to an execution unit allocated to a subsequent instruction that consumes that result as an operand, and it is also determined to forward the result from the temporary register to the register file when a subsequent load operation reaches its writeback stage); and
control the forwarding circuitry to forward the result of the operation according to the determination (again, see the abstract and the aforementioned reasoning);
wherein the write-back reschedule circuitry is configured to control the
forwarding circuitry to forward the result of the operation to the further execution unit of the one or more execution units in response to identifying a subsequent operation that uses the result of the operation (again, see the abstract and the reasoning set forth above);
Patel has not taught wherein the write-back reschedule circuitry is configured to control the forwarding circuitry to allow the result of the operation held at the given execution unit at a stage at which the operation was stalled to be overwritten without writing back the result of the operation to the one or more registers in response to identifying that the subsequent operation that uses and overwrites the result of the operation. However, Arakawa has first taught a subsequent load instruction whose source and destination are the same as the destination of a previous load instruction (see the paragraph spanning pages 6-7). This would allow the processor to determine which address to load based on data loaded by a previous instruction, which could increase addressing flexibility. As a result, it would have first been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Patel such that the subsequent load instruction both uses and overwrites the result of the operation. Furthermore, Katsura has taught reducing power consumption by suppressing the writing of the result of a preceding instruction to a register when it is detected that a subsequent instruction writes its result to the same register (see the “Background-Art” section in the provided translation). As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Srinivasa such that the write-back reschedule circuitry is configured to control the forwarding circuitry to allow the result of the operation held at the given execution unit at a stage at which the operation was stalled to be overwritten without writing back the result of the operation to the one or more registers in response to identifying that the subsequent operation that uses and overwrites the result of the operation. That is, if, while a result is stored in a temporary register, a subsequent load instruction is identified as writing to the same register that the result is to be written to, the result in the temporary storage would simply not be written to the register file to save power (since it’s going to be overwritten anyway). Instead, that result will be overwritten (when the subsequent load is to write its result) without register write-back.
Patel, as modified, has further taught that stalling the operation causes a result of the operation to be held at the given execution unit such that performing the subsequent operation will cause the result of the operation to be lost (the load operation is stalled at the execution unit by keeping the loaded data in the temporary register and preventing it from being written to the register file. When a subsequent load instruction both uses and overwrites the result of the operation (as taught by Arakawa), the result of the operation never makes it to the register file (as taught by Katsura), i.e., it is lost (there will be no record of it in the register file)).
Referring to claim 2, Patel, as modified, has taught the apparatus according to claim 1, wherein: the write-back reschedule circuitry is configured to control the forwarding circuitry to forward the result of the operation to be written back to a register of the one or more registers in response to identifying a subsequent operation performed by the given execution unit that is due to occupy a stage at which the operation was stalled (again, see the abstract. A first load is stalled at writeback until the next load reaches writeback. Thus, the first load’s result must be vacated from the temporary register and stored to the register file so that the second load’s result can be stored in the temporary register).
Referring to claim 5, Patel, as modified, has taught the apparatus according to claim 1, wherein: the write-back reschedule circuitry is configured to identify the subsequent operation that uses the result of the operation based on the subsequent operation reading from a particular register to which the result of the operation is due to be written (again, see the abstract and column 7, lines 3-4. This is how forwarding/bypassing works. The destination register of the load matches a source register of a subsequent instruction and, thus, instead of the subsequent instruction waiting for the result of the load to be in the register file, the result may be forwarded from the temporary register to the subsequent instruction).
Referring to claim 6, Patel, as modified, has taught the apparatus according to claim 1, wherein: the write-back reschedule circuitry is configured to cause the given execution unit to stall the operation prior to the write-back stage of the given execution unit until the write-back reschedule circuitry identifies at least one of: a subsequent operation performed by the given execution unit that is due to occupy a stage at which the operation was stalled (again, see the abstract. A first load is stalled at writeback (i.e., before writeback actually occurs) until the next load reaches writeback. Thus, the first load’s result must be vacated from the temporary register and stored to the register file so that the second load’s result can be stored in the temporary register); and a subsequent operation that uses the result of the operation.
Referring to claim 8, Patel, as modified, has taught the apparatus according to claim 1, wherein: each execution unit has a plurality of stages (see the abstract, which shows multiple stages, including “execute” and “writeback”); and the write-back reschedule circuitry is configured to, for each operation, stall the operation at a stage immediately prior to the write-back stage of the given execution unit (see the abstract. The writeback stage is deemed the stage in which the result is actually written to the register file. Thus, since a result of a load is not allowed to be written to the register file, the load is technically stalled from entering the writeback stage. In other words, the operation is stalled in a stage immediately prior to writeback).
Claim 15 is rejected for similar reasoning as claim 1.
Claims 13-14, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Patel in view of Katsura and the examiner’s taking of Official Notice.
Referring to claim 13, Patel, as modified, has taught the apparatus according to claim 1, but has not taught wherein: the processing circuitry comprises a matrix processor. However, a matrix processor and/or a processor that operates on matrices was well known in the art before applicant’s invention. Such a processor is built to more efficiently perform matrix calculations. As a result, in order to more efficiently handle matrix inputs, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Patel such that the processing circuitry comprises a matrix processor.
Referring to claim 14, Patel, as modified, has taught the apparatus according to claim 1, but has not taught wherein: the processing circuitry comprises a vector processor. However, a vector processor was well known in the art before applicant’s invention. Such a processor may perform the same operation on multiple data items at once, thereby increasing throughput. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Patel such that the processing circuitry comprises a vector processor.
Claim 16 is mostly rejected for similar reasoning as claim 1. Patel has not taught a non-transitory computer-readable medium to store computer-readable code for fabrication of an apparatus with the claims components of claim 16. However, such was well known in the art before applicant’s invention. Software on such a medium can be flexibly modified/updated to change the design to implement any improvements. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Patel to include a non-transitory computer-readable medium to store computer-readable code for fabrication of an apparatus with the claimed components of claim 16.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Patel in view of Katsura and Hennessy et al., “Computer Architecture - A Quantitative Approach”.
Referring to claim 7, Patel, as modified, has taught the apparatus according to claim 1, wherein: each execution unit has a plurality of stages (see the abstract, at least the execute and writeback stages. Also see FIGs.4-6 for various stages);
Patel has not taught that the write-back reschedule circuitry is configured to delay the determination of whether to forward the result of the operation to be written back to a register of the one or more registers or to forward the result of the operation to the further execution unit of the one or more execution units until a subsequent operation has reached a stage in the given execution unit immediately prior to a stage at which the operation is stalled. However, Hennessy has taught forwarding a result generated by DM stage, which is where data would be loaded by a load instruction, to the beginning of the execute stage when a consumer instruction reaches the execute stage, i.e., when a subsequent operation reaches a stage immediately prior to the previous operation (see p.153, Figure 3.12 and note the dotted line after the DM stage in the top row connecting to the front of the ALU in clock cycle 4. This allows for forwarding to occur immediately when the result is produced thereby maximizing throughput as opposed to stalling the very next instruction if it consumes the result of the previous instruction. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Patel such that the write-back reschedule circuitry is configured to delay the determination of whether to forward the result of the operation to be written back to a register of the one or more registers or to forward the result of the operation to the further execution unit of the one or more execution units until a subsequent operation has reached a stage in the given execution unit immediately prior to a stage at which the operation is stalled. In combination, Patel’s load retrieves the data from cache in the 4th cycle and stalls the writeback to the register file that would normally occur in the 5th cycle. Thus, the system essentially stalls the load at the end of cycle 4 where the loaded value is stored in a temp register, and will wait to forward the loaded value from the temp register to any subsequent instruction until that subsequent instruction starts its 3rd cycle, i.e., in the stage immediately preceding the stage in which the load stalled.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 15 is alternatively rejected under 35 U.S.C. 102(a)(1) as being anticipated by Patel.
Referring to claim 15, when the forwarding and allowing of the last paragraph are not performed (when the identifying does not occur), claim 15 is rejected for a subset of similar reasoning set forth in the rejection of claim 1. Note that Arakawa and Katsura are not relied upon for this rejection.
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 9-12, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Barrick et al., U.S. Patent Application Publication No. 2022/0035637 A1, in view of Srinivasa, Warnes, and Katsura.
Referring to claim 1, Barrick has taught an apparatus (FIG.1) comprising: processing circuitry comprising one or more execution units (FIG.1, at least 120, 130, and/or 140), the one or more execution units configured to perform operations in response to instructions (see paragraph [0013]. The operations may be any of the instructions that need to have their result written to a result buffer (see FIG.3));
one or more registers (FIG.1, registers 190) to store data accessed by the processing circuitry (from FIG.1, the results of pipes 120-140 are written to registers in file 190 via writeback port 180. Also, from paragraph [0015], operands are read from file 190 to process them in pipes 120-140);
forwarding circuitry to selectively forward results of the operations from the one or more execution units to be written back to the one or more registers (again, see FIG.1. Results are forwarded from execution units to file 190. Also see paragraph [0019]); and
write-back reschedule circuitry configured to, for an operation of the operations (for each operation that needs to be delayed, per FIG.3):
cause a given execution unit of the one or more execution units, the given execution unit performing the operation, to stall the operation prior to a write-back stage of the given execution unit, wherein stalling the operation causes a result of the operation to be held at the given execution unit and prevents the result of the operation from being written back to the one or more registers while the operation is stalled (see the abstract and FIG.3. Basically, if it is determined that two operations will conflict at writeback, one of the operations is stalled prior to writeback occurring by writing the operation’s result to a delayed result buffer for a number of cycles. The result buffer may be deemed part of an execution unit);
Barrick has not taught the forwarding circuitry to selectively forward results of the operations from the one or more execution units to be written back to the one or more execution units for use as operands of further operations subsequent to the operations, and also has not taught the write-back reschedule circuitry configured to determine, based on monitoring subsequent operations to be performed by the processing circuitry, whether to forward the result of the operation to be written back to a register of the one or more registers or to forward the result of the operation to a further execution unit of the one or more execution units; and control the forwarding circuitry to forward the result of the operation according to the determination. However, Srinivasa has taught that a result in a delay buffer that is waiting to be written to the register file may be forwarded to a subsequent operation that uses that value as an operand (see the abstract and paragraphs [0082]-[0083]. When a consumer is detected, the forwarding circuitry will be controlled to transfer the appropriate result from a delay buffer (A, B, C, or D in FIG.1), to the execution unit allocated to the consumer). Forwarding is a known advantageous technique in the art where a subsequent instruction may retrieve its operand before the operand is written to the register file, so as to speed up operand retrieval (and avoid potential stalling when the operand is not yet in the register file). As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Barrick to include the forwarding circuitry to selectively forward results of the operations from the one or more execution units to be written back to the one or more execution units for use as operands of further operations subsequent to the operations, and also has not taught the write-back reschedule circuitry configured to determine, based on monitoring subsequent operations to be performed by the processing circuitry, whether to forward the result of the operation to be written back to a register of the one or more registers or to forward the result of the operation to a further execution unit of the one or more execution units; and control the forwarding circuitry to forward the result of the operation according to the determination.
Barrick, as modified, has taught wherein the write-back reschedule circuitry is
configured to control the forwarding circuitry to forward the result of the operation to the further execution unit of the one or more execution units in response to identifying a subsequent operation that uses the result of the operation (again, as described above, when an execution unit is to execute a subsequent operation that needs a value stored in a temporary storage element, that value will be forwarded to that execution unit);
Barrick, as modified, has not taught wherein the write-back reschedule circuitry is
configured to control the forwarding circuitry to allow the result of the operation held at the given execution unit at a stage at which the operation was stalled to be overwritten without writing back the result of the operation to the one or more registers in response to identifying that the subsequent operation uses and overwrites the result of the operation. However, Warnes has first taught an instruction whose destination register is the same as a source register of the instruction (see paragraph [0088]). This would allow an instruction’s encoding to require fewer bits since one register would need to be encoded to indicate both a source and destination. This also allows the system to discard a previous result after its used to generate a new result, which could reduce register utilization. As a result, it would have first been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Barrick such that the subsequent instruction both uses and overwrites the result of the operation. Furthermore, Katsura has taught reducing power consumption by suppressing the writing of the result of a preceding instruction to a register when it is detected that a subsequent instruction writes its result to the same register (see the “Background-Art” section in the provided translation). As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Barrick such that the write-back reschedule circuitry is configured to control the forwarding circuitry to allow the result of the operation held at the given execution unit at a stage at which the operation was stalled to be overwritten without writing back the result of the operation to the one or more registers in response to identifying that the subsequent operation uses and overwrites the result of the operation. That is, if, while a result is stored in the result buffer, a subsequent instruction is identified as using and writing the same register that the result is to be written to, the result in the result buffer would simply not be written to the register file to save power. Instead, that result will be overwritten (ultimately by another result written to the result buffer) without register write-back.
Barrick, as modified, has further taught that stalling the operation causes a result of the operation to be held at the given execution unit such that performing the subsequent operation will cause the result of the operation to be lost (the operation is stalled at the execution unit by keeping it in the temporary storage element and preventing it from being written to the register file. When a subsequent instruction both uses and overwrites the result of the operation (as taught by Warnes), the result of the operation never makes it to the register file (as taught by Katsura), i.e., it is lost (there will be no record of it in the register file)).
Referring to claim 9, Barrick, as modified, has taught the apparatus according to claim 1, the apparatus further comprising:
data location tracking circuitry to maintain information identifying, for each of a plurality of operations, the given execution unit to which the operation was allocated and a number of clock cycles until the operation reaches a stage immediately prior to the write-back stage of the given execution unit (see paragraphs [0015], [0017], and [0024]-[0025]. The tracking circuitry knows which instructions are in which pipeline 120-140, and determines the number of cycles until each operation will reach RES, which is immediately prior to writeback, per FIG.1);
wherein the write-back reschedule circuitry is configured to reference the information maintained by the data location tracking circuitry to determine whether to forward the result of the operation to be written back to a register of the one or more registers (the tracking information is references to determine whether to forward the data to the register file (i.e., there is no writeback conflict), or if the data must instead be forwarded to a delayed buffer 150 for a number of cycles determined based on the tracking information (FIG.3)) or to forward the result of the operation to the further execution unit of the one or more execution units.
Referring to claim 10, Barrick, as modified, has taught the apparatus according to claim 1, wherein:
the write-back reschedule circuitry is configured to detect a write-back conflict where two or more conflicting operations performed by respective execution units sharing a write-back port are scheduled to reach a write-back stage of the respective execution units at the same clock cycle (see FIG.1 and the abstract. Multiple pipelines 120-140 share a writeback (WB) port and, thus, there may be collisions if two instructions need to use the WB port at the same time. Such collisions are detected); and
the write-back reschedule circuitry is responsive to detection of the write-back conflict to cause at least one of the execution units sharing the write-back port to stall a respective conflicting operation of the conflicting operations and to control the forwarding circuitry to forward results of the conflicting operations on different clock cycles (see the abstract and note that in response to collisions, delays are added via result buffer 150 such that forwarding of the results of the colliding instructions to the register files occurs on different cycles).
Referring to claim 11, Barrick, as modified, has taught the apparatus according to claim 10, wherein: the execution units sharing the write-back port have different associated latencies (see FIG.1, pipes 120-140 and paragraph [0013]).
Referring to claim 12, Barrick, as modified, has taught the apparatus according to claim 10, wherein: the execution units sharing the write-back port are operable to perform at least two types of operation; and the types of operation are performed with different latencies (see FIG.1 and paragraph [0013]).
Claim 15 is rejected for similar reasoning as claim 1.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Barrick in view of Srinivasa, Warnes, Katsura, and the examiner’s taking of Official Notice
Claim 16 is mostly rejected for similar reasoning as claim 1. Barrick has not taught a non-transitory computer-readable medium to store computer-readable code for fabrication of an apparatus with the claimed components of claim 16. However, such was well known in the art before applicant’s invention. Software on such a medium can be flexibly modified/updated to change the design to implement any improvements. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Barrick to include a non-transitory computer-readable medium to store computer-readable code for fabrication of an apparatus with the claimed components of claim 16.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 15 is alternatively rejected under 35 U.S.C. 102(a)(1) as being anticipated by Barrick.
Referring to claim 15, when the forwarding and allowing of the last paragraph are not performed (when the identifying does not occur), claim 15 is rejected for a subset of similar reasoning set forth in the rejection of claim 1. Note that Warnes and Katsura are not relied upon for this rejection.
Examiner Note
The examiner notes different grounds of rejection based on three different primary references. A dependent claim not rejected based on a given primary reference may be lacking a rejection only because the claim was already rejected based on another primary reference, and not necessarily because the claim is allowable over the given reference. Should applicant amend to overcome a primary reference (in a manner other than simply writing a dependent claim into independent form), the examiner may introduce a new dependent claim rejection with respect to another primary reference at that time, if possible. Any such new dependent claim rejection will be necessitated by applicant's amendment to overcome another primary reference. The examiner is not required to make all possible rejections at this time, but has done so only to expedite prosecution.
Response to Arguments
On page 8 of applicant’s response, applicant argues that the temporary storage cannot be interpreted as part of the execution unit in each reference because the temporary storage in the references allow the execution unit to continue without the result being lost.
This argument is not persuasive because the result in each of the references is still lost, i.e., never recorded in the register file, since a subsequent instruction is to overwrite the result. Applicant appears to simply be claiming in a different way what is already in the last paragraph of claim 1, for instance, i.e., that a result is overwritten by a subsequent instruction that uses and overwrites the result. This causes the result to be lost in response to a subsequent operation being performed. Since each reference applied in a rejection above similarly loses a result because a subsequent instruction uses and overwrites that result, the claims are still not distinguished from the prior art.
On pages 8-9 of the response, applicant argues that because the results are temporarily stored, they are not lost.
The examiner asserts that this is too narrow of an interpretation of “lost”. To the examiner, if a result is overwritten before it ever even makes it to its final destination, the result is lost. Stalling writing of the result to its final destination allows the result to be lost/removed from the system by performing a subsequent instruction.
On pages 10-11 of the response, applicant argues Official Notice of a matrix processor and vector processor because they vary significantly in the art and it is impossible to ascertain whether any such processor would have been obvious to combine with the other art.
This is not persuasive for reasons previously set forth. In addition, applicant may see U.S. Patent No. 6,366,937, as an example of a general purpose processor (FIG.1, 10) that additionally includes a special execution unit (FIG.1, 14) to multiply a matrix with a vector (FIG.2). Inclusion of this unit makes a general-purpose processor a matrix/vector processor that can more efficiently process matrix/vector operations such Fast Fourier Transform (abstract).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183
Prosecution Insights