DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to RCE filed on October 21, 2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, 6-9 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over by Kamijo (US 2014/0035124) in view of Shiraishi et al. (JP 2017017145 A, hereinafter Shiraishi).
Regarding claim 1, Kamijo discloses for a semiconductor device comprising that
a semiconductor layer (semiconductor substrate 12, Fig. 1) having an element region (active region 20, Fig. 1) where a semiconductor element is provided and a termination region (peripheral voltage-resistant region 50, Fig. 1) surrounding the element region (20, Fig. 1);
a conductive film (emitter electrode 22, Fig. 1) provided on the element region (20, Fig. 1) and the termination region (50, Fig. 1), because the emitter electrode 22 by Kamijo spans both the active region and the peripheral voltage-resistant region (Fig. 1), the conductive film (22, Fig. 1) having a bottom surface (bottom surface of 22, Fig. 1) facing the semiconductor layer (12, Fig. 1) and a top surface that is opposite to the bottom surface (top surface of 22, Fig. 1);
a first insulating film (polymer layer 80, Fig. 1) provided on the top surface of the conductive film (top surface of 22, Fig. 1) on the termination region (50, Fig. 1) and on a portion of the element region (20, Fig. 1) adjacent to the termination region, because Applicants do not specifically claim what the first insulating film is made of, the polymer layer 80 by Kamijo is electrically insulating film and disposed directly on a top surface of the emitter electrode 22 (Fig. 1) on both the active region and the peripheral voltage-resistant region (Fig. 1, [0043]); and
a second insulating film (nitride film 76, Fig. 1) provided on the first insulating film (80, Fig. 1), because the nitride film 76 by Kamijo is disposed on a bottom surface of the polymer layer 80, which corresponds to the first insulating film in the claimed invention, and
having a resistivity lower than a resistivity of the first insulating film and higher than a resistivity of the conductive film, because “the nitride film 76 may be a semiconductive silicon nitride film so-called SInSin film)” (emphasis added, [0041]), and Applicants originally disclosed that “an SInSiN film (referred to herein as a second insulating film) 6” (page 4 of current application), which is the same material used by Kamijo, and the polymer layer 80 by Kamijo is formed of a polyamide ([0043]), which is electrically insulating polymer, therefore, a resistivity of the nitride film 76 (SInSin) would be lower than a resistivity of the polymer layer 80 (polyamide) and higher than a resistivity of the emitter electrode 22 (conductive metal).
Kamijo does not explicitly disclose that a second insulating film provided on a top surface of the first insulating film.
However, Shiraishi discloses for a semiconductor device, such as IGBT ([0002]) in which the device 300 (Fig. 8) includes a source electrode 31 and an EQPR electrode 33 disposed in the first region R1 and the second region R2, respectively (Fig. 8). The source electrode 31 or EQPR electrode 33 correspond to the conductive film in the claimed invention, and the second region R2 corresponds to the termination region in the claimed invention. Shiraishi further discloses that the insulating layer 42 is disposed on a top surface of the source and EQPR electrodes 31/33 (Fig. 8), and thus corresponds to the first insulating film in the claimed invention. Shiraishi further discloses that the semi-insulating layer 41 is disposed on a top surface of the insulating layer 42 (Fig. 8), and therefore corresponds to the second insulating layer in the claimed invention (Fig. 8). Shiraishi further discloses that “the semi-insulating layer 41 includes silicon nitride” ([0021], see attached machine-translated copy), “the electrical resistance of the insulating layer 42 is higher than the electrical resistance of the semi-insulating layer 41” ([0024]), indicating that the semi-insulating layer 41 by Shiraishi has a lower resistivity than the insulating layer 42, which corresponds to the relative resistivity relationship recited in claim 1. Accordingly, Shiraishi discloses a structural configuration in which a semi-insulating silicon nitride layer is disposed on a top surface of an insulating layer formed on a conductive electrode.
Since both Kamijo and Shiraishi teach a semiconductor power device, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor power device of Kamijo to provide the semi-insulating layer on a top surface of the insulating layer, as disclosed by Shiraishi, rather than on a bottom surface as disclosed by Kamijo, as a matter of design choice to optimize the device performance and such a modification represents the predictable use of known insulating and semi-insulating silicon nitride layer arrangements to achieve improved performance.
Regarding claim 3, Kamijo further discloses that a third insulating film (polyimide film 70, Fig. 1) provided on the second insulating film (76, Fig. 1) except for an edge of the second insulating film on a side closer to the element region (side closer to region 20, Fig. 1), because Applicants do not specifically claim the geometrical orientation of a third insulating film with respect to a second insulating film, the polyimide film 70 by Kamijo is disposed on a bottom surface of the nitride film 76, which corresponds to the second insulating film in the claimed invention, therefore, the polyimide film 70 can correspond to the third insulating layer in the claimed invention; except for a part of the second insulating film on a side closer to the element region (side closer to region 20, Fig. 1) , because the polyimide film 70 is not disposed a part of the nitride film 76 closer to the region 20 (Fig. 1),
wherein a side wall of the second insulating film on the side closer to the element region (left side wall of 76, Fig. 1) is in contact with the conductive film (22, Fig. 1).
Regarding claim 4, Kamijo further discloses that the conductive film (22, Fig. 1) includes a first electrode (a left portion of emitter electrode 22, Fig. 1) provided on the element region (20, Fig. 1).
Regarding claim 6. Kamijo further discloses that the conductive film further includes an interconnection part (electrode 54 or 64, Fig. 1) that is provided on the termination region (50, Fig. 1), electrically isolated from the first electrode (a left portion of 22, Fig. 1), and is electrically connected to a second electrode (another portion of the emitter electrode 22, Fig. 1) provided in the element region, because the electrode 54 in the region 50 is in contact with the p+ guard ring region which is in contact with a portion of the emitter electrode 22, therefore, the electrode 54 is electrically connected to a portion of the emitter electrode 22 through P+ doped guard ring region (Fig. 1).
Regarding claim 7, Kamijo further discloses that the first insulating film (80, Fig. 1) is provided on the first electrode (22, Fig. 1), the interconnection part (54 or 64, Fig. 1), and the semiconductor layer (12, Fig. 1) between the first electrode (22, Fig. 1) and the interconnection part (54 or 64, Fig. 1), because the polymer layer 80 is formed on a top surface of the emitter electrode 22, on a top surface of the electrodes 54 or 64, and on a top surface of the semiconductor substrate 12, which correspond to the first electrode, the interconnection part, and the semiconductor layer in the claimed invention, respectively, and a portion of the polymer 80 is formed between the emitter electrode 22 and the electrode 54 (see attached Fig. 1 below). Examiner notes that Fig. 10 of the present application shows a portion of the first insulating film 5 is provided between the first electrode 4 and the interconnection part 42, rather than an entirety of the first insulating film 5.
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Regarding claim 8, Kamijo further discloses that the second insulating film (76, Fig. 1) is a semi-insulating silicon nitride film, because “the nitride film 76 may be a semiconductive silicon nitride film so-called SInSin film)” (emphasis added, [0041]).
Regarding claim 9, Kamijo further discloses for a semiconductor device comprising that
a semiconductor layer (12, Fig. 1) having an element region (20, Fig. 1) where a semiconductor element is provided and a termination region (50, Fig. 1) surrounding the element region (20, Fig. 1);
a conductive film (22, Fig. 1) provided on the element region (20, Fig. 1) and the termination region (50, Fig. 1), the conductive film having a bottom surface (bottom surface of 22, Fig. 1) facing the semiconductor layer (12, Fig. 1) and a top surface (top surface of 22, Fig. 1) that is opposite to the bottom surface;
a first insulating film (80, Fig. 1) provided on the top surface of the conductive film (22, Fig. 1) on the termination region (50, Fig. 1) and on a portion of the element region (a portion of 20, Fig. 1) adjacent to the termination region (50, Fig. 1), because Applicants do not specifically claim what the first insulating film is made of, the polymer layer 80 by Kamijo is electrically insulating film and disposed directly on a top surface of the emitter electrode 22 (Fig. 1) on both the active region and the peripheral voltage-resistant region (Fig. 1, [0043]);
a second insulating film (76, Fig. 1), which is in direct contact with the conductive film (22, Fig. 1), because a far-left side of the nitride film 76 by Kamijo is in direct contact with the emitter electrode 22 (Fig. 1),
provided on the first insulating film (80, Fig. 1), because the nitride film 76 by Kamijo is disposed on a bottom surface of the polymer layer 80, which corresponds to the first insulating film in the claimed invention, and
having a resistivity lower than a resistivity of the first insulating film and higher than a resistivity of the conductive film, because “the nitride film 76 may be a semiconductive silicon nitride film so-called SInSin film)” (emphasis added, [0041]), and Applicants originally disclosed that “an SInSiN film (referred to herein as a second insulating film) 6” (page 4 of current application), which is the same material used by Kamijo, and the polymer layer 80 by Kamijo is formed of a polyamide ([0043]), which is electrically insulating polymer, therefore, a resistivity of the nitride film 76 (SInSin) would be lower than a resistivity of the polymer layer 80 (polyamide) and higher than a resistivity of the emitter electrode 22 (conductive metal); and
a third insulating film (resin layer 82, Fig. 1) provided on the second insulating film (76, Fig. 1) and having a resistivity higher than the resistivity of the second insulating film, because a typical synthetic resin is electrically insulating, therefore, it is inherent that resin layer 82 has a higher resistivity than semiconductive silicon nitride film 76.
Kamijo does not explicitly disclose that a second insulating film provided on a top surface of the first insulating film.
However, Shiraishi discloses for a semiconductor device, such as IGBT ([0002]) in which the device 300 (Fig. 8) includes a source electrode 31 and an EQPR electrode 33 disposed in the first region R1 and the second region R2, respectively (Fig. 8). The source electrode 31 and EQPR electrode 33 correspond to the conductive film in the claimed invention, and the second region R2 corresponds to the termination region in the claimed invention. Shiraishi further discloses that the insulating layer 42 is disposed on a top surface of the source and EQPR electrodes 31/33 (Fig. 8), and thus corresponds to the first insulating film in the claimed invention. Shiraishi further discloses that the semi-insulating layer 41 is disposed on a top surface of the insulating layer 42 (Fig. 8), and therefore corresponds to the second insulating layer in the claimed invention (Fig. 8). Shiraishi further discloses that “the semi-insulating layer 41 includes silicon nitride” ([0021], see attached machine-translated copy), “the electrical resistance of the insulating layer 42 is higher than the electrical resistance of the semi-insulating layer 41” ([0024]), indicating that the semi-insulating layer 41 by Shiraishi has a lower resistivity than the insulating layer 42, which corresponds to the relative resistivity relationship recited in claim 9. Accordingly, Shiraishi discloses a structural configuration in which a semi-insulating silicon nitride layer is disposed on a top surface of an insulating layer formed on a conductive electrode.
Since both Kamijo and Shiraishi teach a semiconductor power device, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor power device of Kamijo to provide the semi-insulating layer on a top surface of the insulating layer, as disclosed by Shiraishi, rather than on a bottom surface as disclosed by Kamijo, as a matter of design choice to optimize the device performance and such a modification represents the predictable use of known insulating and semi-insulating silicon nitride layer arrangements to achieve improved performance
Regarding claim 15, Kamijo further discloses that the semiconductor element is an insulated gate bipolar transistor, because “an IGBT (Insulated Gate Bipolar Transistor) is formed in the active region 20” ([0034]).
Claims 2, 11-14 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over by Kamijo (US 2014/0035124) in view of Shiraishi et al. (JP 2017017145 A, hereinafter Shiraishi) as applied to claim 1 and 9 above, and further in view of Narita (JP 2018120930 A). The teachings of Kamijo in view of Shiraishi are discussed above.
Regarding claim 2, Kamijo further discloses for the semiconductor device according to claim 1 that a third insulating film (polyimide film 70, Fig. 1) provided on the second insulating film (nitride film 76, Fig. 1), because Applicants do not specifically claim the geometrical orientation of a third insulating film with respect to a second insulating film, the polyimide film 70 by Kamijo is disposed on a bottom surface of the nitride film 76, which corresponds to the second insulating film in the claimed invention, therefore, the polyimide film 70 can correspond to the third insulating layer in the claimed invention; except for a part of the second insulating film on a side closer to the element region (side closer to region 20, Fig. 1) , because the polyimide film 70 is not disposed a part of the nitride film 76 closer to the region 20 (Fig. 1).
Kamijo in view of Shiraishi differs from the claimed invention by not showing that a side wall of the second insulating film on the side closer to the element region and an upper surface of the part of the second insulating film are in contact with the conductive film.
However, Narita discloses for an insulated gate bipolar transistor (IGBT) that the device includes the element region 11 and the peripheral region 15 (Figs. 3-4), and the interlayer protective film 60 is disposed on a top surface of the AlSi layer 51 of the upper main electrode 50, which corresponds to the conductive film in the claimed invention, and therefore, the interlayer protective film 60 can correspond to the first insulating film in the claimed invention and the semi-insulating film 71 can correspond to the second insulating film in the claimed invention; as shown in the attached Fig. 4 of Narita below, a side wall of the semi-insulating film 71 on the side closer to the element region 11 and an upper surface of the part of the semi-insulating film 71 by Narita are in contact with the AlSi layer 51, i.e., a portion of the upper main electrode 50 (conductive film in the claimed invention), therefore, one of ordinary skill in the art would modify a semiconductive silicon nitride layer of Kamijo with the geometrical relationship of the semi-insulating film by Narita.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a semi-conductive or semi-insulating silicon nitride layer can be in contact with surfaces of an emitter electrode including side wall and top/bottom surfaces, as disclosed by Narita, in order to prevent possible short-circuit damage in an electrode and an interconnection structure.
Regarding claim 11, Kamijo in view of Shiraishi differs from the claimed invention by not showing that the second insulating film is in direct contact with the conductive film at an edge of the second insulating film that is farthest from the termination region.
However, Narita further discloses that the second insulating film (71, Fig. 4) is in direct contact with the conductive film (51 of 50, Fig. 4) at an edge of the second insulating film (right edge of 71, Fig. 4) that is farthest from the termination region (farthest from the region 15, Fig. 4).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a semi-conductive or semi-insulating silicon nitride layer can be in contact with an emitter electrode at an edge of the semi-conductive or semi-insulating silicon nitride layer, as disclosed by Narita, in order to prevent possible short-circuit damage in an electrode and an interconnection structure.
Regarding claim 12, Narita further discloses that the edge of the second insulating film (right edge of 71, Fig. 4) that is in direct contact with the conductive film (51 of 50, Fig. 4) is between the first insulating layer (66, Fig. 4) and the third insulating layer (60, Fig. 4).
Regarding claim 13, Kamijo further discloses that the third insulating film (82, Fig. 1) includes first and second portions, because the Merriam-Webster dictionary defines a word “portion” as “an often limited part of a whole”, and therefore, arbitrary portion and another arbitrary portion of the resin layer 82 can be selected as a first and a second portion as shown in the attached Fig. 1 of Kamijo below, and the second insulating film (76, Fig. 1) is in further direct contact with the conductive film between the first and second portions of the third insulating film, because a far-left sidewall of the nitride layer 76 is in direct contact with the emitter 22 between the first and the second portions as shown in the attached Fig. 1 below.
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Regarding claim 14, Narita further discloses that a side of the edge of the second insulating film (far right side of 71, Fig. 4) and an upper surface of the edge of the second insulating film (upper surface of a far-right side of 71, Fig. 4) are in direct contact with the conductive film (51 of 50, Fig. 4).
Regarding claim 21, Kamijo further discloses that a third insulating film (70, Fig. 1) provided on the second insulating film (76, Fig. 1) except for a part of the second insulating film on a side closer to the element region (side closer to region 20, Fig. 1) , because the polyimide film 70 is not disposed a part of the nitride film 76 closer to the region 20 (Fig. 1), and the third insulating film (70, Fig. 1) is provided between a side wall of the second insulating film on the side closer to the element region (left side wall of 76, Fig. 1) and the upper surface (upper surface of 76, Fig. 1), because a portion of the polyimide film 70 closer to the element region 20 is disposed between a left side wall of the nitride film 76 and a part of the upper surface of the nitride film 76 (Fig. 1).
Kamijo in view of Shiraishi differs from the claimed invention by not showing that an upper surface of the part of the second insulating film are in contact with the conductive film.
However, as shown in the attached Fig. 4 of Narita above, a side wall of the semi-insulating film 71 on the side closer to the element region 11 and an upper surface of the part of the semi-insulating film 71 by Narita are in contact with the AlSi layer 51, i.e., a portion of the upper main electrode 50 (conductive film in the claimed invention), therefore, one of ordinary skill in the art would modify a semiconductive silicon nitride layer of Kamijo with the geometrical relationship of the semi-insulating film by Narita.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a semi-conductive or semi-insulating silicon nitride layer can be in contact with surfaces of an emitter electrode including side wall and top/bottom surfaces, as disclosed by Narita, in order to prevent possible short-circuit damage in an electrode and an interconnection structure.
Regarding claim 22, Kamijo further discloses that the third insulating film (70, Fig. 1) is provided on the second insulating film (76, Fig. 1) between the side wall and the upper surface, because a portion of the polyimide film 70 closer to the element region 20 is disposed between a left side wall of the nitride film 76 and a part of the upper surface of the nitride film 76 (Fig. 1).
Claims 5, 10 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over by Kamijo (US 2014/0035124) in view of Shiraishi et al. (JP 2017017145 A, hereinafter Shiraishi) as applied to claim 1 and 9 above, and further in view of Uemura (US 2012/0068310). The teachings of Kamijo in view of Shiraishi are discussed above.
Regarding claim 5, Kamijo further discloses that the second insulating film (76, Fig. 1) is provided on the first insulating film (80, Fig. 1) and on the semiconductor layer (12, Fig. 1).
Kamijo in view of Shiraishi differs from the claimed invention by not showing that the second insulating film is in contact with the semiconductor layer at positions farther from the element region than the first insulating film.
However, Uemura disclose for an IGBT device that the oxide film 18 and the interlayer insulation film 19 is disposed on the drift layer 11, which corresponds to the semiconductor layer in the claimed invention, and disposed on a top surface of the emitter region 15, which corresponds to the conductive film in the claimed invention, therefore, a composite insulating film of the oxide film 18 and the interlayer insulation film 19 can correspond to the first insulating film in the claimed invention, and the overcoat film 35 made of sin-SiN (semi-insulating Silicon Nitride, [0034]) is disposed on the composite film of 18/19, and the overcoat film 35 is in contact with the drift layer 11 at a far right side of Fig. 1 of Uemura, which corresponds to a position farther from the cell region (i.e., element region in the claimed invention) than the composite layer of 18/19 (Fig. 1).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a semi-insulating film of a semiconductor power device (or IGBT) can be in contact with semiconductor layers, as disclosed by Uemura, in order to prevent possible short-circuits damage in an electrode and an interconnection, thereby improving the overall performance of a semiconductor power device.
Regarding claim 10, Kamijo in view of Shiraishi differs from the claimed invention by not showing that the second insulating film is in direct contact with the semiconductor layer in the termination region and not in direct contact with the semiconductor layer in the element region.
However, Uemura further discloses that the second insulating film (35, Fig. 1) is in direct contact with the semiconductor layer (11, Fig. 1) in the termination region (far right side of the guard ring region, Fig. 1) and not in direct contact with the semiconductor layer (11, Fig. 1) in the element region (cell region, Fig. 1), because the overcoat film 35 is not in contact with the drift layer 11 in the cell region, which corresponds to the element region in the claimed invention.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a semi-insulating film of a semiconductor power device (or IGBT) can be direct contact with the semiconductor layer in the termination region, while it is not in direct contact with the semiconductor layer in the element region, as disclosed by Uemura, in order to prevent possible short-circuits damage in an electrode and an interconnection, thereby improving the overall performance of a semiconductor power device.
Regarding claim 16, Kamijo in view of Shiraishi and further in view of Uemura do not explicitly disclose that the semiconductor element is a fast recovery diode.
However, Uemura further disclose that “in a sixth preferred embodiment, the present invention is applied to a PiN diode” ([0061]) and one of ordinary skill in the art would acknowledge that IGBT and a fast recovery diode are often used together in power circuits to optimize performance, reduce switching losses, and improve reliability, as well known in the art, therefore, one would recognize that the semiconductor element would include a fast recovery diode in the IGBT device by Kamijo in view of Shiraishi and Uemura.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/WOO K LEE/Examiner, Art Unit 2815