Prosecution Insights
Last updated: October 02, 2026
Application No. 17/901,606

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Final Rejection §103
Filed
Sep 01, 2022
Priority
Feb 25, 2022 — JP 2022-028571
Examiner
WEGNER, AARON MICHAEL
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
KIOXIA Corporation
OA Round
4 (Final)
74%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
70%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allowance Rate
28 granted / 38 resolved
+5.7% vs TC avg
Minimal -4% lift
Without
With
+-3.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
41 currently pending
Career history
95
Total Applications
across all art units

Statute-Specific Performance

§103
59.8%
+19.8% vs TC avg
§102
20.7%
-19.3% vs TC avg
§112
16.3%
-23.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 38 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 1-20 are pending in this application. Applicant elected without traverse Invention I, Species A (claims 1-4 and since added claims 19-20) in the reply filed on April 9, 2025. Claims 5-18 were withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention and/or species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on April 9, 2025. The Examiner notes that claims 1-4 and 19-20 are examined and claims 5-18 are withdrawn. Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. JP2022-028571, filed on February 25, 2022. Response to Amendment This Office Action is in response to Applicant’s Amendment filed June 30, 2026. Claim 1 is amended. Claims 5-18 remain withdrawn. The Examiner notes that claims 1-4 and 19-20 are examined. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-4 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2019/0164989 A1) in view of Son (US 2009/0242966 A1). With respect to claim 1, Lee teaches in Fig. 20: A semiconductor device (device of Fig. 20) comprising: a stack including a plurality of electrode films (conductive pattern 150a of gate structures 156) stacked in a first direction (first direction) so as to be separated from each other (separated by insulation patterns 110a); a column portion (channel structure 134) extending in the stack in the first direction, the column portion (134) including a semiconductor layer (channel pattern 128) and having memory cells at respective intersections between the semiconductor layer (128) and the electrode films (156); a dividing portion (column including common source line 162 and spacers 160) extending in the stack in the first direction (first direction, see Fig. 20) and a second direction (second direction, see Fig. 2A) crossing the first direction, the dividing portion dividing the electrode films in a third direction (third direction, see Fig. 2A and 20) crossing the first direction and the second direction, and the dividing portion including an insulator (insulation spacer 160); and a first film (conductive pattern 154a) provided such that an entirety of the first film is interposed between the insulator (160) and an end-most surface (see annotated Fig. 20 below) in the third direction of each of the electrode films (150a), the first film (154a) directly contacting the insulator (160) wherein the insulator (160) protrudes towards the column portion (134) along the third direction (third direction), and wherein the first film (154a) protrudes from the insulator (160) towards the column portion (134) along the third direction (third direction). PNG media_image1.png 291 625 media_image1.png Greyscale Lee fails to teach: and containing a first metal and silicon, Son teaches in Fig. 33: and a first film (metal silicide pattern 162) provided between the insulator (silicon oxide layer pattern 134) and an end surface in the third direction of each of the electrode films (control gate pattern 131a) the first film (162) directly contacting the insulator (134) and containing a first metal and silicon (para 237 “The metal silicide pattern 162 may include cobalt silicide, nickel silicide, tungsten silicide, palladium silicide, etc. according to the material of the metal layer 160 that is deposited by the previous process.”), Lee discloses the claimed invention except for the first film being a metal silicide. Son teaches that it is known to make a metal silicide layer between a insulating column and a gate electrode as set forth in para. 237 of Son. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to make the first film from metal silicide, as taught by Son order to increase the operating speed of the non-volatile memory device (para. 221). See MPEP 2144. With respect to claim 2, Lee further teaches: wherein the first film (154a) is provided on an opposed surface of the electrode film (150a) which is opposed to the dividing portion (160 and 162). With respect to claim 3, Lee further teaches: wherein the first film (154a) covers a side surface of the electrode film (150a) on a side of the dividing portion (160 and 162). With respect to claim 4, Son further teaches: wherein any of molybdenum silicide, tungsten silicide, titanium silicide, ruthenium silicide, cobalt silicide, and nickel silicide is used for the first film (para 237 “The metal silicide pattern 162 may include cobalt silicide, nickel silicide, tungsten silicide, palladium silicide, etc. according to the material of the metal layer 160 that is deposited by the previous process.”) It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Lee in view of Son as explained above. With respect to claim 19, Lee further teaches: wherein a protruding portion of the first film (154a) is curved (see Fig. 20). With respect to claim 20, Lee further teaches: wherein a protruding portion of the insulator (160) is curved (see Fig. 20). Response to Arguments Applicant's arguments filed June 30, 2026 have been fully considered but they are not persuasive. Applicant states that the amended limitation of claim 1 overcomes the prior art of record, however the Examiner determined that the prior art still reads on the newly amended limitations, as explained above. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /A.M.W./ Examiner, Art Unit 2897 /JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Show 1 earlier event
Apr 22, 2025
Non-Final Rejection mailed — §103
Jul 22, 2025
Response Filed
Oct 07, 2025
Final Rejection mailed — §103
Jan 07, 2026
Request for Continued Examination
Jan 23, 2026
Response after Non-Final Action
Mar 30, 2026
Non-Final Rejection mailed — §103
Jun 30, 2026
Response Filed
Aug 24, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
74%
Grant Probability
70%
With Interview (-3.6%)
3y 6m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 38 resolved cases by this examiner. Grant probability derived from career allowance rate.

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