Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of Claims
Examiner notes that in the instant application:
-Claims 1-8 and 16-20 are pending.
-Claims 9-15 are cancelled.
-Claims 1, 3, and 16 are Amended.
-Claims 8 and 19-20 are withdrawn.
Priority
Examiner noted in the previous Office Action, dated August 19, 2025, hereinafter Office Action, that in order to effectively benefit from the foreign priority date based on the application filed in Japan on March 23, 2022, an English translation of the certified copy (of the foreign application as filed) filed together with a statement that the translation of the certified copy is accurate must be presented. The Applicant has not included these documents in the instant application. Therefore, the right to foreign priority under 35 U.S.C. 119 (a)-(d) is not considered perfected.
Title
Acknowledgement is made of Applicant’s replacement of the title of the invention to in the Specification amendment on November 11, 2025. Upon review, Examiner finds the new title does narrow down the focus a bit, but doesn’t quite convey the main purpose (the inventive concept) of the invention to which the claims are directed. In particular, the Specification states that the semiconductor disclosed is a MOSFET with increased breakdown voltage, which is not conveyed by the amended title and seems to the Examiner important to state. The Examiner suggests combining the current title with the previous suggestion for a clearer title, as stated in the maintained objection below.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested:
--A MOSFET With Increased Breakdown Voltage Including A Termination Region With Vertically Separated Upper And Lower Impurity Regions Of Different Concentrations--
Response to Arguments
Applicant's amendments and arguments filed November 19, 2025 have been fully considered but they are not found to be persuasive.
In regards to the amendments to Claims 1 and 16, Applicant argues that the amended limitations, providing for the separation of the fifth and sixth semiconductor regions in a first direction, are not taught by Hoshi (U.S. Pub. 2022/0077312), hereinafter Hoshi. Applicant further states that in the Office Action, Examiner supposedly identified the fifth semiconductor regions simply as the p+-type region (21) of Hoshi. Examiner finds neither of these assertions to be true. In the Office Action, the Examiner identified the fifth semiconductor regions as “specifically the lower portions of ‘p+-type region’ (21) which are below (in the Z-direction) of the element (33a)” (pg. 5), which, notably, is indeed separated from the plurality of sixth semiconductor regions, which the Examiner simply identified as the whole of p-type region (22) of Hoshi. Moreso, Examiner notes that “separated” may come under a broad reasonable interpretation as simply meaning not overlapping, (Merriam-Webster, transitive verb, 1b: to make a distinction between).
As it relates to the arguments directed to the additional amendments to Claims 3 and 16, under this understanding of the fifth and sixth semiconductor regions in Hoshi, we find that the identified seventh semiconductor region of the Office Action (p+-type regions (62) including (62a)) are located between the fifth and sixth semiconductor regions in the first direction, vertically.
In regards to this interpretation of semiconductor regions of Hoshi, Examiner further explained his understanding in the rejection of Claim 3 of the Office Action (pg. 6) that, absent any limiting definition, ‘region’ has a broad reasonable interpretation that does not require the full structural element to be included. Thus indeed Hoshi is found to anticipate the amended limitations.
The rejections have been updated to address the newly amended limitations.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 and 16-18 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Hoshi (U.S. Pub. 2022/0077312), hereinafter Hoshi..
Regarding Claim 1, Hoshi teaches a semiconductor device (‘vertical MOSFET’ (30); Fig. 2, Paragraph [0051]) comprising:
-a first electrode ((52); Fig. 2, Paragraph [0100]);
-a first semiconductor region of a first conductivity type (‘n--type drift region’ (32); Fig. 2, Paragraph [0052]) that is provided on the first electrode (51) in a first direction (Z-direction; Fig. 2) and includes a first region (‘active region’ (1) part of (32); Fig. 2, Paragraph [0051]) and a second region (consisting of ‘edge termination region’ (2) and ‘intermediate region’ (3) parts of (32); Fig. 2, Paragraphs [0051] and [0052]) provided around the first region (1);
-a second semiconductor region of a second conductivity type (‘p-type base region’ (34) consisting of (34a) and (34b); Fig. 2, Paragraph [0055])) that is provided on the first region (1);
-a third semiconductor region of the first conductivity type (‘n+-type source region’ (35); Fig. 2, Paragraph [0055]) that is provided on a part of the second semiconductor region (34);
-a gate electrode ((39); Fig. 2, Paragraph [0055]) that faces the second semiconductor region (34) with a gate insulation layer ((38); Fig. 2, Paragraph [0055]) placed therebetween;
-a fourth semiconductor region of the second conductivity type (‘p+-type region (61); Fig. 2, Paragraph [0064]) that is provided between the first region (1) and the gate electrode (39);
-a plurality of fifth semiconductor regions of the second conductivity type (specifically the lower portions of ‘p+-type region’ (21) which are below (in the Z-direction) of the element (33a); Fig. 2, Paragraph [0087]) that are provided in the second region ((2) and (3)), each located around the fourth semiconductor region (61) in a first plane (X-Y plane of a first height; Figs. 1 and 2) perpendicular to the first direction (Z-direction), and separated from each other in a second direction (Y-direction; Fig. 2) that extends from the first region (1) to the second region ((2) and (3));
-a plurality of sixth semiconductor regions of the second conductivity type (‘p-type region’ (22); Fig. 2, Paragraph [0087]) that are provided in the second region ((2) and (3)), located around the second semiconductor region (34) along a second plane (X-Y plane of a second height; Figs. 1 and 2) perpendicular to the first direction (Z-direction), and separated from each other in the second direction (Y-direction), the plurality of sixth semiconductor regions (22) each having a concentration of impurities of the second conductivity type (p) which is lower (p < p+, see also Paragraph [0090]) than a concentration of impurities of the second conductivity type (p++) of each of the plurality of fifth semiconductor regions (lower portions (21)); and
-a second electrode (‘barrier metal’ (46); Fig. 2, Paragraph [0077]) that is provided on the second semiconductor region (34) and the third semiconductor region (35),
-wherein the plurality of fifth semiconductor regions (lower portions of (21)) is separated from the plurality of the sixth semiconductor regions (22) in the first direction (Z-direction), and a part of the first semiconductor region (e.g. the portion of (32) to the right of element (33a)) is disposed between the plurality of fifth semiconductor regions (lower portions of (21)) and the plurality of sixth semiconductor regions (22) in the first direction (Z-direction).
(Please see Response to Arguments above regarding both the Examiner’s understanding of “region” i.e., that absent any limiting definitions, ‘region’ has a broad reasonable interpretation that does not require the full structural element to be included. And “separated” as simply meaning distinguishable or not overlapping)
Regarding Claim 2, Hoshi teaches a semiconductor device (‘vertical MOSFET’ (30); Fig. 2, Paragraph [0051]) of Claim 1, wherein:
- the concentration of impurities of the second conductivity type (p) of each of the plurality of sixth semiconductor regions (22) is lower than a concentration of impurities of the second conductivity type (p) of the second semiconductor region ((34), specifically within the subset region (34b), which may be formed during the second step of the multistage deposition of epitaxial layer (73) (consisting of (73a) and (73b)) corresponding to a higher impurity concentration as with regions (36) and (23), see Paragraphs [0098] and [128]).
Regarding Claim 3, Hoshi teaches a semiconductor device (‘vertical MOSFET’ (30); Fig. 2, Paragraph [0051]) of Claim 2, further comprising:
a plurality of seventh semiconductor regions of the second conductivity type (‘p+-type regions (62) including (62a); Fig. 2, Paragraph [0069]) that are located around the gate electrode (39) in a third plane perpendicular (X-Y plane of a third height; Figs. 1 and 2) to the first direction (Z-direction), wherein the plurality of seventh semiconductor regions (62) are located in the second region ((2) and (3)) between the plurality of fifth semiconductor regions (lower portions of (21)) and the plurality of sixth semiconductor regions (22) in the first direction (Z-direction).
Regarding Claim 4, Hoshi teaches a semiconductor device (‘vertical MOSFET’ (30); Fig. 2, Paragraph [0051]) of Claim 3, wherein:
-a concentration of impurities of the second conductivity type (p+) of each of the plurality of seventh semiconductor regions (62) is lower than the concentration of impurities of the second conductivity type (p+) of each of the plurality of fifth semiconductor regions (lower portions of (21)) (Firstly, note Hoshi discloses both (61) and (62) as the same ‘high concentration’ regions, used to mitigate the electric field applied to the bottom of the gate trenches, Paragraph [0064]. Paragraph [0110] gives the impurity concentration of (61) as 3x1018/cm3, while Paragraph [0137] gives the impurity concentration of (21) as 5x1018/cm3, thus the limitation is taught) and higher than the concentration of impurities of the second conductivity type (p) of each of the plurality of sixth semiconductor regions (22) (p+ > p, see also Paragraphs [0110] and [0137], 3x1018/cm3 > 4x1017/cm3).
Regarding Claim 5, Hoshi teaches a semiconductor device (‘vertical MOSFET’ (30); Fig. 2, Paragraph [0051]) of Claim 4, wherein:
-the plurality of seventh semiconductor regions ((62) and (62a)) include a first continuous semiconductor region (62) in the third plane (X-Y plane of a third height; Figs. 1 and 2) around the gate electrode (39) and a second continuous semiconductor region (62a) in the third plane (X-Y plane of a third height; Figs. 1 and 2) around the first continuous semiconductor region ((62), see also Paragraphs [0069] and [0070]).
Regarding Claim 16, Hoshi teaches a semiconductor device (‘vertical MOSFET’ (30); Fig. 2, Paragraph [0051]) comprising:
-a first electrode ((52); Fig. 2, Paragraph [0100]);
-a first semiconductor region of a first conductivity type (‘n--type drift region’ (32); Fig. 2, Paragraph [0052]) that is provided on the first electrode (51) in a first direction (Z-direction; Fig. 2) and includes a first region (‘active region’ (1) part of (32); Fig. 2, Paragraph [0051]) and a second region (consisting of ‘edge termination region’ (2) and ‘intermediate region’ (3) parts of (32); Fig. 2, Paragraph [0051]) provided around the first region (1);
-a second semiconductor region of a second conductivity type (‘p-type base region’ (34) consisting of (34a) and (34b); Fig. 2, Paragraph [0055])) that is provided on the first region (1);
-a third semiconductor region of the first conductivity type (‘n+-type source region’ (35); Fig. 2, Paragraph [0055]) that is provided on a part of the second semiconductor region (34);
-a gate electrode ((39); Fig. 2, Paragraph [0055]) that faces the second semiconductor region (34) with a gate insulation layer ((38); Fig. 2, Paragraph [0055]) placed therebetween;
-a fourth semiconductor region of the second conductivity type (‘p+-type region (61); Fig. 2, Paragraph [0064]) that is provided between the first region (1) and the gate electrode (39);
-a fifth semiconductor region of the second conductivity type (specifically the lower portion of a ‘p+-type region’ (21), which is below (in the Z-direction) of the element (33a); Fig. 2, Paragraph [0087]) that is provided in the second region ((2) and (3)), and located around the fourth semiconductor region (61) in a first plane (X-Y plane of a first height; Figs. 1 and 2) perpendicular to the first direction (Z-direction);
-a sixth semiconductor region of the second conductivity type (a ‘p-type region’ (22); Fig. 2, Paragraph [0087]) that is provided in the second region ((2) and (3)), located around the second semiconductor region (34) in a second plane (X-Y plane of a second height; Figs. 1 and 2) perpendicular to the first direction (Z-direction);
- a plurality of seventh semiconductor regions of the second conductivity type (‘p+-type regions (62) including (62a); Fig. 2, Paragraph [0069]) that are located around the gate electrode (39) in a third plane that is perpendicular (X-Y plane of a third height; Figs. 1 and 2) to the first direction (Z-direction) and is between the first plane and the second plane in the first direction (as the first plane is located lower at a first height, whereas the second plane is located higher at a second height, it is understood the third height is between them in the Z-direction), separated from each other in a second direction (Y-direction; Fig. 2) that extends from the first region (1) to the second region ((2) and (3)), and located in the second region ((2) and (3)) between the fifth semiconductor region (lower portion of a (21)) and the sixth semiconductor region (leftmost (22)) in the first direction (Z-direction); and
-a second electrode (‘barrier metal’ (46); Fig. 2, Paragraph [0077]) that is provided on the second semiconductor region (34) and the third semiconductor region (35).
(Please see Response to Arguments above regarding both the Examiner’s understanding of “region” i.e., that absent any limiting definitions, ‘region’ has a broad reasonable interpretation that does not require the full structural element to be included. And “separated” as simply meaning distinguishable or not overlapping)
Regarding Claim 17, Hoshi teaches a semiconductor device (‘vertical MOSFET’ (30); Fig. 2, Paragraph [0051]) of Claim 16, wherein:
-the fifth semiconductor region (lower portions of (21)) includes a first part (e.g. the lower of the leftmost (21)) that is provided around the second semiconductor region (34) in the first plane (X-Y plane of a first height; Figs. 1 and 2), a second part (e.g. the lower of the second from the left (21) that is provided around the first part (lower leftmost (21)) in the first plane (X-Y plane of a first height; Figs. 1 and 2), and wherein the sixth semiconductor region (22) includes a first portion (e.g. the leftmost (22)) that is provided around the second semiconductor region (34) in the second plane (X-Y plane of a second height; Figs. 1 and 2), a second portion (e.g. the second from the left (22)) that is provided around the first portion (leftmost (22)) in the second plane (X-Y plane of a second height; Figs. 1 and 2), and a third portion (e.g. rightmost (22)) that is provided around the second portion (second from the left (22)) in the second plane (X-Y plane of a second height; Figs. 1 and 2).
Regarding Claim 18, Hoshi teaches a semiconductor device (‘vertical MOSFET’ (30); Fig. 2, Paragraph [0051]) of Claim 17, wherein:
-a spacing (distance in the Y-direction of Fig. 2) between the first portion (leftmost (22)) and the second portion (second from the left (22)) is less than a spacing between the second portion (second from the left (22)) and the third portion (rightmost (22)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7 is rejected under 35 U.S.C. 103 as being unpatentable over Hoshi in view of Chen et al. (U.S. Pub. 2015/0279931), hereinafter Chen.
Regarding Claim 7, Hoshi teaches the semiconductor device (‘vertical MOSFET’ (30); Fig. 2, Paragraph [0051]) of Claim 1 upon which it depends, and further that:
-the FLR regions (24) may be adjusted to establish a predetermined breakdown voltage of the edge termination region (2) (Paragraph [0086]).
Hoshi does not teach:
- a spacing between two adjacent sixth semiconductor regions in the second direction increases at positions that are farther from the first region.
Chen teaches a semiconductor device to be used for high-voltage application featuring a field limit ring (FLR), wherein:
- a spacing between two adjacent sixth semiconductor regions (ring layers (12a-12f); Fig. 2, Paragraph [0044]) in the second direction (towards the channel stopper region, nominally the Y-direction) increases at positions that are farther from the first region (Active Region).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Chen into the device of Hoshi such that a spacing between two adjacent sixth semiconductor regions in the second direction increases at positions that are farther from the first region. This would be due to the fact that doing so would improve turn-off breaking capability and widen allowable range of p-type doses (Chen, Paragraph [0008]).
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 6, the best prior art of record does not teach or fairly suggest, along with the other claimed features, which are necessary in informing the structure, a semiconductor device wherein:
- the plurality of seventh semiconductor regions include a first continuous semiconductor region in the third plane around the gate electrode and a plurality of disconnected semiconductor regions of the second conductivity type in the third plane around the first continuous semiconductor region.
Closest prior art references found during examination are listed below:
U.S. Pub. 2022/0077312 U.S. Pub. 2022/0344455 U.S. Pub. 2022/0216335
These references disclose similar semiconductor devices (MOSFETS) intended to carry high breakdown voltages. In the case of Hoshi (U.S. Pub. 2022/0077312), seventh semiconductor regions ((62) and (62a)) include a first continuous semiconductor region (62) in the third plane (X-Y plane of a third height; Figs. 1 and 2) around the gate electrode (39). However, Hoshi fails to teach “a plurality of disconnected semiconductor regions of the second conductivity type in the third plane around the first continuous semiconductor region.” In the case of Hoshi et al. (U.S. Pub. 2022/0344455), the disclosure contains a similar form as Hoshi and fails to teach the plurality of disconnected semiconductor regions as described. In the case of Okumura (U.S. Pub. 2022/0216335), the disclosure contains seventh semiconductor regions (3; Fig. 2) include a first continuous semiconductor region (e.g. the left (3)) in the third plane (X-Y plane of a given height; Fig. 2) around the gate electrode (12). As with Hoshi, the disclosure fails to teach the plurality of disconnected semiconductor regions as described.
In regards to the limitation, the Examiner notes that this feature is well described in the instant application in Pages [19] and [20] and Fig. 6B, and the inclusion of such a feature is not considered arbitrary or a simple choice of element shape.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.M./Examiner, Art Unit 2812 /DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812