DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (Claims 1-17) in the reply filed on 10/29/2025 is acknowledged.
Claims 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10/29/2025.
Examiner’s Note
The Examiner notes that copending Application No. 17950870 (used later as the reference application in the double patenting rejection) has been published as US 2024/0113114.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-10 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-6,9-11 and 17 of copending Application No. 17950870 hereinafter “’870 App” (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other.
Current App.
1. A method for fabricating semiconductor devices, comprising: forming a first stack over a substrate, the first stack including a plurality of first dielectric layers and a plurality of second dielectric layers alternately stacked on top of one another; replacing a first portion of the first stack with a second stack, the second stack including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked on top of one another; removing a second portion of the first stack to expose sidewalls of each of the plurality of second semiconductor layers, respectively; forming, through the removed second portion of the first stack, a pair of first epitaxial structures in contact with a lower one of the second semiconductor layers, respectively; and forming, through the removed second portion of the first stack, a pair of second epitaxial structures in contact with an upper one of the second semiconductor layers, respectively.
‘870 App
1. A method for fabricating semiconductor devices, comprising: forming a first stack over a substrate, the first stack including a plurality of first dielectric layers and a plurality of second dielectric layers alternately stacked on top of one another; replacing a first portion, a second portion, and a third portion of the first stack with a first dielectric structure, a second dielectric structure, and a third dielectric structure, respectively, wherein the first, second, and third dielectric structures each continuously extend through the first stack; replacing the first dielectric structure with a second stack, the second stack including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked on top of one another; removing a portion of the second dielectric structure; removing a portion of the third dielectric structure; exposing, through the removed portion of the second dielectric structure and the removed portion of the third dielectric structure, sidewalls of each of the plurality of second semiconductor layers, respectively; forming a pair of first epitaxial structures in contact with the exposed sidewalls of a lower one of the second semiconductor layers, respectively; and forming a pair of second epitaxial structures in contact with the exposed sidewalls of an upper one of the second semiconductor layers, respectively.
Claim 2 of the current application is anticipated by claim 2 of the ‘870 App.
Claim 3 of the current application is anticipated by claim 3 of the ‘870 App.
Claim 4 of the current application is anticipated by claim 9-11 of the ‘870 App.
Claim 5 of the current application is anticipated by claim 17 of the ‘870 App.
Claim 6 of the current application is anticipated by claim 4 of the ‘870 App.
Claim 7 of the current application is anticipated by claim 5 of the ‘870 App.
Claim 8 of the current application is anticipated by claim 6 of the ‘870 App.
Claim 9 of the current application is anticipated by claim 9 of the ‘870 App.
Claim 10 of the current application is anticipated by claim 9 of the ‘870 App.
Claims 11-15 and 17 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 4, 9-11, 15 and 16 of copending Application No. 17950870 hereinafter “’870 App” (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other.
Current App.
11. A method for fabricating semiconductor devices, comprising: forming a stack including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked on top of one another, wherein sidewalls of each of the first semiconductor layers are respectively covered by corresponding first dielectric layers, and sidewalls of each of the second semiconductor layers are respectively covered by corresponding second dielectric layers; exposing the sidewalls of each of the second semiconductor layers; forming a pair of first epitaxial structures in contact with the sidewalls of a lower one of the second semiconductor layers, respectively; and forming a pair of second epitaxial structures in contact with the sidewalls of an upper one of the second semiconductor layers, respectively.
‘870 App
1. A method for fabricating semiconductor devices, comprising: forming a first stack over a substrate, the first stack including a plurality of first dielectric layers and a plurality of second dielectric layers alternately stacked on top of one another; replacing a first portion, a second portion, and a third portion of the first stack with a first dielectric structure, a second dielectric structure, and a third dielectric structure, respectively, wherein the first, second, and third dielectric structures each continuously extend through the first stack; replacing the first dielectric structure with a second stack, the second stack including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked on top of one another; removing a portion of the second dielectric structure; removing a portion of the third dielectric structure; exposing, through the removed portion of the second dielectric structure and the removed portion of the third dielectric structure, sidewalls of each of the plurality of second semiconductor layers, respectively; forming a pair of first epitaxial structures in contact with the exposed sidewalls of a lower one of the second semiconductor layers, respectively; and forming a pair of second epitaxial structures in contact with the exposed sidewalls of an upper one of the second semiconductor layers, respectively.
Claim 12 of the current application is anticipated by claim 4 of the ‘870 App.
Claim 13 of the current application is anticipated by claim 2 of the ‘870 App.
Regarding claim 14, the ‘870 App does not explicitly teach “where the gate structure, the upper and lower second semiconductor layers, the pair of first epitaxial structures, and the pair of second epitaxial structures collectively operate as a single transistor”.
However, claim 2 of ‘870 App teaches where the pair of first epitaxial structures and the second epitaxial structures are concurrently formed, and wherein the pair of the first epitaxial structures and the pair of second epitaxial structures have a same conductive type.
Further, claim 14 of the current application does not add any additional structure beyond that of that taught by claims 11-13 (which is read upon by claims 12 and 4 of the ‘870 App as stated above), and merely recites a use of the structure claimed in previous claims 11-13.
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the gate structure, the upper and lower second semiconductor layers, the pair of first epitaxial structures, and the pair of second epitaxial structures collectively operate as a single transistor as recited in claim 14 in the current app because “If an examiner concludes that a functional limitation is an inherent characteristic of the prior art, then to establish a prima case of anticipation or obviousness, the examiner should explain that the prior art structure inherently possesses the functionally defined limitations of the claimed apparatus. In re Schreiber, 128 F.3d at 1478, 44 USPQ2d at 1432.” (MPEP 2114).
Claim 15 of the current application is anticipated by claim 9-11 of the ‘870 App.
Claim 17 of the current application is anticipated by claim 15 and 16 of the ‘870 App.
Claims 16 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 4, 9-11, 15 and 16 of copending Application No. 17950870 hereinafter “’870 App” (reference application) in view of Mehandru et al. (US 2018/0323195) hereinafter “Mehandru”. Although the claims at issue are not identical, they are not patentably distinct from each other.
Regarding claim 16, the ‘870 App does not explicitly teach “where the gate structure, the lower second semiconductor layer and the pair of first epitaxial structures collectively operate as a first transistor of an inverter, and the gate structure, the upper second semiconductor layer, and the pair of second epitaxial structures collectively operate as a second transistor of an inverter.
However, claim 11 of ‘870 App teaches where the first conductive type is opposite to the second conductive type.
Further, claim 16 of the current application does not add any additional structure beyond that of that taught by claims 11, 12 and 15 (which is read upon by claims 9-11 and 4 of the ‘870 App as stated above), and merely recites a use of the structure claimed in previous claims 11, 12 and 15.
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the pair of first epitaxial structures collectively operate as a first transistor of an inverter, and the gate structure, the upper second semiconductor layer, and the pair of second epitaxial structures collectively operate as a second transistor of an inverter as recited in claim 16 in the current app because “If an examiner concludes that a functional limitation is an inherent characteristic of the prior art, then to establish a prima case of anticipation or obviousness, the examiner should explain that the prior art structure inherently possesses the functionally defined limitations of the claimed apparatus. In re Schreiber, 128 F.3d at 1478, 44 USPQ2d at 1432.” (MPEP 2114).
Further, the ‘870 App does not explicitly teach where the first and second transistor are used in an inverter.
Mehandru teaches where in an inverter structure, a top transistor stack is of an opposite conductivity than that of a lower transistor stack (Paragraph 0127).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the first and second transistor used in an in inverter because transistors having opposite conductivity type are known to be used together in an inverter (Mehandru Paragraph 0127).
Alternately, Claims 11-15 and 17 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2, 4, 9-11, 15 and 16 of copending Application No. 17950870 hereinafter “’870 App” (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other.
Current App.
11. A method for fabricating semiconductor devices, comprising: forming a stack including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked on top of one another, wherein sidewalls of each of the first semiconductor layers are respectively covered by corresponding first dielectric layers, and sidewalls of each of the second semiconductor layers are respectively covered by corresponding second dielectric layers; exposing the sidewalls of each of the second semiconductor layers; forming a pair of first epitaxial structures in contact with the sidewalls of a lower one of the second semiconductor layers, respectively; and forming a pair of second epitaxial structures in contact with the sidewalls of an upper one of the second semiconductor layers, respectively.
‘870 App
9. A method for fabricating semiconductor devices, comprising: forming a first stack over a substrate, the first stack including a plurality of first dielectric layers and a plurality of second dielectric layers alternately stacked on top of one another; replacing a first portion, a second portion, a third portion, a fourth portion, a fifth portion, and a sixth portion of the first stack with a first dielectric structure, a second dielectric structure, a third dielectric structure, a fourth dielectric structure, a fifth dielectric structure, and a sixth dielectric structure, respectively, wherein the first to sixth dielectric structures each continuously extend through the first stack, the first dielectric structure is interposed between the second and third dielectric structures, and the fourth dielectric structure is interposed between the fifth and sixth dielectric structures; replacing the first dielectric structure with a second stack and replacing the fourth dielectric structure with a third stack, the second stack and third stack each including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked on top of one another; forming, through at least respectively removed portions of the second dielectric structure and the third dielectric structure, a plurality of pairs of first epitaxial structures in contact with sidewalls of the second semiconductor layers of the second stack, respectively; and forming, through at least respectively removed portions of the fifth dielectric structure and the sixth dielectric structure, a plurality of pairs of second epitaxial structures in contact with sidewalls of the second semiconductor layers of the third stack, respectively.
Claim 12 of the current application is anticipated by claim 4 of the ‘870 App.
Claim 13 of the current application is anticipated by claim 2 of the ‘870 App.
Regarding claim 14, the ‘870 App does not explicitly teach “where the gate structure, the upper and lower second semiconductor layers, the pair of first epitaxial structures, and the pair of second epitaxial structures collectively operate as a single transistor”.
However, claim 2 of ‘870 App teaches where the pair of first epitaxial structures and the second epitaxial structures are concurrently formed, and wherein the pair of the first epitaxial structures and the pair of second epitaxial structures have a same conductive type.
Further, claim 14 of the current application does not add any additional structure beyond that of that taught by claims 11-13 (which is read upon by claims 12 and 4 of the ‘870 App as stated above), and merely recites a use of the structure claimed in previous claims 11-13.
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the gate structure, the upper and lower second semiconductor layers, the pair of first epitaxial structures, and the pair of second epitaxial structures collectively operate as a single transistor as recited in claim 14 in the current app because “If an examiner concludes that a functional limitation is an inherent characteristic of the prior art, then to establish a prima case of anticipation or obviousness, the examiner should explain that the prior art structure inherently possesses the functionally defined limitations of the claimed apparatus. In re Schreiber, 128 F.3d at 1478, 44 USPQ2d at 1432.” (MPEP 2114).
Claim 15 of the current application is anticipated by claim 9-11 of the ‘870 App.
Claim 17 of the current application is anticipated by claim 15 and 16 of the ‘870 App.
Alternatively, Claims 16 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2, 4, 9-11, 15 and 16 of copending Application No. 17950870 hereinafter “’870 App” (reference application) in view of Mehandru et al. (US 2018/0323195) hereinafter “Mehandru”. Although the claims at issue are not identical, they are not patentably distinct from each other.
Regarding claim 16, the ‘870 App does not explicitly teach “where the gate structure, the lower second semiconductor layer and the pair of first epitaxial structures collectively operate as a first transistor of an inverter, and the gate structure, the upper second semiconductor layer, and the pair of second epitaxial structures collectively operate as a second transistor of an inverter.
However, claim 11 of ‘870 App teaches where the first conductive type is opposite to the second conductive type.
Further, claim 16 of the current application does not add any additional structure beyond that of that taught by claims 11, 12 and 15 (which is read upon by claims 9-11 and 4 of the ‘870 App as stated above), and merely recites a use of the structure claimed in previous claims 11, 12 and 15.
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the pair of first epitaxial structures collectively operate as a first transistor of an inverter, and the gate structure, the upper second semiconductor layer, and the pair of second epitaxial structures collectively operate as a second transistor of an inverter as recited in claim 16 in the current app because “If an examiner concludes that a functional limitation is an inherent characteristic of the prior art, then to establish a prima case of anticipation or obviousness, the examiner should explain that the prior art structure inherently possesses the functionally defined limitations of the claimed apparatus. In re Schreiber, 128 F.3d at 1478, 44 USPQ2d at 1432.” (MPEP 2114).
Further, the ‘870 App does not explicitly teach where the first and second transistor are used in an inverter.
Mehandru teaches where in an inverter structure, a top transistor stack is of an opposite conductivity than that of a lower transistor stack (Paragraph 0127).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the first and second transistor used in an in inverter because transistors having opposite conductivity type are known to be used together in an inverter (Mehandru Paragraph 0127).
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC K ASHBAHIAN whose telephone number is (571)270-5187. The examiner can normally be reached 8-5:30 PM.
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/ERIC K ASHBAHIAN/Primary Examiner, Art Unit 2891