Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
This office action is in response to applicant’s communication filed on 02/19/26. Claims 1-20 are pending in this application.
Claim Rejections Under 35 U.S.C. §103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, and 11-19 are rejected under 35 U.S.C. §103 as being unpatentable over Ma US 20200044059 A1) and further in view of Lee(US 20230380148 A1).
Regarding claim 1, Ma discloses a circuit comprising: a circuit structure configured to store charge in a charge-based storage element (see fig 3, para [0053] and fig 1a disclosing charge storage), wherein the charge-based storage element is disposed in a shallow-trench-isolation (STI) region of the circuit (see para [0053] disclosing STI).
However, Ma does not explicitly disclose that a capacitor is partially disposed in the STI. However, Lee is directed towards memory/capacitor arrangements and at least at fig 9, discloses a capacitor is partially disposed in the STI (see para [0025], and fig 9, disclosing capacitor OTP, disposed in STI 18). Ma and Lee are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Ma and Lee. Ma and Lee may be combined by forming the device of Ma in accordance with Lee, in order to achieve small device footprint.
Regarding claim 2, Ma and Lee disclose the circuit of claim 1, wherein the charge-base storage element comprises one or more capacitors (see charge storage), and wherein at least one capacitor of the one or more capacitors is disposed in at least one of a buried rail trench or at least one of a gate-cut and fin-cut region corresponding at least partially to the STI region (see figs 3-7 disclosing charge storage in trench, see para [0054] disclosing fin Stack).
Regarding claim 3, Ma and Lee disclose the circuit of claim 2, wherein the at least one capacitor is formed on a storage node of the circuit, wherein the storage node is positioned in one or both of the buried rail trench and the fin-cut region of the circuit (see para [0055] and figs 3-7, disclosing fin region).
Regarding claim 4, Ma and Lee disclose the circuit of claim 2, wherein the at least one capacitor is formed in the STI region and a silicon substrate region of the circuit(see figs 3-7 disclosing charge storage in trench, see para [0054] disclosing fin Stack, see para [0063] disclosing sti region).
Regarding claim 5, Ma and Lee disclose the circuit of claim 2, wherein the at least one capacitor is formed perpendicular to a transistor-gate layer configured to form respective gates of first transistor and second transistors(see figs 3-7 disclosing charge storage in trench, see para [0054] disclosing fin Stack, see fig 1, disclosing perpendicular orientation).
Regarding claim 6, Ma and Lee disclose the circuit of claim 2, wherein the at least one capacitor is formed parallel to a transistor- gate layer configured to form respective gates of first transistor and second transistors (see figs 3-7 disclosing gate over channel over charge storage in trench, see para [0054] disclosing fin Stack).
Regarding claim 7, Ma and Lee disclose the circuit of claim 1, wherein the circuit structure comprises a memory bitcell (see para [0090] disclosing memory bit cell).
Regarding claim 11, Ma and Lee disclose the circuit of claim 1, wherein the circuit structure is configured to store digital data in the charge-based storage element (see para [0090] disclosing storing bit data). Lee is directed towards memory/capacitor arrangements and at least at fig 9, discloses a capacitor is partially disposed in the STI (see para [0025], and fig 9, disclosing capacitor OTP, disposed in STI 18).
Regarding claim 12, Ma and Lee disclose the circuit of claim 1, wherein the charge-based storage element comprises: a first liner material; and a first metal layer disposed on the first liner material (see para [0092] disclosing fixed metal liners).
Regarding claim 13, Ma and Lee disclose a method comprising: providing a circuit structure disposed on a substrate and a shallow-trench-isolation (STI) region of a circuit (see para [0036] disclosing STI); forming an opening of the substrate and the STI region by removing a portion of the substrate and STI region (see para [0042] disclosing etching); placing a first liner material in the opening and on remaining portions of the substrate and the STI region (see 3-7); and depositing a first metal layer in the opening on the first liner material (see para [0042] disclosing metal in trench).
Regarding claim 14, Ma and Lee disclose the method of claim 13, wherein the substrate is coupled to ground, and wherein an input voltage is coupled to the circuit structure (see para [0050] disclosing active voltage), and wherein forming the opening comprises: removing a portion of a field effect transistor (see para [0092] disclosing FET and para [0069] disclosing removing fixed charge liner).
Regarding claim 15, Ma and Lee disclose the method of claim 13, further comprising: placing a second liner material in the opening and on the first metal layer (see para[0069]); depositing a second metal layer in the opening on the second liner material, wherein the input voltage is coupled to the first metal layer (see para [0069] and figs 3-7) disclosing two sides with metal liners.
Regarding claim 16, Ma and Lee disclose the method of claim 14, further comprising: enclosing the second metal layer within the second liner material (see figs 3-7 disclosing 110 enclosing130); and depositing the first metal layer on the second liner material, wherein the first metal layer is separated from the second metal layer (see 106 formed on titanium, see para [0036]).
Regarding claim 18, Ma and Lee disclose a method comprising: providing a memory cell structure disposed on a substrate and a shallow-trench-isolation (STI) region (see figs 3-7 disclosing STI regions); forming one or more charge-based storage elements in the substrate and the STI region to store data of the memory cell structure (see para ); and manufacturing, or causing to be manufactured, a memory device having the memory cell structure with the one or more charge-based storage element formed in the substrate and the STI region or fin-cut region (see fig 1 and para [0037] disclosing charge liners).
Regarding claim 19, Ma and Lee disclose the method of claim 18, wherein the one or more charge-based storage elements comprises one or more capacitors (see para [0037] disclosing charge liners).
Claims 8, 10 and 20 are rejected under 35 U.S.C. §103 as being unpatentable over Ma, Lee and further in view of Han (US 20150200005 A1).
Regarding claim 8, Ma and Lee disclose the circuit of claim 7, but does not disclose wherein the memory bitcell comprises an eDRAM gain-cell.
However, Han discloses a Gain cell bitline cell.
Ma, Lee and Han are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art a time prior to the effective filing date of the present application to combine Han with Ma and Lee. Han and Ma and Lee may be combined by forming the device of Han in a gain cell, as disclosed in Ma, see figs 21 and 22, and para [0136].
Regarding claim 9, Han, Lee and Ma disclose the circuit of claim 8, wherein the eDRAM gain cell comprises: a write transistor; a read transistor (see para [0036]-[0040] disclosing read/write); and a storage node coupled to a gate of the read transistor (see para [0059] disclosing storage element), wherein the charge- based storage element comprises a capacitor that is formed on the storage node of the circuit(see para [0059] disclosing storage element [0079] disclosing capacitive).
Regarding claim 10, Han, Lee and Ma disclose the circuit of claim 9, wherein a charge of the storage node corresponds to a charge of a gate capacitance of the read transistor(see para [0036]-[0040] disclosing read/write).
Regarding claim 20, Ma and Lee discloses the method of claim 18, but does not explicitly disclose memory cell structure comprises an eDRAM gain-cell.
However, Han discloses a Gain cell bitline cell.
Ma, Lee and Han are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art a time prior to the effective filing date of the present application to combine Han, Lee with Ma. Han and Ma may be combined by forming the device of Han in a gain cell, as disclosed in Ma, see figs 21 and 22, and para [0136].
Claim 17 is rejected under 35 U.S.C. §103 as being unpatentable over Ma and Lee.
Regarding claim 17, Ma and Lee disclose the method of claim 15, wherein a ground connectivity corresponding to the second metal layer is configured for connectivity at either upper or lower portions of the second metal layer (see paras [0119] disclosing power arrangement, see also para [0097]). This office action notes that Ma discloses Power connection arrangements and it would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to connect Ma’s device to power/VCC/ground.
Response to Arguments
Applicants assert that the cited art do not disclose: the charge-based storage element is disposed at least partially in a shallow-trench-isolation (STI) region of the circuit. Applicant appears to interpret the claim narrowly and asserts that the Lee’s Charge-based storage element is recessed into and surrounded by an STI material. However, this office action notes that the claims do not recite this feature. Instead, the claims recite exceedingly broad limitations of the charge based storage element merely being in the STI “region” Clearly, Lee discloses this, as 18/24 is in the recessed STI region of 18:
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Thus, applicant’s assertions are not persuasive. However, should applicant amend independent claims to instead recite that the charge storage element is surrounded by STI material and is partially recessed into the substrate into the STI material, such an amendment would likely overcome the cited art.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD CHIN whose telephone number is (571)270-1827. The examiner can normally be reached M-F 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDWARD CHIN/Primary Examiner, Art Unit 2893