DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. It is suggested that the Applicant amend the title to include a part directed to the interactivity of the fins.
Response to Arguments
Applicant's arguments filed 11/20/2025 have been fully considered but they are not persuasive. In specific, Applicant argues that Lee does not disclose that the channel extends from the first source/drain region around the one or more middle fins and on to the second source/drain region.
In response, although Lee is not explicit in its disclosure of the above referenced limitation, a person of ordinary skill in the art, in keeping with the broadest reasonable interpretation of the claims, would understand that the channel would form from the first S/D region extending to other portions of the structure, including around the one or more middle fins and onto the second S/D region as a matter of inherency in operation i.e., the function of an identical device is presumed to be inherent. M.P.E.P. 2112 III.
The formation of the channel of the claims requires operation of the device as informed by the as-filed specification ¶ [0031]. Lee does not disclose or teach the result of operating the device of fig. 4 but if a voltage is applied to the first S/D region (in operation; the region annotated below) through the buried contact 154 immediately above the first S/D region, a conductive channel (i.e., a flow of charge carriers) would inherently form to other parts of the structure including to the second S/D region (105b below). This flow would be inherent because charge is applied to a semiconductive material (active region 105) [0037] wherein charge carriers would be encouraged by the recited “active” (presumed to mean electrically active) nature to flow to all parts (in varying concentrations) of this material. Thus, there would inherently exist at least one pathway i.e., channel, which forms to satisfy the requirements of the channel of claim 1. This rationale, being provided as required by, and seemingly satisfying the requirements of, M.P.E.P. 2112 IV.
In addition to the above, because Lee discloses an identical structure to the structure of claim 1, and because the formation of the channel of claim 1 requires operation of the device (as-filed specification ¶ [0031]), it is reasonably concluded that the channel limitations, argued as patentable by Applicant, amount to function, such function not supporting allowability when an identical structure is taught by the reference. M.P.E.P. 2112 III.
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Annotated fig. 4 from Lee
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 8, 9, 10, & 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Pat. Pub. No. US 20210126098 A1 Lee et al. (hereinafter “Lee”).
Regarding claim 1, Lee teaches a transistor (transistor shown in the differing views of figs. 1-12B) [0011]-[0017], comprising:
a first source/drain region (105b located on an opposite side in a DR1 direction as annotated below, hereinafter “first S/D”; fig. 4) [0066] coupled to a top (vertically top in fig. 4) of a first fin (annotated below, hereinafter “first fin”) and a second source/drain region (105b as Lee shows in fig. 4, on an opposite side from “first S/D” annotated below, hereinafter “second S/D”; fig. 4) [0066] coupled to a top of a second fin (area immediately below and in direct contact with 105b as annotated by Lee; fig. 4) [0066];
one or more middle fins (area immediately below and in direct contact with 105a in the horizontal middle of the structure shown in fig. 4, hereinafter “middle fin”; fig. 4) [0066] located laterally between the first fin (first fin) and the second fin (second fin) to form a channel (conductive path between the first and second fin through active region 105; fig. 4) [0037] that extends from the first source/drain region (first S/D) around (not explicitly taught, see below) the one or more middle fins and on to the second source/drain region (second S/D);
a number of conductive lines (gate electrodes 137 which flank the middle fin 105a; fig. 4) [0059] passing through trenches (115T; fig. 4) [0054] between the first fin (first fin), the second fin (second fin), and the one or more middle fins (middle fin); and
a gate dielectric layer (136; fig. 4) [0056] between the number of conductive lines (135) and the first fin (first fin), the second fin (second fin), and the one or more middle fins (middle fin).
Although Lee is not explicit in its disclosure of the channel extending from the first S/D region around the middle fins and onto the second S/D region, a person of ordinary skill in the art, in keeping with the broadest reasonable interpretation of the claims, would understand that the channel would form from the first S/D region extending to other portions of the structure, including around the one or more middle fins and onto the second S/D region as a matter of inherency in operation i.e., the function of an identical device is presumed to be inherent. M.P.E.P. 2112 III.
The formation of the channel of the above claim requires operation of the device as informed by the as-filed specification ¶ [0031]. Lee does not disclose or teach the result of operating the device of fig. 4 but if a voltage is applied to the first S/D region (in operation; the region annotated below) through the buried contact 154 immediately above the first S/D region, a conductive channel (i.e., a flow of charge carriers) would inherently form to other parts of the structure including to the second S/D region (105b below). This flow would be inherent because charge is applied to a semiconductive material (active region 105) [0037] wherein charge carriers would be encouraged by the recited “active” (presumed to mean electrically active) nature to flow to all parts (in varying concentrations) of this material. Thus, there would inherently exist at least one pathway i.e., a channel, which would form to satisfy the requirements of the channel of the above claim. This rationale, being provided as required by, and satisfying the requirements of, M.P.E.P. 2112 IV.
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Annotated fig. 4 from Lee
Regarding claim 2, Lee teaches the transistor of claim 1, further including silicon nitride layer (part of the gate dielectric 136) over the number of conductive lines (137). To further clarify, Lee teaches that the gate dielectric layer may include “at least one of… silicon nitride.” Lee [0057] (emphasis added by Examiner). This teaching from Lee allows for interpretation of layers with mixed and separate composition. It is understood that Lee may deposit materials of differing composition which make up the gate dielectric layer 136, silicon nitride being one of the options.
Regarding claim 3, Lee teaches the transistor of claim 1, wherein the number of conductive lines (137) are located below (vertically below in the direction of DR4 in fig. 4) the top of the first fin (first fin) and the top of the second fin (second fin).
Regarding claim 4, Lee teaches the transistor of claim 1, further including a gate contact (buried contact BC; fig. 2) [0031] & [0059] coupled to more than one of the number of conductive lines (137 which may be a word line WL). To further clarify, Lee teaches that the conductive lines 137 may be considered as word lines [0031] (see also fig. 2 and compare fig. 2 to fig. 4 which is cross section B-B’). Lee further teaches that the buried contacts may connect the word lines with active regions [0059], thus providing a contact.
Regarding claim 8, Lee teaches the transistor of claim 1, further including an isolation structure (isolation film 114; fig. 4) [0035] on either side (horizontally flanking) of the transistor formed beneath (beneath in the direction of DR4; fig. 4) one of the number of conductive lines (137).
Regarding claim 9, Lee teaches a semiconductor device (transistor shown in the differing views of figs. 1-12B) [0011]-[0017], comprising:
an array of memory cells (cells in fig. 2) [0021], including a number of parallel word lines (gate electrodes 132 on the edges of fig. 4 and gate electrodes 137 between 132, hereinafter “word lines”; fig. 4) [0031], [0055], & [0059];
a sub word line driver (structure between 132 in fig. 4; fig. 4) located between portions of the array of memory cells (cells shown in fig. 2);
wherein the sub word line driver (between 132) includes one or more transistors that include;
a first source/drain region (105b located on an opposite side in a DR1 direction as annotated below, hereinafter “first S/D”; fig. 4) [0066] coupled to a top (vertically top in fig. 4) of a first fin (annotated below, hereinafter “first fin”) and a second source/drain region (105b as Lee shows in fig. 4, on an opposite side from “first S/D” annotated below, hereinafter “second S/D”; fig. 4) [0066] coupled to a top (vertically top in fig. 4) of a second fin (area immediately below and in direct contact with 105b as annotated by Lee; fig. 4) [0066];
one or more middle fins (area immediately below and in direct contact with 105a in the horizontal middle of the structure shown in fig. 4, hereinafter “middle fin”; fig. 4) [0066] located laterally between the first fin (first fin) and the second fin (second fin) to form a channel (conductive path between the first and second fin through active region 105; fig. 4) [0037] that extends from the first source/drain region (first S/D) around (not explicitly taught, see below) the one or more middle fins and on to the second source/drain region (second S/D);
wherein at least a portion of the number of parallel word lines (132) pass through trenches (115T; fig. 4) [0054] between the first fin (first fin), the second fin (second fin), and the one or more middle fins (middle fins); and
a gate dielectric layer (136; fig. 4) [0056] between the portion of the number of parallel word lines (132) and the first fin (first fin), the second fin (second fin), and the one or more middle fins (middle fins).
Although Lee is not explicit in its disclosure of the channel extending from the first S/D region around the middle fins and onto the second S/D region, a person of ordinary skill in the art, in keeping with the broadest reasonable interpretation of the claims, would understand that the channel would form from the first S/D region extending to other portions of the structure, including around the one or more middle fins and onto the second S/D region as a matter of inherency in operation i.e., the function of an identical device is presumed to be inherent. M.P.E.P. 2112 III.
The formation of the channel of the above claim requires operation of the device as informed by the as-filed specification ¶ [0031]. Lee does not disclose or teach the result of operating the device of fig. 4 but if a voltage is applied to the first S/D region (in operation; the region annotated below) through the buried contact 154 immediately above the first S/D region, a conductive channel (i.e., a flow of charge carriers) would inherently form to other parts of the structure including to the second S/D region (105b below). This flow would be inherent because charge is applied to a semiconductive material (active region 105) [0037] wherein charge carriers would be encouraged by the recited “active” (presumed to mean electrically active) nature to flow to all parts (in varying concentrations) of this material. Thus, there would inherently exist at least one pathway i.e., a channel, which would form to satisfy the requirements of the channel of the above claim. This rationale, being provided as required by, and satisfying the requirements of, M.P.E.P. 2112 IV.
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Annotated fig. 4 from Lee
Regarding claim 10, Lee teaches the semiconductor device of claim 9, wherein the number of parallel word lines (word lines) are separated into an electrically separate array portion (word lines 132) and a sub word line driver portion (word lines 137).
Regarding claim 12, Lee teaches the semiconductor device of claim 9, further including a gate contact (buried contact BC; fig. 2) [0031] & [0059] coupled to multiple word lines (word lines) [0031] & [0059] in the number of parallel word lines (word lines).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 5, 6, & 11 are rejected under 35 U.S.C. 103 as being unpatentable over Lee.
Regarding claim 5, Lee does not explicitly teach the transistor of claim 1, wherein the first fin (first fin), the second fin (second fin), and the middle fins (middle fin) are formed from a P-type substrate. Lee teaches that the active region 105 (wherein each of the first, second, and middle fins are disposed; the fins further being formed therefrom) is doped with impurities to form the S/D regions [0024]. The POSITA, viewing this teaching, then has a finite number of identified, predictable solutions, with a reasonable expectation of success.
It thus would have been obvious to the POSITA to choose P-type impurities to dope the first, second, and middle fins to form a P-type transistor; the finite number of identified, predictable solutions being provided (either P-type of N-type) and a reasonable expectation of success being known (producing a P-type or N-type transistor, depending on the application). M.P.E.P. 2143 I (E).
Regarding claim 6, Lee does not explicitly teach the transistor of claim 1, wherein the first fin (first fin), the second fin (second fin), and the middle fins (middle fin) are formed from a N-type substrate. Lee teaches that the active region 105 (wherein each of the first, second, and middle fins are disposed; the fins further being formed therefrom) is doped with impurities to form the S/D regions [0024]. The POSITA, viewing this teaching, then has a finite number of identified, predictable solutions, with a reasonable expectation of success.
It thus would have been obvious to the POSITA to choose N-type impurities to dope the first, second, and middle fins to form an N-type transistor; the finite number of identified, predictable solutions being provided (either P-type of N-type) and a reasonable expectation of success being known (producing a P-type or N-type transistor, depending on the application). M.P.E.P. 2143 I (E).
Regarding claim 11, Lee teaches the semiconductor device of claim 9 and wherein the at least a portion of the number of parallel word lines (word lines) function as transistor gates (“gate electrode 137,” and “gate electrode 132”).
Lee does not explicitly teach wherein the one or more transistors includes a P-type transistor and an N-type transistor.
Lee, however, teaches that the active region 105 (wherein each of the first, second, and middle fins are disposed; the fins further being formed therefrom) is doped with impurities to form the S/D regions [0024]. The POSITA, viewing this teaching, then has a finite number of identified, predictable solutions, with a reasonable expectation of success.
It thus would have been obvious to the POSITA to form transistors in a structure which have at least one P-type transistor and at least one N-type transistor; the finite number of identified, predictable solutions being provided (P-type of N-type transistors) and a reasonable expectation of success being known (producing a structure with P-type and N-type transistors, each with their own advantages, depending on the application). M.P.E.P. 2143 I (E).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claim 1 above, and further in view of U.S. Pat. Pub. No. US 20180374948 A1 to Naito (hereinafter “Naito”).
Regarding claim 7, Lee does not teach the transistor of claim 1, wherein the first (first S/D) and second source/drains (first S/D) includes a layer of lightly doped and a layer of heavy doped material of opposite conductivity type to the first fin, the second fin, and the middle fins. Lee teaches doping of both the fins and the source/drains but is silent otherwise.
Naito, however, teaches a semiconductor device with buried contact trenches (abstract) wherein the first (first S/D) and second source/drains (composite of source regions 12, contact layer 28, and base region 14, functioning as a source or drain during operation; fig. 1B) [0063], [0066], & [0068] includes a layer of lightly doped (present in element 14) and a layer of heavy doped material (present in element 28) of opposite conductivity type to the first fin (one of accumulation region 16; fig. 1b) [0063], the second fin (one of accumulation region 16; fig. 1b) [0063], and the middle fins (one of accumulation region 16; fig. 1b) [0063].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the dopant concentration of the S/D regions i.e., having a higher concentration in one region, of Lee, being of opposite dopant type when compared to the fins, to allow for device function regardless of miniaturization of the device, thus having little effect on threshold voltage, as taught by Naito [0069].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ETHAN EDWARD CUTLER whose telephone number is (703)756-5415. The examiner can normally be reached Monday-Friday 7:30 am - 5:00 pm Eastern Time.
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/ETHAN EDWARD CUTLER/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892