DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on May 5th 2026 has been entered. Claims 1-25 remain pending in the application. Claims 1-7, 12-14 and 16-20 are examined in this office action. Claims 8-11, 15 and 21-25 are withdrawn from further consideration. Applicant’s amendments to the Drawing and Specification have overcome each and every objection and 112 rejection previously set forth in the Non-Final Office Action mailed on Feb. 9th 2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 6, 12-14 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20200058627) in view of Pietambaram et al. (US 20200312767).
Regarding claim 1, Chen teaches a microelectronic structure (Abstract) including:
a first buildup layer (fig. 2C, dielectric layers 502; para. 0025) and a second buildup layer (dielectric layers 102; para. 0010), the first buildup layer (502) including a first non-conductive material (dielectric layers 502; para. 0025) and first electrically conductive structures (redistribution circuit patterns 504; para. 0025) embedded within the first non-conductive material (502), and the second buildup layer (102) including a second non-conductive material (dielectric layers 102; para. 0010) and second electrically conductive structures (redistribution circuit patterns 104; para. 0010) embedded within the second non-conductive material (102); and
a bridge layer (encapsulation material 400; para. 0019), the bridge layer (400) between the first buildup layer (502) and the second buildup layer (102) and comprising:
an interconnect bridge (bridge structure 300; para. 0014) including third electrically conductive structures (routing patterns 306; para. 0031) coupling a first set of the first electrically conductive structures (middle left 504 connect 300) to a second set of the first electrically conductive structures (middle right 504 connect 300); and
generic vias (conductive pillars 200; para. 0019) extending from a top surface thereof to a bottom surface thereof (top surface to a bottom surface of 400), the generic vias (200) coupling a third set of the first electrically conductive structures (504 not connect 300) to at least some of the second electrically conductive structures (104).
Chen fails to explicitly teach a glass material extending across a width thereof;
the generic vias are through glass vias (TGVs).
However, Pietambaram teaches a glass material (Pietambaram: fig. 2H, glass substrate 210; para. 0057, similar to 400 of Chen) extending across a width (Pietambaram: width of 210);
the generic vias are through glass vias (TGVs) (Pietambaram: through-glass vias (TGVs) 216; para. 0057, similar to 200 of Chen).
Pietambaram and Chen are considered to be analogous to the claimed invention because they are in the same field of packaged semiconductor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add glass material and through glass vias as taught by Pietambaram.
Doing so would realize a glass substrate for warpage mitigation (Pietambaram: para. 0027). Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice.
Regarding claim 2, Chen in view of Pietambaram teaches the microelectronic structure of claim 1, wherein the bridge layer extends (Chen: fig. 2C, 400) along an entire width (Chen: entire width of 502 or 102) of at least one of the first buildup layer or the second buildup layer.
Regarding claim 3, Chen in view of Pietambaram teaches the microelectronic structure of claim 1, wherein the third electrically conductive structures (Chen: fig. 2C, 306 in 300) are embedded in the glass material (Pietambaram: glass substrate 210) of the bridge layer (Chen: 400).
Regarding claim 4, Chen in view of Pietambaram teaches the microelectronic structure of claim 1, wherein:
the bridge layer (Chen: fig. 1A-1B, 400) defines a cavity (Chen: cavity between 200) therein; and
the interconnect bridge (Chen: 300) includes a glass body (Chen: glass substrate 302, dielectric layer 304; para. 0014, 0015), the third electrically conductive structures (Chen: 306) embedded in the glass body (Chen: 302, 304), the glass body (Chen: 302, 304) in the cavity of the bridge layer (Chen: cavity between 200 of 400).
Regarding claim 6, Chen in view of Pietambaram teaches the microelectronic structure of claim 1, the bridge layer (Chen: fig. 2C, 400) including through glass vias (TGVs) (Chen: 200 as 216 of Pietambaram) extending therethrough, the TGVs (Chen: 200 as 216 of Pietambaram) in registration with vias (Chen: 104) of the second buildup layer (Chen: 102).
Regarding claim 12, Chen in view of Pietambaram teaches the microelectronic structure of claim 1, wherein the third electrically conductive structures (Chen: fig. 2C, 306 in 300) have dimensions that are at least about 1/3 smaller than corresponding dimensions of the first electrically conductive structures (504) or of the second electrically conductive structures (104).
Regarding claim 13, Chen teaches a semiconductor package (Abstract), comprising:
a generic board (Chen: fig. 2C, carrier C; para. 0009) including:
a first buildup layer (fig. 2C, dielectric layers 502; para. 0025) and a second buildup layer (dielectric layers 102; para. 0010), the first buildup layer (502) including a first non-conductive material (dielectric layers 502; para. 0025) and first electrically conductive structures (redistribution circuit patterns 504; para. 0025) embedded within the first non-conductive material (502), and the second buildup layer (102) including a second non-conductive material (dielectric layers 102; para. 0010) and second electrically conductive structures (redistribution circuit patterns 104; para. 0010) embedded within the second non-conductive material (102); and
a bridge layer (encapsulation material 400; para. 0019), the bridge layer (400) between the first buildup layer (502) and the second buildup layer (102) and comprising:
an interconnect bridge (bridge structure 300; para. 0014) including third electrically conductive structures (routing patterns 306; para. 0031) coupling a first set of the first electrically conductive structures (middle left 504 connect 300) to a second set of the first electrically conductive structures (middle right 504 connect 300); and
generic vias (conductive pillars 200; para. 0019) extending from a top surface thereof to a bottom surface thereof (top surface to a bottom surface of 400), the generic vias (200) coupling a third set of the first electrically conductive structures (504 not connect 300) to at least some of the second electrically conductive structures (104); and
a first die (first die 700; para. 0026) and a second die (second die 800; para. 0026) on the generic board (C), the third electrically conductive structures (306) electrically coupling the first die (700) to the second die (800).
Chen fails to explicitly teach the generic board is a printed circuit board;
a glass material extending across a width thereof;
the generic vias are through glass vias (TGVs).
However, Pietambaram teaches the generic board is a printed circuit board (Pietambaram: fig. 2H, printed wiring board 196; para. 0054, similar to C of Chen);
a glass material (Pietambaram: fig. 2H, glass substrate 210; para. 0057, similar to 400 of Chen) extending across a width (Pietambaram: width of 210);
the generic vias are through glass vias (TGVs) (Pietambaram: through-glass vias (TGVs) 216; para. 0057, similar to 200 of Chen).
Pietambaram and Chen are considered to be analogous to the claimed invention because they are in the same field of packaged semiconductor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add glass material and through glass vias as taught by Pietambaram.
Doing so would realize a glass substrate for warpage mitigation and printed wiring board as external boundary of a computing system to connect outside devices (Pietambaram: para. 0027, 0054). Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice.
Regarding claim 14, Chen in view of Pietambaram teaches the semiconductor package of claim 13, wherein the third electrically conductive structures (Chen: fig. 2C, 306 in 300) are embedded in the glass material (Pietambaram: glass substrate 210) of the bridge layer (Chen: 400).
Regarding claim 16, Chen in view of Pietambaram teaches the semiconductor package of claim 13, wherein the glass material (Pietambaram: fig. 2H, 210) includes silicon (Pietambaram: silicon dioxide glass; para. 0027).
Regarding claim 17, Chen in view of Pietambaram teaches the semiconductor package of claim 16, wherein the glass material (Pietambaram: fig. 2H, 210) further includes at least one of oxygen and boron (Pietambaram: silicon dioxide glass; para. 0027).
Claims 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Pietambaram as applied to claim 1 or 6 above, and further in view of Cheah et al. (US 20210183776).
Regarding claim 5, Chen in view of Pietambaram teaches the microelectronic structure of claim 1 including the first buildup layer (Chen: fig. 2C, 502).
Chen in view of Pietambaram fails to explicitly teach a core layer, the first buildup layer, the second buildup layer, and the bridge layer on a top surface or on a bottom surface of the core layer.
However, Cheah teaches a core layer (Cheah: fig. 2, core layer 244; para. 0051), the first buildup layer (Chen: 502 on bridge layer 400), the second buildup layer (Cheah: build-up layers 246; para. 0051, similar to 102 of Chen), and the bridge layer (Cheah: layer of underfill mass 254; para. 0048, similar to 400 of Chen) on a top surface or on a bottom surface of the core layer (Cheah: top surface of 244).
Cheah, Pietambaram and Chen are considered to be analogous to the claimed invention because they are in the same field of packaged semiconductor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a core layer as taught by Cheah.
Doing so would realize a core layer to improve rigidity and adjust z-height (Cheah: para. 0051).
Regarding claim 7, Chen in view of Pietambaram teaches the microelectronic structure of claim 6 including the second buildup layer (Chen: fig. 2C, 102).
Chen in view of Pietambaram fails to explicitly teach the vias of the second buildup layer include an underetch region sharing a surface with a bottom surface of a material of the bridge layer.
However, Cheah teaches the vias (Cheah: fig. 1M, package vias 148; para. 0038, similar to 104 of Chen) of the second buildup layer (Cheah: 246) include an underetch region (Cheah: protrude region above 246) sharing a surface (Cheah: surface between 254 and 246) with a bottom surface of a material of the bridge layer (Cheah: bottom surface of 254).
Cheah, Pietambaram and Chen are considered to be analogous to the claimed invention because they are in the same field of packaged semiconductor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add an underetch region as taught by Cheah.
Doing so would realize a region for vias to accommodates the standoff and secure the connection (Cheah: para. 0037).
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Pietambaram and Guzek et al. (US 20190189564).
Regarding claim 18, Chen teaches an integrated circuit (IC) device assembly (Abstract) including:
a generic board (Chen: fig. 2C, carrier C; para. 0009) including:
a first buildup layer (fig. 2C, dielectric layers 502; para. 0025) and a second buildup layer (dielectric layers 102; para. 0010), the first buildup layer (502) including a first non-conductive material (dielectric layers 502; para. 0025) and first electrically conductive structures (redistribution circuit patterns 504; para. 0025) embedded within the first non-conductive material (502), and the second buildup layer (102) including a second non-conductive material (dielectric layers 102; para. 0010) and second electrically conductive structures (redistribution circuit patterns 104; para. 0010) embedded within the second non-conductive material (102); and
a bridge layer (encapsulation material 400; para. 0019), the bridge layer (400) between the first buildup layer (502) and the second buildup layer (102) and comprising:
an interconnect bridge (bridge structure 300; para. 0014) including third electrically conductive structures (routing patterns 306; para. 0031) coupling a first set of the first electrically conductive structures (middle left 504 connect 300) to a second set of the first electrically conductive structures (middle right 504 connect 300); and
generic vias (conductive pillars 200; para. 0019) extending from a top surface thereof to a bottom surface thereof (top surface to a bottom surface of 400), the generic vias (200) coupling a third set of the first electrically conductive structures (504 not connect 300) to at least some of the second electrically conductive structures (104); and
a first die (first die 700; para. 0026) and a second die (second die 800; para. 0026) on a first face (top side) of the generic board (C), the third electrically conductive structures (306) electrically coupling the first die (700) to the second die (800).
Chen fails to explicitly teach the generic board is a printed circuit board;
a glass material extending across a width thereof;
the generic vias are through glass vias (TGVs).
However, Pietambaram teaches the generic board is a printed circuit board (Pietambaram: fig. 2H, printed wiring board 196; para. 0054, similar to C of Chen);
a glass material (Pietambaram: fig. 2H, glass substrate 210; para. 0057, similar to 400 of Chen) extending across a width (Pietambaram: width of 210);
the generic vias are through glass vias (TGVs) (Pietambaram: through-glass vias (TGVs) 216; para. 0057, similar to 200 of Chen).
Pietambaram and Chen are considered to be analogous to the claimed invention because they are in the same field of packaged semiconductor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add printed circuit board, glass material and through glass vias as taught by Pietambaram.
Doing so would realize a glass substrate for warpage mitigation and printed wiring board as external boundary of a computing system to connect outside devices (Pietambaram: para. 0027, 0054). Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice.
In addition, Chen in view of Pietambaram does not teach a package-on-package structure on a second face of the printed circuit board, the package- on-package structure including a third die and a fourth die, the third die directly coupled to the printed circuit board and between the printed circuit board and the fourth die.
However, Guzek teaches a package-on-package structure (Guzek: fig. 24, package-on-package structure 2434; para. 0093) on a second face (bottom side) of the printed circuit board (Guzek: circuit board 2402; para. 0087), the package- on-package structure (Guzek: 2434) including a third die (Guzek: electronics package 2426; para. 0093) and a fourth die (Guzek: electronics package 2432; para. 0093), the third die (Guzek: 2426) directly coupled to the printed circuit board (Guzek: 2402) and between the printed circuit board (Guzek: 2402) and the fourth die (Guzek: 2432).
Guzek, Pietambaram and Chen are considered to be analogous to the claimed invention because they are in the same field of packaged semiconductor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add package-on-package structure as taught by Guzek.
Doing so would realize package-on-package structure to minimized warpage and reduced z-height (Guzek: para. 0002).
Regarding claim 19, Chen in view of Pietambaram and Guzek teaches the IC device assembly of claim 18, wherein the bridge layer (Chen: fig. 2C, 400) extends along an entire width (Chen: entire width of 502 or 102) of at least one of the first buildup layer or the second buildup layer.
Regarding claim 20, Chen in view of Pietambaram and Guzek teaches the IC device assembly of claim 18, wherein the bridge layer (Chen: fig. 2C, 300 as a part of the bridge layer, OR a part of 400 between 200 at two opposite sides) extends along less than an entire width (Chen: entire width of 502 or 102) of individual ones of the first buildup layer and the second buildup layer.
Response to Arguments
Applicant's arguments filed on May 5th 2026 have been fully considered but they are not persuasive.
With respect to pages 4-5 of applicant’s response of claim 1 is rejected under 35 U.S.C.103.
Applicant submits "Pietambaram et al. is not prior art to the present application under 35 U.S.C. § 102(a)(2), pursuant to 35 U.S.C. § 102(b)(2)(C)".
The examiner respectfully disagrees.
The ref. US 20200312767 of Pietambaram is in 103 and can be applied to 102(a)(1). This ref. of Pietambaram is published on 10/1/20, which is over 1 year before the earliest effective filing date 9/6/22 of the application. Therefore this ref. of Pietambaram is a suitable prior art under 102(a)(1) and not pursuant to 35 U.S.C. § 102(b)(1). As result, given a broadest reasonable interpretation, Chen in view of Pietambaram teaches all limitations of claim 1. Details of rejections are discussed above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIJUN XU whose telephone number is (571)270-3447. The examiner can normally be reached Monday-Thursday 9am-5pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ZHIJUN XU/Examiner, Art Unit 2818
/BRIAN TURNER/Examiner, Art Unit 2818
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