Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Final Office Action
DETAILED ACTION
Examiner’s Notes
(a) Claim date: 01/31/25 (amendment).
(b) Priority date: 12/13/19.
(c ) Non-final OA date: 08/26/2025
Applicant’s argument and Examiner’s Response
Applicant’s arguments have been fully considered; however, some/all are NOT found to be persuasive because of the following reasons:
Examiner:
Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Claim Rejections - 35 USC 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:A person shall be entitled to a patent unless:(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.Claims 1-5, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by the prior art of record Murali (US 8042087 B2)
(As to claim 1, Murali discloses):1. (CURRENTLY AMENDED) A computer-implemented method of designing a network on chip (NoC), the method comprising [5: “Networks on Chips (NoCs)”]:
defining a topology of the NoC having a set of constraints [10: “topology is achieved by a method to design Networks on Chips (NoCs)”];
approximating area and timing of components defined as part of the topology [19: “Perform floorplan of the synthesized topology, get link power consumption, detect timing delays 6: end for 7: end for 8: end for 9: Choose topology that best optimizes user objectives”]
by mapping at least one synthesis primitive to each component of the topology based on at least one constraint provided for the topology [6: “setting various design parameters (such as frequency of operation or link width), generating the RTL code for the network components and generating the physical design (such as synthesis and layout) models”],
wherein the at least one constraint includes at least one of timing and area [20: “accurate area, power and timing models for the NoC components further bridges the gap between the topology design phase”]; and
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generating a complete register transfer level (RTL) description of the topology if the approximated area and timing satisfy the constraints [Fig. 1, RTL description is pointed/highlighted by using an arrow].
(As to claim 2, Murali discloses):2. (Original) The method of claim 1,
wherein the NoC is designed subject to the set of constraints including area constraints and timing constraints [20: “make sure as early as possible, i.e. during the topology generation phase itself, that the timing constraints after the place & route phase will not be violated”] and
wherein the approximations consist of the timing approximations and area approximations that are compared to the timing constraints and area constraints to determine whether the constraints are satisfied [12: “area, wire length, size (number of inputs, outputs) of the switches, delay, and maximum possible speed of operation. Some of these metrics can be used as objectives to be optimized by the method, while some can be used as constraints that need to be me”; note: claim limitation “approximation” is functionally equivalent to the disclosure “optimized” of the prior art].
(As to claim 3, Murali discloses):3. (Original) The method of claim 1, wherein performing the area approximations and timing approximations includes [19: “Perform floorplan of the synthesized topology, get link power consumption, detect timing delays 6: end for 7: end for 8: end for 9: Choose topology that best optimizes user objectives”]:
using a library of basic primitives to synthesize components in the complete RTL description to primitive gates [Fig. 1 above, RTL block (arrow)]; and
determining the area and timing from the primitive gates [Fig. 1].
(As to claim 4, Murali discloses):4. (Original) The method of claim 3, wherein the approximation of timing is based on delays through the gates and not delays through wires connecting the gates [6: “setting various design parameters (such as frequency of operation or link width), generating the RTL code for the network components and generating the physical design (such as synthesis and layout)”, Note: the claimed limitation “not delays through wires connecting the gate” is open ended. As known in the pertinent art, during design optimization, various design “weight” values are applied into each design constraints, including: timing, placement, critical dimensions and etc. Adding more/max emphasis on gate delay and less/none on interconnect is just one of the many combinations].
(As to claim 5, Murali discloses):5. (Original) The method of claim 1,
wherein the topology is designed for a system- on-chip (SoC) and wherein the complete RTL description is delivered to a SoC integrator [2: “multicore systems (MCSs) integrate several processor cores, hardware blocks, co-processors, memories, Digital Signal Processors (DSPs) and I/O blocks on the same chip”, note: prior art disclosure is functionally equivalent to SoC.]
having a full library of primitives for generating an exact complete RTL description of the SoC and wherein the library of basic primitives is substantially smaller than the full library [Fig. 1 depicts these features. Note: library primitives are subset of full library, therefore, will be smaller as to common sense].
Allowable Subject Matter
The following claims would be allowable if all rejections/objections cited in this office action (if any) are overcome and rewritten to include all of the limitations of the base claim and any intervening claims.The reason for this allowance is: the claimed subject matter could not have been anticipated or obviated using any prior arts.Allowable claims are: 7, 9 and 10-11.
Conclusion
If any prior art made of record in the form PTO-892 and not relied upon, then those arts should simply be considered as pertinent, to the applicant's disclosure.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
The time for reply to a final rejection is as follows (MPEP paragraphs: 7.39, 7.40, 7.40.01, 7.40.02.fti, 7.40.02.aia, 7.41, 7.41.03, 7.42.03.fti, 7.42.031.fti, or 7.42.09):
A shortened statutory period will expire at 3 months from the date of the final rejection or on the date the advisory action is mailed, whichever is later. Thus, a variable reply period will be established. If the last day of "2 months of the date of the final Office action" falls on Saturday, Sunday, or a federal holiday within the District of Columbia, and a reply is filed on the next succeeding day which is not a Saturday, Sunday, or a federal holiday, pursuant to 37 CFR 1.7(a), the reply is deemed to have been filed within the 2 months period and the shortened statutory period will expire at 3 months from the date of the final rejection or on the mailing date of the advisory action, whichever is later (see MPEP § 710.05). In no event can the statutory period for reply expire later than 6 months from the mailing date of the final rejection.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED ALAM at telephone number is (571) 270-1507, fax number is (571) 270-2507 and email address:mohammed.alam@uspto.gov. The examiner can normally be reached on 10AM to 4PM (EST), Monday to Thursday. If attempts to reach the examiner by telephone are unsuccessful, the Examiner’s Supervisor, JACK CHIANG can be reached on (571) 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Mohammed Alam/
Primary Examiner, Art Unit 2851