Prosecution Insights
Prosecution Insights
Technology areas: Computing & Software • Networking & Security • Semiconductors, Circuits & Optics
5 pending office actions • 3 art units • 5 examiners • 0 of 5 (0%) have an AI response strategy ready • 12 patents granted in the last 365 days
Arteris Inc. currently manages 5 pending office actions within the Semiconductors, Circuits & Optics technology area. These matters are distributed across 3 distinct art units, indicating a focused but multi-disciplinary approach to their patent portfolio. The involvement of 5 distinct examiners suggests that each pending action is being handled by a different individual at the office.
Among the active examiners, LIN, ARIC is identified as the busiest, though this individual is responsible for 1 pending action. This distribution shows that no single examiner holds a disproportionate share of the company's current workload. Practitioners should prepare for varied perspectives across the examiners currently reviewing the portfolio.
Based on the USPTO statutory response window for each pending office action. 2 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §101 + other | 1 (20%) |
| §103 only | 1 (20%) |
| Double-patenting only | 2 (40%) |
| Multi-statute (no §101) | 1 (20%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| LIN, ARIC | 1 | 59.8% | +12.4% |
| HAJ SAID, FADI | 1 | 79.2% | +19.7% |
| BOWERS, BRANDON | 1 | 86.3% | +6.4% |
| FAAL, BABOUCARR | 1 | 80.6% | +14.3% |
| DILUZIO, NICHOLAS JOSEPH | 1 | 31.3% | +83.3% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 1 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 19061951 | ELECTRONIC DESIGN TOLL FOR GENERATION OF A NETWORK-ON-CHIP (NoC) | BOWERS, BRANDON | — |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 2 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 19257390 | REINFORCED LEARNING FOR TOPOLOGY GENERATION OF A NETWORK-ON-CHIP | LIN, ARIC | 28d |
| 18901002 | COHERENT TRAFFIC ACCELERATION FOR A DIRECTORY-BASED MULTI-CORE ELECTRONIC SYSTEM | FAAL, BABOUCARR | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 4 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 17834808 | Using Information Flow For Security Exploration and Analysis | DILUZIO, NICHOLAS JOSEPH | 36d overdue |
| 19257390 | REINFORCED LEARNING FOR TOPOLOGY GENERATION OF A NETWORK-ON-CHIP | LIN, ARIC | 28d |
| 19221575 | MODIFICATION OF EXISTING NETWORK-ON-CHIPs (NoCs) USING INCREMENTAL MODIFICATIONS | HAJ SAID, FADI | — |
| 18901002 | COHERENT TRAFFIC ACCELERATION FOR A DIRECTORY-BASED MULTI-CORE ELECTRONIC SYSTEM | FAAL, BABOUCARR | — |
| Art Unit | Apps |
|---|---|
| 2851 | 1 |
| 2138 | 1 |
| 2498 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 19257390 | REINFORCED LEARNING FOR TOPOLOGY GENERATION OF A NETWORK-ON-CHIP | LIN, ARIC | 2851 | §101§103§112 | Non-Final OA | 28d | Pending | Jul 01, 2025 |
| 19221575 | MODIFICATION OF EXISTING NETWORK-ON-CHIPs (NoCs) USING INCREMENTAL MODIFICATIONS | HAJ SAID, FADI | — | DP | Non-Final OA | — | Pending | May 29, 2025 |
| 19061951 | ELECTRONIC DESIGN TOLL FOR GENERATION OF A NETWORK-ON-CHIP (NoC) | BOWERS, BRANDON | — | DP | Non-Final OA | — | Pending | Feb 24, 2025 |
| 18901002 | COHERENT TRAFFIC ACCELERATION FOR A DIRECTORY-BASED MULTI-CORE ELECTRONIC SYSTEM | FAAL, BABOUCARR | 2138 | §102§103 | Final Rejection | — | Pending | Sep 30, 2024 |
| 17834808 | Using Information Flow For Security Exploration and Analysis | DILUZIO, NICHOLAS JOSEPH | 2498 | §103 | Final Rejection | 36d overdue | Pending | Jun 07, 2022 |
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