DETAILED ACTION
Claims 1-5, 8-16, 19-25, and 29-31 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 2 (and similarly each of claims 13 and 23) is objected to because of the following informalities:
Since identifying the portion was deleted from claim 1, the “wherein…” should be worded as a separate step, e.g. by replacing “data, wherein” with
--data; and-- and starting a new paragraph with --identify a portion of the firmware data comprising the first compressed bank data based…--.
Claims 13-16 and 19-21 are objected to because of the following informalities:
Each claim claims “The non-transitory computer-readable medium of…”. However, claim 12 is for a memory circuit comprising a medium. Thus, each of these claims should claim --The memory circuit of claim…--. Alternatively, applicant may delete “memory circuit comprising a” from claim 12, line 1, and replace the first instance of “the” with --a-- in claim 12, line 3.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 5 and 16 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Referring to claim 5, parent claim 1 sets forth that the memory circuit is to decompress a first compressed bank data, of the plurality of compressed bank data, to obtain a first bank data. Claim 5 only additionally adds that a portion of the firmware data is read to obtain the first bank data. However, in claim 1, in order to decompress first compressed bank data, that data must be read (from some portion of the plurality of compressed bank data). Thus, the examiner does not see how claim 5 adds anything beyond that which is already in claim 1. Applicant may cancel claim 5, amend it to be in proper dependent form, or present a sufficient showing that the it complies with the statutory requirements.
Claim 16 is rejected for similar reasoning.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-5, 8-16, and 19-25, and 29-31 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception without significantly more.
Regarding step 1 of the subject matter eligibility test (MPEP 2106), claims 1-5, 8-16, 19-21, and 29-31 are to a machine/manufacture, and claims 22-25 are to a process.
Regarding claim 1:
Considering step 2A (prong 1) of the test, the claim recites:
identify[ing], based at least in part on a quantity of compressed bank data of firmware data comprising a plurality of compressed bank data, and the size of each compressed bank data, a boundary of each compressed bank data of the plurality of compressed bank data, the firmware data comprising a bank header, wherein the bank header indicates the quantity of compressed bank data within the plurality of compressed bank data, and wherein the bank header indicates the size of each compressed bank data of the plurality of compressed bank data; and
decompress[ing], based at least in part on identifying the boundary of each compressed bank data, a first compressed bank data, of the plurality of compressed bank data, to obtain a first bank data corresponding to a first bank of the plurality of banks.
Limitation (a) constitutes an abstract idea that falls into the category of mental processes (MPEP 2106.04(a) and (a)(2)(III)). A human can analyze binary data of firmware to detect the quantity and size data therein, and then use that to identify boundaries of compressed bank data. This involves actions including one or more of observing, evaluating, or judging.
Limitation (b) constitutes an abstract idea that falls into the category of mathematical concepts. For instance, decompressing data involves a mathematical relationship such as “organizing information and manipulating information through mathematical correlations, Digitech Image Techs., LLC v. Electronics for Imaging, Inc., 758 F.3d 1344, 1350, 111 USPQ2d 1717, 1721 (Fed. Cir. 2014). The patentee in Digitech claimed methods of generating first and second data by taking existing information, manipulating the data using mathematical functions, and organizing this information into a new form. The court explained that such claims were directed to an abstract idea because they described a process of organizing information through mathematical correlations, like Flook's method of calculating using a mathematical formula. 758 F.3d at 1350, 111 USPQ2d at 1721.” (see MPEP 2106.04(a)(2)). Alternatively, limitation (b) could also be considered a mental process that is practically performed in the human mind with the aid of pen and paper, for instance. The firmware data, as claimed, could be any size, including a small portion of firmware data to which an algorithm can be practically applied by a human to decompress the data as part of a mental exercise.
Considering step 2A (prong 2) of the test, the claim recites additional elements of:
a memory circuit comprising a plurality of banks and processing circuitry coupled with the plurality of banks and configured to cause the memory circuit to perform the claimed operations; and
access the firmware data associated with the memory circuit.
The components are generic computer components used as a tool to perform the abstract idea. The accessing of data is insignificant pre-solution activity that is incidental to the primary abstract idea and is a mere nominal addition to the claim. The courts have identified such generic components and activity as not integrating the abstract idea into a practical application (MPEP 2106.04(d)(I), 6th and 7th bullets).
Considering step 2B of the test, and considering the additional elements both individually and in combination, the courts have identified that the generic components to perform the abstract idea also do not amount to significantly more (MPEP 2106.05(I)(A)). Furthermore, the courts have determined that accessing data (e.g. over some network or from memory) is well-understood, routine, and conventional activity that does not amount to significantly more (MPEP 2106.05(I)(A) and 2106.05(d)(II)(i) or (iv)).
Thus, claim 1 is not patent-eligible under 101.
Regarding claims 2-4, the claims involve determining steps according to indicator data in the header. This is part of a mental process that defines data and evaluation (or observation or judgment) steps to be practically performed by a human brain. Since there are no additional elements, the judicial exception(s) are not integrated into an application, and there is not significantly more.
Regarding claim 5, the claimed reading is either (1) part of the mental process, in which case there are no additional elements and, thus, no integration into a practical application or significantly more, or (2) a well-understood, routine, conventional insignificant pre-solution activity, which the courts have deemed to not integrate or amount to significantly more (MPEP 2106.05(d)(II)(i) or (iv)).
Referring to claim 8, the claim merely further defines the data that is processed mentally by a human. There is no additional element to integrate the judicial exception(s) into a practical application or amount to significantly more.
Referring to claim 9, an error control operation on data is performed. This is at least one of a mental process and mathematical concept. Thus, the claim only further sets forth a judicial exception, not an additional element to integrate the judicial exception(s) into a practical application or amount to significantly more.
Referring to claim 10, applicant claims storing the first bank data based on decompressing, e.g. storing decompressed data. Storing to memory is insignificant post-solution activity that has been deemed by the courts as well-understood, routine, conventional activity. Thus, again, there is no integration or significantly more (MPEP 2106.05(d)(II)(iv)).
Referring to claim 11, applicant claims receiving the firmware data. Receiving from memory/network is insignificant pre-solution activity that has been deemed by the courts as well-understood, routine, conventional activity. Thus, again, there is no integration or significantly more (MPEP 2106.05(d)(II)(i) or (iv)).
Claim 12 is mostly not patent-eligible for similar reasoning as claim 1. The additional element of the non-transitory medium that stores instructions that cause the steps to occur is a combination of a generic computer component (medium/memory) and instructions to implement the abstract idea, which is not enough to integrate into a practical application or amount to significantly more (MPEP 2106.04(d)(I), 6th bullet, and 2106.05(I)(A)).
Claims 13-16 and 19-25 are not patent-eligible for similar reasoning as claims 2-5, 8-10, and 1-4, respectively.
Claims 29-30 merely define properties of the data based on lack of inclusion of dummy data. Analyzing such data is simply part of the mental process and there is not an additional element to integrate or amount to significantly more.
Claim 31 merely define a property of the data based where each segment corresponds to banks of a memory circuit. Analyzing such data is simply part of the mental process and there is not an additional element to integrate or amount to significantly more.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5, 8-13, 16, 19, 23, and 29-31 are rejected under 35 U.S.C. 103 as being unpatentable over O’Neill, U.S. Patent No. 6,832,373, in view of Yoon (US 5,978,589) and Chu (US 5,734,892).
Referring to claim 1, O’Neill has taught a memory circuit, comprising:
a plurality of banks (see FIGs.8A and 10, and column 30, line 42, to column 31, line 27); and
processing circuitry (see column 5, line 60, to column 6, line 8) coupled with the plurality of banks and configured to cause the memory circuit (see column 7, lines 23-29, and FIG.8A. A computer having memory may be the memory circuit) to:
access firmware data (column 33, lines 32-36) associated with the memory circuit, the firmware data comprising a bank header (see column 18, lines 6-11) and a plurality of compressed bank data (see column 18, lines 3-11, column 30, lines 31-37, column 34, lines 22-23 and 50-54, and column 37, lines 16-40, along with FIGs.9 and 11 and their descriptions. In summary, the firmware update package, which may be compressed (e.g. via LZW compression (column 18, lines 3-6)), includes various compressed bank information for the system (code to initialize bank pointer, code to update current firmware banks, bank size information, CRC information for fault tolerance during update, etc.)),
wherein the bank header indicates a size of each compressed bank data of the plurality of compressed bank data (see column 30, lines 31-37, which specify the size of each bank to be updated. For each bank, a corresponding size of code/data in the update package will be accessed to update that bank. Thus, a specified bank size determines a size of the data to be accessed).
O’Neill has taught that the header includes “file or bank sizes” (column 30, lines 31-37), but not necessarily both. Based on including bank sizes in the header (see above), O’Neill has not explicitly taught wherein the bank header indicates a quantity of compressed bank data within the plurality of compressed bank data. However, Yoon has taught a benefit for why a transmitted file would include a header that indicates a size of the file. Specifically, the receiving system is able to verify whether all the expected data has been received. See the abstract and FIG.3 (and its description). Such information would allow O’Neill to determine whether all data has been received or whether some error has occurred that prevented all data from arriving (so that corrective action could be taken) (e.g. see column 33, lines 49-52). Additionally, O’Neill determines whether there is sufficient storage to accommodate a downloaded file and, if not, room is made by offloading currently-stored data to different storage (column 15, line 61, to column 16, line 2). One of ordinary skill in the art would have recognized that the size information in the header could be used to help O’Neill make the determination of whether sufficient storage is available, i.e., if the size indicated is X, and O'Neill determines that less than X memory space is available, some storage locations could be freed to make room. For these reasons, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify O’Neill’s bank header to, in addition to indicating bank sizes, indicate a quantity of compressed bank data within the plurality of compressed bank data.
O’Neill, as modified, has taught that the memory circuit is to identify, based at least in part on the quantity of compressed bank data and the size of each compressed bank data, a boundary of each compressed bank data of the plurality of compressed bank data (based on FIG.9 and its description in column 31, line 55, to column 33, line 20, one bank is updated at a time. The code (instructions/data) to perform the update is pointed to in order to update the current bank. Thus, for each bank size, the corresponding code/data is pointed to (boundary of the current code/data is determined). And, this will occur for the entirety of the update file. In other words, boundaries are determined for all segments of code/data in the entirety of the file in order to update each corresponding bank size.
O'Neill, as modified, has not taught that the memory circuit is to decompress, based at least in part on identifying the boundary of each compressed bank data, a first compressed bank data, of the plurality of compressed bank data, to obtain a first bank data corresponding to a first bank of the plurality of banks. However, Chu has taught decompressing on demand, and only decompressing the desired/current part of the file being accessed (column 6, lines 5-8, and column 7, lines 8-18 and 53-56). Decompressing the entire file at once may be impractical and time-consuming with large files and may exceed the size of the available memory (column 5, lines 38-42). Thus, decompressing only portions as they are needed in Chu could reduce the memory requirements for the program, which means less available space needs to be reserved, which in turn means less offloading (and offloading time) may be required in O’Neill. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify O’Neill to decompress, based at least in part on identifying the boundary of each compressed bank data, a first compressed bank data, of the plurality of compressed bank data, to obtain a first bank data corresponding to a first bank of the plurality of banks. That is, when a first bank is being updated, only the code/data of the update file will be decompressed so as to make the bank update. Then, when the second bank is being updated, only the code/data for that bank will be decompressed, and so on.
Referring to claim 2, O’Neill, as modified, has taught the memory circuit of claim 1, wherein the processing circuitry is further configured to cause the memory circuit to: determine whether the firmware data comprises the plurality of compressed bank data or a second plurality of uncompressed bank data, wherein identifying a portion of the firmware data comprising the first compressed bank data is based at least in part on determining that the firmware data comprises the plurality of compressed bank data (from column 18, lines 3-6, and column 34, lines 22-23, compression may occur in O’Neill and is, thus, optional. Thus, it must be determined whether the data is compressed or uncompressed so that, if the former, the data can be uncompressed. If compression is indicated, then first compressed bank data is identified).
Referring to claim 5, O’Neill, as modified, has taught the memory circuit of claim 1, wherein the decompressing is configured to cause the memory circuit to: read a portion of the firmware data comprising the first compressed bank data to obtain the first bank data (if the package is compressed, all data therein is decompressed, including the first compressed bank data to obtain the first bank data, which is used to update the first bank).
Referring to claim 8, O’Neill, as modified, has taught the memory circuit of claim 1, wherein the bank header comprises a plurality of error control information corresponding to the plurality of compressed bank data (see column 33, lines 37-61, and column 18, lines 6-11. CRC codes and digital signatures are included for error control, as is validation information).
Referring to claim 9, O’Neill, as modified, has taught the memory circuit of claim 8, wherein the processing circuitry is further configured to cause the memory circuit to: perform, based at least in part on the decompressing, an error control operation on the first bank data based at least in part on first error control information of the plurality of error control information (as described, error control for all package data, including first bank data, is performed based on the error control information. And since all package data is decompressed (when indicated by the header as being compressed), the error control is partly based on the result of the decompression. Note FIG.11 (and its description) as well, which performs specific error control operation for the bank at which the update failed, which could include any bank, including the first bank).
Referring to claim 10, O’Neill, as modified, has taught the memory circuit of claim 1, wherein the processing circuitry is further configured to cause the memory circuit to: store the first bank data at the processing circuitry based at least in part on the decompressing (see column 16, lines 32-42. When decompressed, the decompressed data has to be stored to memory where it will wait for the update. Also, see column 29, lines 17-30, where based on the decompression, the system determines if there is enough storage for the package and, if not, current data on the computer may be rearranged/compressed so as to make room for the decompressed package).
Referring to claim 11, O’Neill, as modified, has taught the memory circuit of claim 1, wherein the processing circuitry is further configured to cause the memory circuit to: receive the firmware data, wherein accessing the firmware data is based at least in part on receiving the firmware data (see FIG.2A and the description thereof).
Claim 12 is mostly rejected for similar reasoning as claim 1. Further, to perform all of the claimed operations, a processor executes instructions stored in a memory (non-transitory computer-readable medium).
Claims 13, 16, and 19-23 are rejected for similar reasoning as claims 2, 5, 8-10, and 1-2, respectively.
Referring to claim 29, O’Neill, as modified, has taught the memory circuit of claim 1, wherein the plurality of compressed bank data is compressed based at least in part on one or more compressed bank data refraining from including dummy data (see column 18, lines 3-6, which disclosed using LZW to compress the firmware update. Per Wikipedia (“Lempel-Ziv-Welch), which was previously cited and is used herein as extrinsic evidence, LZW compresses repeated data compactly (see the “Example” section). Repeated data may be deemed dummy data. Thus, LZW compression involves refraining from including dummy data).
Referring to claim 30, O’Neill, as modified, has taught the memory circuit of claim 29, wherein the plurality of compressed bank data is contiguous based at least in part on refraining from including the dummy data (see the “Example” section of Wikipedia. The compressed data is a sequence of contiguous bit codes that omits the full dummy data).
Referring to claim 31, O’Neill, as modified, has taught the memory circuit of claim 1, wherein each compressed bank data of the plurality of compressed bank data is associated with a respective bank of the plurality of banks (again, each firmware bank is updated one bank at a time. Thus, there is a compressed segment of code/data that corresponds to each firmware bank to be updated).
Claims 3-4, 14-15, and 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over O’Neill in view of Yoon, Chu, and Osthoff et al. (US 2005/0091501).
Referring to claim 3, O’Neill, as modified, has taught the memory circuit of claim 2, but has not taught wherein: the firmware data comprises an indication of whether the firmware data comprises the plurality of compressed bank data or whether the firmware data comprises the second plurality of uncompressed bank data; and determining that the firmware data comprises the plurality of compressed bank data is based at least in part on the indication. However, Osthoff has similarly taught transmitting software as a payload with a header that indicates whether the payload is compressed, and, if so, the type of compression used (see paragraph [0094], which states “The header 301 further comprises…a command section indicating parameters used by the mobile terminal during the processing of the payload…The parameters may further comprise information about whether and what type of compression and/or encryption is used”). One of ordinary skill in the art would have recognized that to implement optional compression in O’Neill, indicating the composition of the package data, i.e., whether it is compressed or not, and then providing the compression type, would inform the receiver as to the type of data being received and allow the receiver to quickly select the appropriate decompression routine that corresponds to the selected compression type. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify O’Neill such that the firmware data comprises an indication of whether the firmware data comprises the plurality of compressed bank data or whether the firmware data comprises the second plurality of uncompressed bank data; and determining that the firmware data comprises the plurality of compressed bank data is based at least in part on the indication.
Referring to claim 4, O’Neill, as modified, has taught the memory circuit of claim 3, wherein: the firmware data comprises a firmware header indicating a composition of the firmware data; and the firmware header comprises the indication of whether the firmware data comprises the plurality of compressed bank data or the second plurality of uncompressed bank data (see the rejections of claims 1 and 3 and note that the indicator may be considered part of the header since it is not part of the update program itself (it is merely metadata providing information about the program)).
Claims 14-15 and 24-25 are rejected for similar reasoning as claims 3-4 and 3-4, respectively.
Response to Arguments
On pages 12-13 of the response, applicant argues that CRC is not a quantity of compressed bank data within the plurality of compressed bank data.
The examiner agrees, but notes that this is at least obvious in view of Yoon.
On page 13 of the response, applicant argues that the bank size data of O’Neill indicates a size of a bank structure and not a size of the compressed data.
Even if this is the case, bank structures, each containing current firmware, are updated serially (one at a time). Each bank has corresponding code/data in the update package that corresponds only to that bank. Thus, by determining that a given bank structure is X, the system is determining the size of code/data in the update package that will be accessed in order to update that bank.
On page 14 of applicant’s response, applicant argues that any boundary in O’Neill is for a physical bank, not for the compressed data.
The examiner asserts these two are related. The system determines the bank size, which means the system also determines a boundary for the code/data used to update a particular bank. If updating a bank of size X requires accessing code/data of size Y in the package, then the boundary corresponds to size Y.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183
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