Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgement is made to Applicant’s claim of priority to Chinese application CN202210913726.9, filed August 1, 2022.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 20, 2026 is being considered by the examiner.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed January 25, 2026. Claims 1, 4, 5, 7, 8, 10, 12, 15, and 20 are amended. The Examiner notes that claims 1-10 and 12-20 are examined.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 and 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Li (CN 107731858 A) in view of Sekine (US 2016/0293659 A1) and Osawa (US 2015/0055051 A1).
With respect to claim 1, Li teaches in Fig. 2:
A semiconductor device, comprising:
an insulating substrate (first insulating layer 16);
a first integrated circuit (IC) directly disposed on and being in contact with the insulating substrate (16) and comprising a first thin-film transistor (TFT) (silicon film transistor 11),
and a second IC disposed on the insulating substrate (16) and comprising a second TFT (“oxide thin film transistor 12”);
wherein a mobility of charge carriers in an active layer (silicon channel layer 114) of the first TFT (11) is greater than a mobility of charge carriers in an active layer (semiconductor oxide layer 124) of the second TFT (12) (“The transistors requiring higher carrier mobility in the pixel circuit are set as silicon thin film transistors, and the transistors requiring lower carrier mobility can be set as semiconductor oxide thin film transistors.”);
Li fails to teach:
wherein the first IC comprises a gate driving IC, and the second IC comprises an operational amplifier IC.
wherein a bottom surface of the first TFT is in direct contact with a top surface of the insulating substrate;
Sekine teaches in Fig. 9-10:
wherein the first IC comprises a gate driving IC (gate drive circuit 930), and the second IC comprises an operational amplifier IC (signal readout circuit 920, which is shown in Fig. 10 to comprise operational amplifier 921).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Sekine into the device of Li such that the first IC is a gate driver and the second IC comprises an operational amplifier. The ordinary artisan would have been motivated to modify Li in the manner set forth above for the purpose of providing a mechanism to drive and read an image sensor circuit (para. 78 of Sekine).
Osawa teaches in Fig. 17:
wherein a bottom surface of the first TFT (thin film transistor structure 216 or 240) is in direct contact with a top surface of the insulating substrate (buffer 202, which is made from a dielectric);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Osawa into the device of Li/Sekine such that the bottom surface of the first TFT is in direct contact with the top of the insulating substrate. The ordinary artisan would have been motivated to modify Li in the manner set forth above for the purpose of simplifying the production process by depositing the transistor layer directly on the insulating substrate.
With respect to claim 6, Li teaches all limitations of claim 1 upon which claim 6 depends. Li further teaches:
wherein the first TFT (silicon film transistor 11 of Li) comprises a low-temperature polycrystalline silicon TFT (para. 64 of Li, “the silicon channel layer may be polysilicon formed by low-temperature directional deposition, also known as low-temperature polysilicon,”)
and the second TFT comprises a metal oxide TFT (oxide thin film transistor 12 of Li);
wherein the active layer (114) of the first TFT (11) is disposed on the insulating substrate (disposed on bottom of 16), a gate (111) of the first TFT (11) is insulatedly disposed (separated by first insulating layer 16) on the active layer (114) of the first TFT (11),
Osawa further teaches:
a gate (metal structure 228) of the first TFT (240) and a gate (metal structure 218) of the second TFT (216) are disposed on a same level
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Li in view of Sekine and Osawa as explained above.
With respect to claim 7, Li further teaches:
comprising a gate insulating layer (14) disposed on the gate (111) of the first TFT (11) and the gate (14 disposed on bottom side of 121) of the second TFT (12),
wherein the active layer (124) of the second TFT (12) is disposed on the gate insulating layer (disposed on bottom side of 14), the source or drain metal layer (112 and 113) of the first TFT (11) and the source or drain metal layer (125 and 126) of the second TFT (12) are disposed on a same layer (15) and are disposed (indirectly) on the gate insulating layer (14).
With respect to claim 8, Li further teaches:
wherein the source or drain metal layer (125 and 126) of the second TFT (12) is at least partly disposed (disposed through the ohmic contact layers 122 and 123) of the active layer (124) of the second TFT (12), and is electrically connected to the active layer of the second TFT (connected through the ohmic contacts 122 and 123).
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Li (CN 107731858 A), Sekine (US 2016/0293659 A1) and Osawa (US 2015/0055051 A1) as applied to independent claim 1 above and in view of Mizutani (Journal of the Electron Devices Society, 2021).
With respect to claim 2, Li/Sekine/Osawa teaches all limitations of the independent claim 1 upon which claim 2 depends. Li/Sekine/Osawa is silent to:
wherein along a length direction of a channel area corresponding to the first TFT and the second TFT, an average size of a plurality of grains in the active layer of the first TFT is greater than an average size of a plurality of grains in the active layer of the second TFT.
Mizutani teaches in the conclusion:
“It was also experimentally verified that the larger the grain size, the higher the field-effect mobility”
The Examiner takes the position that Mizutani teaches that increasing the grain size of a low-temperature polycrystalline (LTPS) thin-film transistor (TFT) is known to increase mobility of charge characters. Therefore, by incorporating the teachings of Mizutani into Li to make the first and second transistor out of LTPS of different grain sizes,
Li/Sekine/Osawa/Mizutani teaches:
wherein along a length direction (left/right) of a channel area (114 and 124 of Li) corresponding to the first TFT (11 of Li) and the second TFT (12 of Li), an average size of a plurality of grains in the active layer of the first TFT is greater than an average size of a plurality of grains in the active layer of the second TFT (Li teaches that 11 has higher mobility than 12, Mizutani teaches that this can be achieved by making the channel area from LTPS with a larger grain size in 11 than 12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Mizutani into the device of Li/Sekine/Osawa to make the channel area of the first TFT of larger particles than the channel area of the second TFT. The ordinary artisan would have been motivated to modify Li/Sekine/Osawa in the manner set forth above for the purpose tuning the mobilities of the TFTs though grain size (conclusion of Mizutani) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
With respect to claim 3, Li further teaches:
wherein the grains in the active layer of the first TFT (11) comprise a first boundary (edges of 114) along the first direction (left/right) and a second boundary (top and bottom surfaces of 114) along the second direction (up/down);
and wherein the first direction is same as the length direction (left/right) of the channel area (114), the second direction is perpendicular to the length direction (up/down) of the channel area (114), and a length of the first boundary is greater than a length of the second boundary (Fig. 2, 114’s length is greater than the thickness).
With respect to claim 4, Li/Sekine/Osawa/Mizutani teach all limitations of claim 2 upon which claim 4 depends. Li/Mizutani further teaches:
wherein the active layer (114) of the first TFT (11 of Li) and the active layer (124) of the second TFT (12) have a same material (Mizutani teaches uses LTPS of different grain sizes for the TFTs of different mobilities of Li)
and a source or drain metal layer (first source and drain electrode layers 112 and 113) of the first TFT (11) and a source or drain metal layer (second source and drain electrode layers 125 and 126) of the second TFT (12) are disposed on a same level (top of 112, 113, 125, and 126 are disposed on interlayer dielectric layer 15).
Osawa further teaches:
the active layer (semiconducting oxide layer 224) of the first TFT (240) and the active layer (polysilicon layer 204) of the second TFT are disposed on a same level, a gate (metal structure 228) of the first TFT (240) and a gate (metal structure 218) of the second TFT (216) are disposed on a same level
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Li in view of Sekine, Osawa, and Mizutani as explained above.
Claims 5, 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Li (CN 107731858 A), Sekine (US 2016/0293659 A1), Osawa (US 2015/0055051 A1) and Mizutani (Journal of the Electron Devices Society, 2021) as applied to claim 2 above and further in view of Ma (Journal of the Electron Devices Society, 2020).
With respect to claim 5, Li/Sekine/Osawa/Mizutani teach all limitations of claim 2 upon which claim 5 depends. Li/Sekine/Osawa/Mizutani further teach:
wherein a gate (111) of the first TFT (11) is insulatedly disposed (through first insulating layer 16) on the active layer (114) of the first TFT (11),
a source or drain metal layer (112 and 113) of the first TFT (11) is insulatedly disposed (separated by second insulating layer 14) on the gate (111) of the first TFT (11),
and a gate (121) of the second TFT (12) is insulatedly disposed (separated by second insulating layer 14) on the active layer (124) of the second TFT (12).
Li/Sekine/Osawa/Mizutani fail to teach:
the active layer of the second TFT is insulatedly disposed on the source or drain metal layer of the first TFT,
Ma teaches in Fig. 1(e)
the active layer (top channel) of the second TFT (3rd TFT in annotated Fig. 1(e) below) is insulatedly disposed (separated by OX-3) on the source or drain metal layer (Raised source/drain RS/D) of the first TFT (first TFT),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Ma into the device of Li/Sekine/Osawa/Mizutani to dispose the active layer of the second TFT on the source or drain metal layer of the first TFT. The ordinary artisan would have been motivated to modify Li/Sekine/Osawa/Mizutani in the manner set forth above for the purpose forming monolithic 3D-IC structures (conclusion of Ma).
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With respect to claim 9, Li further teaches:
wherein the first TFT is a low-temperature polycrystalline silicon TFT (11 is a silicon TFT, “the silicon channel layer may be polysilicon formed by deposition in a low temperature direction, which is also called low temperature polysilicon”) and the second TFT is a metal oxide TFT (12 is a semiconductor oxide TFT, “The semiconductor oxide layer may be a semiconductor oxide such as indium gallium zinc oxide (IGZO)”, IGZO is a metal oxide)
Li/Sekine/Osawa/Mizutani fail to teach:
the second TFT is disposed on the first TFT, and the semiconductor device comprises a passivation layer disposed between the first TFT and the second TFT.
Ma teaches in Fig. 1(e):
the second TFT (3rd TFT in annotated Fig. 1e above) is disposed on the first TFT (1st TFT in annotated Fig. 1e above), and the semiconductor device comprises a passivation layer (OX-3) disposed between the first TFT and the second TFT.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Ma into the device of Li/Sekine/Osawa/Mizutani to dispose the second TFT on the first TFT. The ordinary artisan would have been motivated to modify Li/Sekine/Osawa/Mizutani in the manner set forth above for the purpose forming monolithic 3D-IC structures (conclusion of Ma).
With respect to claim 10, Ma further teaches:
wherein the semiconductor device comprises a second gate insulating layer (OX-4), a gate of the second TFT (Poly-Si gate of 3rd TFT) is disposed on the passivation layer (OX-3), the second gate insulating layer (OX-4) is disposed on the passivation layer (OX-3), the active layer of the second TFT (top channel of 3rd TFT) is disposed on the second gate insulating layer (disposed on bottom side of OX-4), and the source or drain metal layer (RS/D of 3rd TFT) of the second TFT is disposed on the second gate insulating layer (disposed on bottom of OX-4); and wherein the source or drain metal layer (RS/D of 3rd TFT) of the second TFT is at least partly disposed on a surface of the active layer of the second TFT (disposed on side surface of top channel layer of 3rd TFT), and is electrically connected to the active layer of the second TFT (RS/D and top channel layer are touching).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Li in view of Sekine, Osawa, Mizutani, and Ma as explained above.
Claims 12-14, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Guo (CN 110137203 A) in view of Li (CN 107731858 A) and Sekine (US 2016/0293659 A1)
With respect to claim 12, Guo teaches in Fig. 1 and 3:
A sensor device, comprising a sensor area (pixel matrix 300) and an outer circuit area defined on a side of the sensor area (scan driving circuit 310, and data readout circuit 320);
wherein the sensor device comprises: an insulating substrate (buffer layer 101);
a sensor unit disposed on the insulating substrate corresponding to the sensor area (electrode 118 treated to comprise a target detection substance);
and an integrated circuit (IC) (first transistor 11), wherein the IC is at least partly disposed on the insulating substrate (first transistor 11 on substrate 101) corresponding to the outer circuit area, and is configured to control the sensor unit (para. 122, “first transistor is used as a switching transistor”);
wherein the IC comprises: a first IC (transistor 11) directly disposed on and being in contact with the insulating substrate and comprising a first thin-film transistor (TFT), wherein a bottom surface of the first TFT (11) is in direct contact with a top surface of the insulating substrate (101); and a second IC disposed on the insulating substrate and comprising a second TFT (second transistor 12);
Guo fails to teach:
wherein a mobility of charge carriers in an active layer of the first TFT is greater than a mobility of charge carriers in an active layer of the second TFT.
wherein the first IC comprises a gate driving IC, and the second IC comprises an operational amplifier IC.
Li teaches in Fig. 2:
wherein a mobility of a charge carriers in an active layer (silicon channel layer 114) of the first TFT (11) is greater than a mobility of charge carriers in an active layer (semiconductor oxide layer 124) of the second TFT (12) (“The transistors requiring higher carrier mobility in the pixel circuit are set as silicon thin film transistors, and the transistors requiring lower carrier mobility can be set as semiconductor oxide thin film transistors.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Li into the device of Guo to include a first TFT with an active layer of greater mobility that the active layer of a second TFT. The ordinary artisan would have been motivated to modify Guo in the manner set forth above for the purpose of improving the switching characteristics of the switch thin film transistor without having a negative impact on the display (para. 5 of Li).
Sekine teaches in Fig. 9-10:
wherein the first IC comprises a gate driving IC (gate drive circuit 930),
and the second IC comprises an operational amplifier IC (signal readout circuit 920, which is shown in Fig. 10 to comprise operational amplifier 921).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Sekine into the device of Guo/Li such that the first IC is a gate driver and the second IC comprises an operational amplifier. The ordinary artisan would have been motivated to modify Guo/Li in the manner set forth above for the purpose of providing a mechanism to drive and read an image sensor circuit (para. 78 of Sekine).
With respect to claim 13, Guo further teaches:
wherein in the sensor area, the sensor device comprises: a plurality of gate signal lines (see annotated Fig. 3 below); and a plurality of data signal lines (see annotated Fig. 3), wherein the data signal lines and the gate signal lines cross each other and form a plurality of intersection areas, each of the intersection areas is provided with at least one sensor unit (electrode 118 that acts as a target detector and makes up the pixel sensor structure, para. 85, Fig. 3, “The sensor device includes a plurality of pixel sensor structures arranged in an array”, only one sensor device is shown), and the sensor unit comprises a first sensor module (transistors 11 and 12); wherein the data signal lines are electrically connected to the first sensor module, and the data signal lines are electrically connected to the IC disposed in the outer circuit area (see annotated Fig. 3).
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With respect to claim 14, Guo further teaches:
wherein the data signal lines are electrically connected to the first IC (first transistor 11), the second IC (second transistor 12) is electrically connected to the first IC (11), and the first IC is electrically connected between the sensor unit (electrode 118 treated to be a detector) and the second IC (12).
With respect to claim 18, Guo further teaches:
wherein the first IC (IC comprising transistor 11) and the second IC (IC comprising transistor 12) are both disposed on a same side of the insulating substrate (100), the first sensor module (sensor electrode 118) is disposed on a side of the first IC away from the insulating substrate (Fig. 1), and the first sensor module is electrically connected to the first TFT (connected through transistor 12 and drain metal layer 113).
With respect to claim 20, Guo teaches in Fig. 1:
An electronic device, comprising a semiconductor device;
wherein the semiconductor device comprises:
an insulating substrate (buffer layer 101);
a first integrated circuit (IC) directly disposed on and being in contact with the insulating substrate and comprising a first thin-film transistor (TFT) (transistor 11), wherein a bottom surface of the first TFT (11) is in direct contact with a top surface of the insulating substrate (101);
and a second IC disposed on the insulating substrate and comprising a second TFT (transistor 12);
or wherein the electronic device comprises a sensor device comprising a sensor area (pixel matrix 300) and an outer circuit area defined on a side of the sensor area (scan driving circuit 310, and data readout circuit 320);
wherein the sensor device comprises: an insulating substrate (substrate 100);
a sensor unit disposed on the insulating substrate corresponding to a sensor area (electrode 118 treated to comprise a target detection substance);
and an integrated circuit (IC) (first transistor 11), wherein the IC is at least partly disposed on the insulating substrate (first transistor 11 on substrate 100) corresponding to the outer circuit area, and is configured to control the sensor unit (para. 122, “first transistor is used as a switching transistor”);
wherein the IC comprises: a first IC (transistor 11) directly disposed on the insulating substrate and comprising a first thin-film transistor (TFT), wherein a bottom surface of the first TFT (11) is in direct contact with a top surface of the insulating substrate (101); and a second IC disposed on the insulating substrate and comprising a second TFT (second transistor 12);
Guo fails to teach:
wherein a mobility of charge carriers in an active layer of the first TFT is greater than a mobility of a charge carriers in an active layer of the second TFT.
wherein the first IC comprises a gate driving IC, and the second IC comprises an operational amplifier IC.
Li teaches in Fig. 2:
wherein mobility of a charge carrier in an active layer (silicon channel layer 114) of the first TFT (11) is greater than mobility of a charge carrier in an active layer (semiconductor oxide layer 124) of the second TFT (12) (“The transistors requiring higher carrier mobility in the pixel circuit are set as silicon thin film transistors, and the transistors requiring lower carrier mobility can be set as semiconductor oxide thin film transistors.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Li into the device of Guo to include a first TFT with an active layer of greater mobility that the active layer of a second TFT. The ordinary artisan would have been motivated to modify Guo in the manner set forth above for the purpose of improving the switching characteristics of the switch thin film transistor without having a negative impact on the display (para. 5 of Li).
Sekine teaches in Fig. 9-10:
wherein the first IC comprises a gate driving IC (gate drive circuit 930),
and the second IC comprises an operational amplifier IC (signal readout circuit 920, which is shown in Fig. 10 to comprise operational amplifier 921).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Sekine into the device of Guo/Li such that the first IC is a gate driver and the second IC comprises an operational amplifier. The ordinary artisan would have been motivated to modify Guo/Li in the manner set forth above for the purpose of providing a mechanism to drive and read an image sensor circuit (para. 78 of Sekine).
Claims 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Guo (CN 110137203 A) in view of Li (CN 107731858 A) and Sekine (US 2016/0293659 A1) as applied to claim 14 above and further in view of Yakubo (US 2022/0199653 A1).
With respect to claim 15, Guo/Li/Sekine further teaches:
the second IC comprises at least one of a memory IC or an operational amplifier IC (signal readout circuit 920 (Fig. 9 of Sekine) includes operational amplifier 921 (Fig. 10 of Sekine)).
Guo/Li/Sekine fails to teach:
the first IC comprises at least one of a low-pass control IC, an analog control IC, or a digital-to-analog converter IC,
Yakubo teaches in Fig. 6-7:
the first IC (13) comprises at least one of a low-pass control IC (low pass filter 103), an analog control IC (control circuit 24), or a digital-to-analog converter IC (digital-to-analog conversion circuit 107), and the second IC (memory 14) comprises at least one of a memory IC (memory 14) or an operational amplifier IC.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Yakubo into the device of Guo/Li/Sekine to include a low pass control IC, an analog control IC, a digital-to-analog converter IC, and a memory IC. The ordinary artisan would have been motivated to modify Guo/Li/Sekine in the manner set forth above for the purpose of converting an input signal to an output signal (para. 90-91 of Yakubo) and/or because the use of low pass control, analog control, digital to analog converters, and memory ICs are well known methods for controlling semiconductor devices.
With respect to claim 16, Guo/Li/Sekine fail to teach:
wherein the first IC comprises a low-pass control IC electrically connected to the data signal lines, an analog control IC electrically connected to the low-pass control IC, and a digital-to-analog converter IC electrically connected to the analog control IC, the second IC comprises a memory IC, the low-pass control IC is electrically connected between the sensor unit and the analog control IC, and the digital-to-analog converter IC is electrically connected between the analog control IC and the memory IC.
Yakubo teaches:
wherein the first IC comprises a low-pass control IC (low pass filter 103, Fig. 7) electrically connected to the data signal lines, an analog control IC (control circuit 24, Fig. 7) electrically connected to the low-pass control IC (103), and a digital-to-analog converter IC (digital-to-analog control circuit 107, Fig. 7) electrically connected to the analog control IC (24), the second IC comprises a memory IC (memory 14, Fig. 6), the low-pass control IC is electrically connected between the sensor unit (semiconductor device 23, Fig. 7, para. 2 semiconductor device can include a sensor device) and the analog control IC, and the digital-to-analog converter IC is electrically connected between the analog control IC and the memory IC (Fig.7).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Yakubo into the device of Guo/Li/Sekine to include a low pass control IC, an analog control IC, a digital-to-analog converter IC, and a memory IC electrically connected to the semiconductor device. The ordinary artisan would have been motivated to modify Guo/Li/Sekine in the manner set forth above for the purpose of converting an input signal to an output signal (para. 90-91 of Yakubo) and/or because the use of low pass control, analog control, digital to analog converters, and memory ICs are well known methods for controlling semiconductor devices.
With respect to claim 17, Li further teaches:
wherein the active layer of the first TFT comprises a low-temperature polycrystalline silicon (para. 64, “the silicon channel layer may be polysilicon formed by low-temperature directional deposition, also known as low-temperature polysilicon,”), and the active layer of the second TFT comprises a metal oxide (oxide thin film transistor 12).
Claims 19 is rejected under 35 U.S.C. 103 as being unpatentable over Guo (CN 110137203 A) in view of Li (CN 107731858 A) and Sekine (US 2016/0293659 A1) as applied to claim 14 above and further in view of Tanaka (US 2021/0013245 A1).
With respect to claim 19, Guo/Li/Sekine teach all limitations of claim 14 upon which claim 19 depends. Guo/Li/Sekine fail to teach:
wherein the first IC and the second IC are both disposed on a first surface of the insulating substrate, and the first sensor module is disposed on a second surface of the insulating substrate opposite to the first surface; and wherein the first sensor module is electrically connected to the first TFT by a through- hole defined on the insulating substrate.
Tanaka teaches in Fig. 2:
wherein the first IC (first oxide semiconductor TFT 170) and the second IC (second oxide semiconductor TFT 130) are both disposed on a first (bottom) surface of the insulating substrate (insulating layer 121), and the first sensor module (pixel electrode 181) is disposed on a second (top) surface of the insulating substrate (121) opposite to the first (bottom) surface; and wherein the first sensor module (181) is electrically connected to the first TFT (170) by a through- hole defined on the insulating substrate (Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Tanaka into the device of Guo/Li/Sekine to put a sensor module on a surface of a substrate opposite two TFTs and connect the sensor to the TFT with a through-hole. The ordinary artisan would have been motivated to modify Guo/Li/Sekine in the manner set forth above for the purpose of “fabricating oxide semiconductor TFTs including oxide semiconductor films having different characteristics (made of different materials) on the same substrate.” (para. 67 of Tanaka)
Response to Arguments
Applicant’s arguments with respect to claims 1-10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments with respect to claims 12 and 20 filed January 25, 2026 have been fully considered but they are not persuasive.
The Examiner has changed the mapping such that layer 101 is the insulating substrate. Applicant argues that “Guo fails to disclose whether the interlayer 101 is insulating.” Guo teaches “chemical vapour deposition technology to deposit silicon nitride or silicon oxide film on the surface of the substrate 100 to form a buffer layer 101” (see para. 96 of the machine translation of Guo included in Office Action dated February 12, 2025.) The Examiner notes that silicon nitride and silicon oxide are known to be insulating dielectrics. The argument is therefore found unpersuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
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/A.M.W./ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897
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