Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on July 2, 2026 has been entered.
Priority
Acknowledgement is made to Applicant’s claim of priority to Chinese application CN202210913726.9, filed August 1, 2022.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed July 2, 2026. Claims 1, 6, 12, and 20 are amended. Claims 4-5 and 7-11 are cancelled. Claim 21 is newly added. The Examiner notes that claims 1-3, 6, and 12-21 are examined.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
A broad range or limitation together with a narrow range or limitation that falls within the broad range or limitation (in the same claim) may be considered indefinite if the resulting claim does not clearly set forth the metes and bounds of the patent protection desired. See MPEP § 2173.05(c). In the present instance, claim 6 recites the broad recitation “wherein the first TFT comprises a low-temperature polycrystalline silicon TFT, and the second TFT comprises a metal oxide TFT” and independent claim 1 upon which claim 6 depends also recites “wherein the first TFT is a low-temperature polycrystalline silicon TFT, and the second TFT is a metal oxide TFT”, which is the narrower statement of the range/limitation. The claim(s) are considered indefinite because there is a question or doubt as to whether the feature introduced by such narrower language is (a) merely exemplary of the remainder of the claim, and therefore not required, or (b) a required feature of the claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over He (US 2021/0327924 A1) in view of Sekine (US 2016/0293659 A1) and Lin (US 2021/0091122 A1).
With respect to claim 1, He teaches in Fig. 8:
A semiconductor device, comprising:
an insulating substrate (base substrate 10 “may include a polyimide substrate to ensure that the flexible substrate has good high temperature resistance and good insulation performance” [0071]);
a first integrated circuit (IC) directly disposed on and being in contact with the insulating substrate (10) and comprising a first thin-film transistor (TFT) (first transistor 20),
wherein a bottom surface of the first TFT (bottom surface of active layer 21) is in direct contact with a top surface of the insulating substrate (10, see Fig. 8);
and a second IC disposed on the insulating substrate (10) and comprising a second TFT (second transistor 30);
wherein a mobility of charge carriers in an active layer (first active layer 21) of the first TFT (20) is greater than a mobility of charge carriers in an active layer (second active layer 31) of the second TFT (30)([0061] “the first active layer 21 is a poly-silicon active layer such as a low temperature poly-silicon (LTPS) active layer. The second active layer 31 in the second transistor 30 includes an oxide semiconductor” “The LTPS thin-film transistor has the advantages of high carrier mobility,”);
wherein the first TFT (20) is a low-temperature polycrystalline silicon TFT ([0061] “the first active layer 21 is a poly-silicon active layer such as a low temperature poly-silicon (LTPS) active layer”) and the second TFT is a metal oxide TFT ([0061] “the second transistor 30 includes an oxide semiconductor”);
and the semiconductor device comprises a passivation layer (see annotated Fig. 8 below) disposed between the first TFT (first transistor 20) and the second TFT (second transistor 30);
wherein the semiconductor device comprises a second gate insulating layer (first insulating layer 40), a gate of the second TFT (second gate 32) has a bottom surface in direct contact with a top surface of the passivation layer (see Fig. 8),
the second gate insulating layer (40) is disposed on the passivation layer (see annotated Fig. 8), the active layer of the second TFT (second active layer 31) is disposed on the second gate insulating layer (40),
and wherein the source or drain metal layer (second source 33 and second drain 34) of the second TFT (30) is at least partly disposed on a surface of the active layer of the second TFT (31), and is electrically connected to the active layer of the second TFT
Li fails to teach:
wherein the first IC comprises a gate driving IC, and the second IC comprises an operational amplifier IC.
Sekine teaches in Fig. 9-10:
wherein the first IC comprises a gate driving IC (gate drive circuit 930), and the second IC comprises an operational amplifier IC (signal readout circuit 920, which is shown in Fig. 10 to comprise operational amplifier 921).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Sekine into the device of He such that the first IC is a gate driver and the second IC comprises an operational amplifier. The ordinary artisan would have been motivated to modify Li in the manner set forth above for the purpose of providing a mechanism to drive and read an image sensor circuit (para. 78 of Sekine).
Lin teaches in Fig. 1:
and a bottom surface of a source or drain metal layer (second source 452 and second drain 453) of the second TFT is in direct contact with a top surface of the second gate insulating layer (gate insulating layer 420);
Claim 1 is rejected under the rationale “Simple Substitution of One Known Element for Another To Obtain Predictable Results”. The Graham factual inquiries of this rationale are:
(1) a finding that the prior art contained a device (method, product, etc.) which differed from the claimed device by the substitution of some components (step, element, etc.) with other components;
(2) a finding that the substituted components and their functions were known in the art;
(3) a finding that one of ordinary skill in the art could have substituted one known element for another, and the results of the substitution would have been predictable; and
(4) whatever additional findings based on the Graham factual inquiries may be necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness.
He includes a device that differs from the claimed invention in that the metal source drain contact the top of the active layer and do not directly contact the gate insulation layer. Lin teaches a similar device in which the metal source and drain has a shape that contacts the gate insulation layer as well as the active layer of the TFT as claimed. One of ordinary skill in the art would have been able to substitute the metal source and drain of Lin for the metal source and drain in the second transistor of He with the predictable result of the source and drain working the same in both devices.
With respect to claim 6, He further teaches:
wherein the first TFT comprises a low-temperature polycrystalline silicon TFT, and the second TFT comprises a metal oxide TFT ([0061] “the first active layer 21 is a poly-silicon active layer such as a low temperature poly-silicon (LTPS) active layer. The second active layer 31 in the second transistor 30 includes an oxide semiconductor” “The LTPS thin-film transistor has the advantages of high carrier mobility,”);
wherein the active layer (21) of the first TFT is disposed on the insulating substrate (10)
Claims 2-3 is rejected under 35 U.S.C. 103 as being unpatentable over He (US 2021/0327924 A1) in view of Sekine (US 2016/0293659 A1) and Lin (US 2021/0091122 A1) as applied to independent claim 1 above and in view of Mizutani (Journal of the Electron Devices Society, 2021).
With respect to claim 2, He/Sekine/Lin teaches all limitations of the independent claim 1 upon which claim 2 depends. He/Sekine/Lin is silent to:
wherein along a length direction of a channel area corresponding to the first TFT and the second TFT, an average size of a plurality of grains in the active layer of the first TFT is greater than an average size of a plurality of grains in the active layer of the second TFT.
Mizutani teaches in the conclusion:
“It was also experimentally verified that the larger the grain size, the higher the field-effect mobility”
The Examiner takes the position that Mizutani teaches that increasing the grain size of a low-temperature polycrystalline (LTPS) thin-film transistor (TFT) is known to increase mobility of charge characters. Therefore, by incorporating the teachings of Mizutani into Li to make the first and second transistor out of LTPS of different grain sizes,
He/Sekine/Lin/Mizutani teaches:
wherein along a length direction (left/right) of a channel area (114 and 124 of Li) corresponding to the first TFT (11 of Li) and the second TFT (12 of Li), an average size of a plurality of grains in the active layer of the first TFT is greater than an average size of a plurality of grains in the active layer of the second TFT (Li teaches that 11 has higher mobility than 12, Mizutani teaches that this can be achieved by making the channel area from LTPS with a larger grain size in 11 than 12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Mizutani into the device of He/Sekine/Lin to make the channel area of the first TFT of larger particles than the channel area of the second TFT. The ordinary artisan would have been motivated to modify He/Sekine/Lin in the manner set forth above for the purpose tuning the mobilities of the TFTs though grain size (conclusion of Mizutani) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
With respect to claim 3, He further teaches:
wherein the grains in the active layer of the first TFT (20) comprise a first boundary (edges of 21) along the first direction (left/right) and a second boundary (top and bottom surfaces of 21) along the second direction (up/down);
and wherein the first direction is same as the length direction (left/right) of the channel area (21), the second direction is perpendicular to the length direction (up/down) of the channel area (21), and a length of the first boundary is greater than a length of the second boundary (Fig. 8, 21’s length is greater than the thickness).
Claims 12-14, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Guo (CN 110137203 A) in view of He (US 2021/0327924 A1), Sekine (US 2016/0293659 A1) and Lin (US 2021/0091122 A1).
With respect to claim 12, Guo teaches in Fig. 1 and 3:
A sensor device, comprising a sensor area (pixel matrix 300) and an outer circuit area defined on a side of the sensor area (scan driving circuit 310, and data readout circuit 320);
wherein the sensor device comprises: an insulating substrate (buffer layer 101);
a sensor unit disposed on the insulating substrate corresponding to the sensor area (electrode 118 treated to comprise a target detection substance);
and an integrated circuit (IC) (first transistor 11), wherein the IC is at least partly disposed on the insulating substrate (first transistor 11 on substrate 101) corresponding to the outer circuit area, and is configured to control the sensor unit (para. 122, “first transistor is used as a switching transistor”);
wherein the IC comprises: a first IC (transistor 11) directly disposed on and being in contact with the insulating substrate and comprising a first thin-film transistor (TFT), wherein a bottom surface of the first TFT (11) is in direct contact with a top surface of the insulating substrate (101); and a second IC disposed on the insulating substrate and comprising a second TFT (second transistor 12);
Guo fails to teach:
wherein a mobility of charge carriers in an active layer of the first TFT is greater than a mobility of charge carriers in an active layer of the second TFT.
wherein the first IC comprises a gate driving IC, and the second IC comprises an operational amplifier IC.
wherein the first TFT is a low-temperature polycrystalline silicon TFT,
and the second TFT is a metal oxide TFT,
the second TFT is disposed on the first TFT, and the semiconductor device comprises a passivation layer disposed between the first TFT and the second TFT;
wherein the semiconductor device comprises a second gate insulating layer, a gate of the second TFT has a bottom surface in direct contact with a top surface of the passivation layer, the second gate insulating layer is disposed on the passivation layer,
the active layer of the second TFT is disposed on the second gate insulating layer, and a bottom surface of a source or drain metal layer of the second TFT is in direct contact with a top surface of the second gate insulating layer;
and wherein the source or drain metal layer of the second TFT is at least partly disposed on a surface of the active layer of the second TFT, and is electrically connected to the active layer of the second TFT.
He teaches in Fig. 8:
wherein a mobility of charge carriers in an active layer (first active layer 21) of the first TFT (20) is greater than a mobility of charge carriers in an active layer (second active layer 31) of the second TFT (30)([0061] “the first active layer 21 is a poly-silicon active layer such as a low temperature poly-silicon (LTPS) active layer. The second active layer 31 in the second transistor 30 includes an oxide semiconductor” “The LTPS thin-film transistor has the advantages of high carrier mobility,”);
wherein the first TFT (20) is a low-temperature polycrystalline silicon TFT ([0061] “the first active layer 21 is a poly-silicon active layer such as a low temperature poly-silicon (LTPS) active layer”) and the second TFT is a metal oxide TFT ([0061] “the second transistor 30 includes an oxide semiconductor”);
and the semiconductor device comprises a passivation layer (see annotated Fig. 8 below) disposed between the first TFT (first transistor 20) and the second TFT (second transistor 30);
wherein the semiconductor device comprises a second gate insulating layer (first insulating layer 40), a gate of the second TFT (second gate 32) has a bottom surface in direct contact with a top surface of the passivation layer (see Fig. 8),
the second gate insulating layer (40) is disposed on the passivation layer (see annotated Fig. 8), the active layer of the second TFT (second active layer 31) is disposed on the second gate insulating layer (40),
and wherein the source or drain metal layer (second source 33 and second drain 34) of the second TFT (30) is at least partly disposed on a surface of the active layer of the second TFT (31), and is electrically connected to the active layer of the second TFT
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Li into the device of Guo to include a first TFT with an active layer of greater mobility that the active layer of a second TFT and for the second TFT to be stacked on the first TFT with the claimed features. The ordinary artisan would have been motivated to modify Guo in the manner set forth above for the purpose of creating a driver circuit with a stable second transistor ([0075] of He) and for the purpose of creating a drive circuit with fast switching form the LTPS while the overall leakage current in the circuit is low because of the oxide TFT [0027].
Sekine teaches in Fig. 9-10:
wherein the first IC comprises a gate driving IC (gate drive circuit 930),
and the second IC comprises an operational amplifier IC (signal readout circuit 920, which is shown in Fig. 10 to comprise operational amplifier 921).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Sekine into the device of Guo/He such that the first IC is a gate driver and the second IC comprises an operational amplifier. The ordinary artisan would have been motivated to modify Guo/He in the manner set forth above for the purpose of providing a mechanism to drive and read an image sensor circuit (para. 78 of Sekine).
Lin teaches in Fig. 1:
and a bottom surface of a source or drain metal layer (second source 452 and second drain 453) of the second TFT is in direct contact with a top surface of the second gate insulating layer (gate insulating layer 420);
Claim 12 is rejected under the rationale “Simple Substitution of One Known Element for Another To Obtain Predictable Results”. The Graham factual inquiries of this rationale are:
(1) a finding that the prior art contained a device (method, product, etc.) which differed from the claimed device by the substitution of some components (step, element, etc.) with other components;
(2) a finding that the substituted components and their functions were known in the art;
(3) a finding that one of ordinary skill in the art could have substituted one known element for another, and the results of the substitution would have been predictable; and
(4) whatever additional findings based on the Graham factual inquiries may be necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness.
Guo modified by He and Sekine includes a device that differs from the claimed invention in that the metal source drain contact the top of the active layer and do not directly contact the gate insulation layer. Lin teaches a similar device in which the metal source and drain has a shape that contacts the gate insulation layer as well as the active layer of the TFT as claimed. One of ordinary skill in the art would have been able to substitute the metal source and drain of Lin for the metal source and drain in the second transistor of He with the predictable result of the source and drain working the same in both devices.
With respect to claim 13, Guo further teaches:
wherein in the sensor area, the sensor device comprises: a plurality of gate signal lines (see annotated Fig. 3 below); and a plurality of data signal lines (see annotated Fig. 3), wherein the data signal lines and the gate signal lines cross each other and form a plurality of intersection areas, each of the intersection areas is provided with at least one sensor unit (electrode 118 that acts as a target detector and makes up the pixel sensor structure, para. 85, Fig. 3, “The sensor device includes a plurality of pixel sensor structures arranged in an array”, only one sensor device is shown), and the sensor unit comprises a first sensor module (transistors 11 and 12); wherein the data signal lines are electrically connected to the first sensor module, and the data signal lines are electrically connected to the IC disposed in the outer circuit area (see annotated Fig. 3).
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With respect to claim 14, Guo further teaches:
wherein the data signal lines are electrically connected to the first IC (first transistor 11), the second IC (second transistor 12) is electrically connected to the first IC (11), and the first IC is electrically connected between the sensor unit (electrode 118 treated to be a detector) and the second IC (12).
With respect to claim 18, Guo further teaches:
wherein the first IC (IC comprising transistor 11) and the second IC (IC comprising transistor 12) are both disposed on a same side of the insulating substrate (100), the first sensor module (sensor electrode 118) is disposed on a side of the first IC away from the insulating substrate (Fig. 1), and the first sensor module is electrically connected to the first TFT (connected through transistor 12 and drain metal layer 113).
With respect to claim 20, Guo teaches in Fig. 1:
An electronic device, comprising a semiconductor device;
wherein the semiconductor device comprises:
an insulating substrate (buffer layer 101);
a first integrated circuit (IC) directly disposed on and being in contact with the insulating substrate and comprising a first thin-film transistor (TFT) (transistor 11), wherein a bottom surface of the first TFT 11) is in direct contact with a top surface of the insulating substrate (101);
and a second IC disposed on the insulating substrate and comprising a second TFT (transistor 12);
or wherein the electronic device comprises a sensor device comprising a sensor area (pixel matrix 300) and an outer circuit area defined on a side of the sensor area (scan driving circuit 310, and data readout circuit 320);
wherein the sensor device comprises: an insulating substrate (substrate 100);
a sensor unit disposed on the insulating substrate corresponding to a sensor area (electrode 118 treated to comprise a target detection substance);
and an integrated circuit (IC) (first transistor 11), wherein the IC is at least partly disposed on the insulating substrate (first transistor 11 on substrate 100) corresponding to the outer circuit area, and is configured to control the sensor unit (para. 122, “first transistor is used as a switching transistor”);
wherein the IC comprises: a first IC (transistor 11) directly disposed on the insulating substrate and comprising a first thin-film transistor (TFT), wherein a bottom surface of the first TFT (11) is in direct contact with a top surface of the insulating substrate (101); and a second IC disposed on the insulating substrate and comprising a second TFT (second transistor 12);
Guo fails to teach:
wherein a mobility of charge carriers in an active layer of the first TFT is greater than a mobility of a charge carriers in an active layer of the second TFT.
wherein the first IC comprises a gate driving IC, and the second IC comprises an operational amplifier IC.
wherein the first TFT is a low-temperature polycrystalline silicon TFT,
and the second TFT is a metal oxide TFT,
the second TFT is disposed on the first TFT, and the semiconductor device comprises a passivation layer disposed between the first TFT and the second TFT;
wherein the semiconductor device comprises a second gate insulating layer, a gate of the second TFT has a bottom surface in direct contact with a top surface of the passivation layer, the second gate insulating layer is disposed on the passivation layer,
the active layer of the second TFT is disposed on the second gate insulating layer, and a bottom surface of a source or drain metal layer of the second TFT is in direct contact with a top surface of the second gate insulating layer;
and wherein the source or drain metal layer of the second TFT is at least partly disposed on a surface of the active layer of the second TFT, and is electrically connected to the active layer of the second TFT.
He teaches in Fig. 8:
wherein a mobility of charge carriers in an active layer (first active layer 21) of the first TFT (20) is greater than a mobility of charge carriers in an active layer (second active layer 31) of the second TFT (30)([0061] “the first active layer 21 is a poly-silicon active layer such as a low temperature poly-silicon (LTPS) active layer. The second active layer 31 in the second transistor 30 includes an oxide semiconductor” “The LTPS thin-film transistor has the advantages of high carrier mobility,”);
wherein the first TFT (20) is a low-temperature polycrystalline silicon TFT ([0061] “the first active layer 21 is a poly-silicon active layer such as a low temperature poly-silicon (LTPS) active layer”) and the second TFT is a metal oxide TFT ([0061] “the second transistor 30 includes an oxide semiconductor”);
and the semiconductor device comprises a passivation layer (see annotated Fig. 8 below) disposed between the first TFT (first transistor 20) and the second TFT (second transistor 30);
wherein the semiconductor device comprises a second gate insulating layer (first insulating layer 40), a gate of the second TFT (second gate 32) has a bottom surface in direct contact with a top surface of the passivation layer (see Fig. 8),
the second gate insulating layer (40) is disposed on the passivation layer (see annotated Fig. 8), the active layer of the second TFT (second active layer 31) is disposed on the second gate insulating layer (40),
and wherein the source or drain metal layer (second source 33 and second drain 34) of the second TFT (30) is at least partly disposed on a surface of the active layer of the second TFT (31), and is electrically connected to the active layer of the second TFT
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Li into the device of Guo to include a first TFT with an active layer of greater mobility that the active layer of a second TFT and for the second TFT to be stacked on the first TFT with the claimed features. The ordinary artisan would have been motivated to modify Guo in the manner set forth above for the purpose of creating a driver circuit with a stable second transistor ([0075] of He) and for the purpose of creating a drive circuit with fast switching form the LTPS while the overall leakage current in the circuit is low because of the oxide TFT [0027].
Sekine teaches in Fig. 9-10:
wherein the first IC comprises a gate driving IC (gate drive circuit 930),
and the second IC comprises an operational amplifier IC (signal readout circuit 920, which is shown in Fig. 10 to comprise operational amplifier 921).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Sekine into the device of Guo/He such that the first IC is a gate driver and the second IC comprises an operational amplifier. The ordinary artisan would have been motivated to modify Guo/He in the manner set forth above for the purpose of providing a mechanism to drive and read an image sensor circuit (para. 78 of Sekine).
Lin teaches in Fig. 1:
and a bottom surface of a source or drain metal layer (second source 452 and second drain 453) of the second TFT is in direct contact with a top surface of the second gate insulating layer (gate insulating layer 420);
Claim 20 is rejected under the rationale “Simple Substitution of One Known Element for Another To Obtain Predictable Results”. The Graham factual inquiries of this rationale are:
(1) a finding that the prior art contained a device (method, product, etc.) which differed from the claimed device by the substitution of some components (step, element, etc.) with other components;
(2) a finding that the substituted components and their functions were known in the art;
(3) a finding that one of ordinary skill in the art could have substituted one known element for another, and the results of the substitution would have been predictable; and
(4) whatever additional findings based on the Graham factual inquiries may be necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness.
Guo modified by He and Sekine includes a device that differs from the claimed invention in that the metal source drain contact the top of the active layer and do not directly contact the gate insulation layer. Lin teaches a similar device in which the metal source and drain has a shape that contacts the gate insulation layer as well as the active layer of the TFT as claimed. One of ordinary skill in the art would have been able to substitute the metal source and drain of Lin for the metal source and drain in the second transistor of He with the predictable result of the source and drain working the same in both devices.
With respect to claim 21, He further teaches:
wherein a source or drain metal layer (first source 23 or first drain 24) of the first TFT (20) extends into the passivation layer (see annotated Fig. 8 above).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Guo in view of He, Sekine, and Lin as explained above.
Claims 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Guo (CN 110137203 A) in view of He (US 2021/0327924 A1), Sekine (US 2016/0293659 A1) and Lin (US 2021/0091122 A1) as applied to claim 14 above and further in view of Yakubo (US 2022/0199653 A1).
With respect to claim 15, Guo/He/Sekine/Lin further teaches:
the second IC comprises at least one of a memory IC or an operational amplifier IC (signal readout circuit 920 (Fig. 9 of Sekine) includes operational amplifier 921 (Fig. 10 of Sekine)).
Guo/He/Sekine/Lin fails to teach:
the first IC comprises at least one of a low-pass control IC, an analog control IC, or a digital-to-analog converter IC,
Yakubo teaches in Fig. 6-7:
the first IC (13) comprises at least one of a low-pass control IC (low pass filter 103), an analog control IC (control circuit 24), or a digital-to-analog converter IC (digital-to-analog conversion circuit 107), and the second IC (memory 14) comprises at least one of a memory IC (memory 14) or an operational amplifier IC.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Yakubo into the device of Guo/He/Sekine/Lin to include a low pass control IC, an analog control IC, a digital-to-analog converter IC, and a memory IC. The ordinary artisan would have been motivated to modify Guo/He/Sekine/Lin in the manner set forth above for the purpose of converting an input signal to an output signal (para. 90-91 of Yakubo) and/or because the use of low pass control, analog control, digital to analog converters, and memory ICs are well known methods for controlling semiconductor devices.
With respect to claim 16, Guo/He/Sekine/Lin fails to teach:
wherein the first IC comprises a low-pass control IC electrically connected to the data signal lines, an analog control IC electrically connected to the low-pass control IC, and a digital-to-analog converter IC electrically connected to the analog control IC, the second IC comprises a memory IC, the low-pass control IC is electrically connected between the sensor unit and the analog control IC, and the digital-to-analog converter IC is electrically connected between the analog control IC and the memory IC.
Yakubo teaches:
wherein the first IC comprises a low-pass control IC (low pass filter 103, Fig. 7) electrically connected to the data signal lines, an analog control IC (control circuit 24, Fig. 7) electrically connected to the low-pass control IC (103), and a digital-to-analog converter IC (digital-to-analog control circuit 107, Fig. 7) electrically connected to the analog control IC (24), the second IC comprises a memory IC (memory 14, Fig. 6), the low-pass control IC is electrically connected between the sensor unit (semiconductor device 23, Fig. 7, para. 2 semiconductor device can include a sensor device) and the analog control IC, and the digital-to-analog converter IC is electrically connected between the analog control IC and the memory IC (Fig.7).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Yakubo into the device of Guo/He/Sekine/Lin to include a low pass control IC, an analog control IC, a digital-to-analog converter IC, and a memory IC electrically connected to the semiconductor device. The ordinary artisan would have been motivated to modify Guo/He/Sekine/Lin in the manner set forth above for the purpose of converting an input signal to an output signal (para. 90-91 of Yakubo) and/or because the use of low pass control, analog control, digital to analog converters, and memory ICs are well known methods for controlling semiconductor devices.
With respect to claim 17, He further teaches:
wherein the active layer (21) of the first TFT (20) comprises a low-temperature polycrystalline silicon, and the active layer (31) of the second TFT (30) comprises a metal oxide ([0061] “the first active layer 21 is a poly-silicon active layer such as a low temperature poly-silicon (LTPS) active layer. The second active layer 31 in the second transistor 30 includes an oxide semiconductor” “The LTPS thin-film transistor has the advantages of high carrier mobility,”)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Guo in view of He, Sekine, Lin, and Yakubo as explained above.
Claims 19 is rejected under 35 U.S.C. 103 as being unpatentable over Guo (CN 110137203 A) in view of He (US 2021/0327924 A1), Sekine (US 2016/0293659 A1) and Lin (US 2021/0091122 A1) as applied to claim 14 above and further in view of Tanaka (US 2021/0013245 A1).
With respect to claim 19, Guo/He/Sekine/Lin teach all limitations of claim 14 upon which claim 19 depends. Guo/He/Sekine/Lin fail to teach:
wherein the first IC and the second IC are both disposed on a first surface of the insulating substrate, and the first sensor module is disposed on a second surface of the insulating substrate opposite to the first surface; and wherein the first sensor module is electrically connected to the first TFT by a through- hole defined on the insulating substrate.
Tanaka teaches in Fig. 2:
wherein the first IC (first oxide semiconductor TFT 170) and the second IC (second oxide semiconductor TFT 130) are both disposed on a first (bottom) surface of the insulating substrate (insulating layer 121), and the first sensor module (pixel electrode 181) is disposed on a second (top) surface of the insulating substrate (121) opposite to the first (bottom) surface; and wherein the first sensor module (181) is electrically connected to the first TFT (170) by a through- hole defined on the insulating substrate (Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Tanaka into the device of Guo/He/Sekine/Lin to put a sensor module on a surface of a substrate opposite two TFTs and connect the sensor to the TFT with a through-hole. The ordinary artisan would have been motivated to modify Guo/He/Sekine/Lin in the manner set forth above for the purpose of “fabricating oxide semiconductor TFTs including oxide semiconductor films having different characteristics (made of different materials) on the same substrate.” (para. 67 of Tanaka)
Response to Arguments
Applicant’s arguments with respect to claims 1, 12, and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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