DETAILED ACTION
This action is responsive to the application No. 17/905,778 filed on September 07, 2022.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The amendment filed on 02/09/2026 responding to the Office action mailed on 01/07/2026, has been entered. The present Office action is made with all the suggested amendments being fully considered. Claims 4-14 and 19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Accordingly, pending in this Office are claims 1, 2, and 4-20.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites that “the third semiconductor region 45 is on the light receiving surface and the side surface of the first semiconductor region 42 near a boundary portion of the pixel 10”.
However, near a boundary portion of pixel 10, the third semiconductor region 45 is not on the side surface of the first semiconductor region 42, it is rather on the side surface of semiconductor region 41. If semiconductor region 41 is being considered as the first semiconductor region, then, regarding claim 1, a multiplication region 47 is formed between semiconductor region 44 and semiconductor region 42, and not between semiconductor region 44 and semiconductor region 41.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 15-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi (US 2019/0181177) in view of Iwata (US 2020/0105804).
Regarding Claim 1, Kobayashi (see, e.g., Fig. 2), teaches a light receiving element, comprising:
a pixel 21 (see, e.g., par. 0116) which includes:
a multiplication region in a region where a first semiconductor region 32 of a first conductivity type (i.e., n-type) and a second semiconductor region 33 of a second conductivity type (i.e., p-type) are joined, wherein the first semiconductor region 32 is opposite to the second semiconductor region 33 (see, e.g., par. 0117), and
a planar region of the second semiconductor region 33 at a position closer to a light receiving surface than the first semiconductor region 32,
a third semiconductor region 34 of the second conductivity type (i.e., p-type) that is a hole accumulation region that surrounds a side surface and a bottom surface of the first semiconductor region 32, wherein
the hole accumulation region is configured to accumulate holes generated by photoelectric conversion (see, e.g., par. 0117).
Kobayashi does not teach that the planar region of the second semiconductor region has a larger area than a planar region of the first semiconductor region and extends to the hole accumulation region at a pixel peripheral portion.
Iwata (see, e.g., Fig. 3), in similar SPAD devices to Kobayashi, on the other hand, teaches that the planar region 104 of the second semiconductor region 103/104 has a larger area than a planar region of the first semiconductor region 101 and extends to the hole accumulation region 202 at a pixel peripheral portion, thus, becoming a potential barrier for the charge photoelectrically converted in the semiconductor region 105, so that the charge is likely to be collected in the semiconductor region 103 (see, e.g., pars. 0050, 0057, 0065).
It would have been obvious to one of ordinary skill in the art at the time of filing to include in Kobayashi’s device, the planar region of the second semiconductor region having a larger area than a planar region of the first semiconductor region and extending to the hole accumulation region at a pixel peripheral portion, as taught by Iwata, so that the planar region becomes a potential barrier for the charge photoelectrically converted and the charge is likely to be collected in the second semiconductor region.
Regarding Claim 15, Kobayashi and Iwata teach all aspects of claim 1. Iwata (see, e.g., Fig. 4A), teaches that a planar shape of the first semiconductor region 101 is a circular shape (see, e.g., par. 0055).
However, this claim limitation is merely considered a change in the shape of the first semiconductor region in Kobayashi’s/Iwata’s device. The specific claimed shape, absent any criticality, is only considered to be an obvious modification of the shape of the first semiconductor region in Kobayashi’s/Iwata’s device30, as the courts have held that changes in shape, without any criticality, are within the level of skill in the art. According to the courts, a particular shape, is nothing more than one among numerous shapes that a person having ordinary skill in the art will find obvious to provide using routine experimentation. See In re Dailey, 149 USPQ 47 (CCPA 1976).
Accordingly, since the applicant has not established the criticality (see next paragraph below) of the claimed circular shape, it would have been obvious to one of ordinary skill in the art at the time of filing to have the claimed shape in Kobayashi’s/Iwata’s device.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed shape or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen shape or upon another variable recited in a claim, the applicant must show that the chosen shape is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
See also Smith v. Nichols, 88 U.S. 112, 118-19 (1874) (a change in form, proportions, or degree “will not sustain a patent”); In re Williams, 36 F.2d 436, 438 (CCPA 1929) (“It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions.”). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007) (identifying “the need for caution in granting a patent based on the combination of elements found in the prior art.”).
Regarding Claim 16, Kobayashi and Iwata teach all aspects of claim 1. Kobayashi is silent with respect to the claim limitation that a diameter of the first semiconductor region is 2 µm or less.
However, this claim limitation is merely considered a change in the diameter of the first semiconductor region in Kobayashi’s/Iwata’s device. The specific claimed diameter, absent any criticality, is only considered to be an obvious modification of the period diameter of the first semiconductor region in Kobayashi/Iwata’s device, as the courts have held that changes in diameter without any criticality, are within the level of skill in the art. According to the courts, a particular diameter is nothing more than one among numerous diameters that a person having ordinary skill in the art will find obvious to provide using routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see next paragraph below) of the claimed diameter, it would have been obvious to one of ordinary skill in the art at the time of filing to have the claimed diameter in Kobayashi’s/Iwata’s device.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed diameter or any unexpected results arising therefrom. Where patentability is said to be based upon a particular chosen diameter or upon another variable recited in a claim, the applicant must show that the chosen diameter is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding Claim 17, Kobayashi and Iwata teach all aspects of claim 1. Kobayashi is silent with respect to the claim limitation that a relative distance in a depth direction of the first semiconductor region and the second semiconductor region is 1000 nm or less.
However, this claim limitation is merely considered a change in the distance in the depth direction of the first semiconductor region and the second semiconductor region in Kobayashi/Iwata’s device.
See also the comments stated above in claim 16 regarding criticality which are considered repeated here.
Regarding Claim 18, Kobayashi and Iwata teach all aspects of claim 1. Iwata (see, e.g., Fig. 3), teaches that an impurity concentration of each of the first semiconductor region 101 and the second semiconductor region 103/104 is 1E+ 16/cm3 or more (see, e.g., pars. 0075, 0077).
However, this claim limitation is merely considered a change in the concentration of the first semiconductor region and the second semiconductor region in Kobayashi’s/Iwata’s device.
See also the comments stated above in claim 16 regarding criticality which are considered repeated here.
Regarding Claim 20, Kobayashi (see, e.g., Figs. 2, 59), teaches a distance measuring system, comprising:
a lighting device 12105 configured to emit irradiation light (see, e.g., pars. 0275-0289); and
a light receiving element 12030 configured to receive reflected light obtained by reflecting the irradiation light by a subject (see, e.g., par. 0275-0289), wherein
the light receiving element 12030 includes
a pixel 21 (see, e.g., par. 0116) which includes:
a multiplication region in a region where a first semiconductor region 32 of a first conductivity type (i.e., n-type) and a second semiconductor region 33 of a second conductivity type (i.e., p-type) are joined, wherein the first semiconductor region 32 is opposite to the second semiconductor region 33 (see, e.g., par. 0117), and
a planar region of the second semiconductor region 33 at a position closer to a light receiving surface than the first semiconductor region 32, wherein
a third semiconductor region 34 of the second conductivity type (i.e., p-type) that is a hole accumulation region that surrounds a side surface and a bottom surface of the first semiconductor region 32, wherein
the hole accumulation region is configured to accumulate holes generated by photoelectric conversion (see, e.g., par. 0117).
Kobayashi does not teach that the planar region of the second semiconductor region has a larger area than a planar region of the first semiconductor region and extends to the hole accumulation region at a pixel peripheral portion.
Iwata (see, e.g., Fig. 3), in similar SPAD devices to Kobayashi, on the other hand, teaches that the planar region 104 of the second semiconductor region 103/104 has a larger area than a planar region of the first semiconductor region 101 and extends to the hole accumulation region 202 at a pixel peripheral portion, thus, becoming a potential barrier for the charge photoelectrically converted in the semiconductor region 105, so that the charge is likely to be collected in the semiconductor region 103 (see, e.g., pars. 0050, 0057, 0065).
It would have been obvious to one of ordinary skill in the art at the time of filing to include in Kobayashi’s device, the planar region of the second semiconductor region having a larger area than a planar region of the first semiconductor region and extending to the hole accumulation region at a pixel peripheral portion, as taught by Iwata, so that the planar region becomes a potential barrier for the charge photoelectrically converted and the charge is likely to be collected in the second semiconductor region.
Response to Arguments
Applicant’s arguments filed on 02/09/2026 with respect to the rejection of claims 1 and 20 have been fully considered but are moot in view of the new grounds of rejection.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Garcés whose telephone number is (571)272-8249. The examiner can normally be reached on M-F 9:00 AM - 5:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Nelson Garces/
Primary Examiner, Art Unit 2814